CN108809294B - Dynamic unit matching circuit - Google Patents
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- CN108809294B CN108809294B CN201811004575.5A CN201811004575A CN108809294B CN 108809294 B CN108809294 B CN 108809294B CN 201811004575 A CN201811004575 A CN 201811004575A CN 108809294 B CN108809294 B CN 108809294B
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Abstract
The invention discloses a dynamic unit matching circuit, which comprises a sequence generating circuit, a multiplexing circuit and a unit array circuit, wherein the sequence generating circuit generates a random sequence signal according to a clock signal transmitted to the sequence generating circuit and outputs the random sequence signal to the multiplexing circuit, the multiplexing circuit comprises a plurality of multiplexers and performs random shift on a set matching signal transmitted to the multiplexing circuit according to the random sequence signal to generate a random matching signal and outputs the random matching signal to the unit array circuit, and the unit array circuit gates unit elements in the unit array circuit according to the random matching signal. By the technical scheme, the deviation of the unit elements in the unit array circuit is averaged, the influence of mismatch on the linearity of the unit elements is reduced, the circuit structure of the dynamic unit matching circuit is simplified, the circuit power consumption is reduced, and the working speed of the circuit is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a dynamic unit matching circuit.
Background
In the chip manufacturing process, due to the uncertainty of each procedure in the manufacturing process, there is a problem that the nominally identical devices have limited mismatching, that is, deviation exists between the actual parameter values and the ideal parameter values of the devices inevitably, and mismatching has a great influence on the matching precision of the components, so that the linearity of the circuit is reduced.
At present, in order to solve the problem of reduced circuit linearity caused by mismatch, a DWA (Dynamic weighted average, dynamic weight average) algorithm or a random DEM (Dynamic element matching, dynamic unit matching) algorithm is often adopted to realize the matching of dynamic units, but the currently used dynamic unit matching algorithm needs to rely on a large number of shift registers, the shift registers internally relate to time sequence driving signals, delay is serious, the internal connection structure of the shift registers is complex, power consumption is high, the shift of the matching signals is realized through the shift registers, and then the matching of the dynamic units is realized, so that the dynamic unit matching structure is complex, delay is serious and power consumption is large.
Disclosure of Invention
In view of this, the invention provides a dynamic unit matching circuit, which makes the deviation of unit elements in a unit array circuit be averaged, realizes the dynamic matching of different unit elements with the same nominal, ensures that each unit element can be utilized averagely, reduces the influence of mismatch problem on the linearity of the unit element, does not need to use a large number of shift registers with complex structure, large power consumption and serious delay to shift the set matching signals so as to realize the matching of the dynamic unit, simplifies the circuit structure of the dynamic unit matching circuit, reduces the power consumption of the dynamic unit matching circuit, and improves the working speed of the dynamic unit matching circuit.
The embodiment of the invention provides a dynamic unit matching circuit, which comprises the following components:
the multi-path selection circuit is respectively and electrically connected with the sequence generation circuit and the unit element array circuit;
the sequence generating circuit is used for generating a random sequence signal according to the clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit;
the multi-path selection circuit comprises a plurality of cascaded selector groups, each selector group comprises a plurality of multi-path selectors, and the multi-path selection circuit is used for randomly shifting a set matching signal transmitted to the multi-path selection circuit according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the cell array circuit;
the cell array circuit is used for gating the cell elements in the cell array circuit according to the random matching signals.
Further, the sequence generating circuit comprises a clock signal input end and a plurality of random signal output ends, and the sequence generating circuit is used for adjusting the output signals of the random signal output ends according to the clock signals transmitted to the clock signal input ends; the output signals of the random signal output ends have randomness, and the output signals of the random signal output ends form the random sequence signals.
Further, the sequence generating circuit comprises a combination logic unit and a cascade multistage shift unit, wherein the combination logic unit comprises a plurality of shift signal input ends and a logic signal output end, and each stage of shift unit comprises a shift clock signal input end, a logic signal input end and a shift signal output end;
all the shift clock signal input ends are electrically connected with the clock signal input end serving as the sequence generating circuit, and the shift signal output end serving as the random signal output end of the sequence generating circuit; the logic signal output end is electrically connected with the logic signal input end of the shifting unit of the first stage, the shifting signal output end is electrically connected with the shifting signal input end in a one-to-one correspondence manner, and the shifting signal output end of the shifting unit of the ith stage is electrically connected with the logic signal input end of the shifting unit of the (i+1) th stage; wherein i is a positive integer;
the combination logic unit is used for randomly selecting a random signal input by the shift signal input end and outputting the random signal through the logic signal output end.
Further, the shift unit includes a flip-flop including a clock signal end, a trigger signal input end, and a trigger signal output end, the clock signal end of the flip-flop being the shift clock signal input end of the shift unit, the trigger signal input end of the flip-flop being the logic signal input end of the shift unit, the trigger signal output end of the flip-flop being the shift signal output end of the shift unit.
Further, the combination logic unit comprises a first logic processor, a second logic processor and a third logic processor, and the sequence generation circuit comprises n cascaded stages of the shift units; wherein n is an integer greater than 2;
the first logic processor comprises two first processing signal input ends and a first processing signal output end, the first processing signal input ends are respectively and correspondingly and electrically connected with the shifting signal output ends of the n-1 level and the n-2 level shifting units, and the first logic processor is used for adjusting the level of the output signals of the first processing signal output ends according to whether the level of the input signals of the two first processing signal input ends is consistent or not;
the second logic processor comprises a plurality of second processing signal input ends and a second processing signal output end, the second processing signal input ends are respectively and correspondingly and electrically connected with the n shift signal output ends, and the second logic processor is used for adjusting the level of the output signal of the second processing signal output end according to whether the level of the input signal of the second processing signal input end is low or not;
the third logic processor comprises two third processing signal input ends and a third processing signal output end, wherein the third processing signal input ends are respectively and electrically connected with the first processing signal output end and the second processing signal output end, the third processing signal output end is used as the logic signal output end of the combination logic unit, and the third logic processor is used for adjusting the level of the output signal of the third processing signal output end according to whether the level of the input signal of the third processing signal input end is low or not.
Further, the multiplexer comprises a plurality of random signal input ends, a plurality of setting signal input ends and a plurality of random matching signal output ends, wherein the random signal input ends are electrically connected with the random signal output ends in a one-to-one correspondence manner;
the multipath selector is used for randomly shifting the set matching signal transmitted to the set matching signal input end according to the random signal input by the random signal input end to generate multipath random matching signals, and outputting the random matching signals through the random matching signal output end.
Further, the multi-path selection circuit is connected with m1 paths of the setting matching signals, each selector group comprises m2 multi-path selectors, and each multi-path selector comprises a selection control signal input end, a selection signal output end and N selection signal input ends;
all the selection control signal input ends of the same selector group are electrically connected with one random signal input end serving as the multiplexing circuit, the selection signal input ends of the first-stage selector group are respectively used as the setting matching signal input ends of the multiplexing circuit, and the selection signal output ends of the last-stage selector group are respectively used as the random matching signal output ends of the multiplexing circuit;
Each path of setting matching signal is transmitted to one selection signal input end of at least N multiplexers of a first-stage selector group, m2 selection signal output ends of a j-stage selector group are randomly and electrically connected with m2 x N selection signal input ends of a j+1stage selector group, and each selection signal output end of the j-stage selector group is electrically connected with one selection signal input end of N multiplexers of the j+1stage selector group; wherein m1, m2 and N are integers greater than 1, and j is a positive integer.
Further, the corresponding electrical connection relationship between the selection signal output terminal of the j-th stage of the selector group and the selection signal input terminal of the j+1-th stage of the selector group is different from the corresponding electrical connection relationship between the selection signal output terminal of the j+1-th stage of the selector group and the selection signal input terminal of the j+2-th stage of the selector group.
Further, the setting matching signal corresponds to a thermometer code;
the selection signal input ends of the first-stage selector group are respectively used as the setting matching signal input ends of the multi-path selection circuit, m2 x N selection signal input ends of the first-stage selector group are randomly connected into m1 paths of setting matching signals, and each path of setting matching signal is transmitted to one selection signal input end of N multi-path selectors of the first-stage selector group; wherein m1 is equal to m2.
Further, the setting matching signal corresponds to a binary code;
the multi-path selection circuit further comprises a decoder, wherein the decoder comprises m1 decoding signal input ends and m2 decoding signal output ends, and the decoding signal input ends are respectively used as the setting matching signal input ends of the multi-path selection circuit;
m1 decoding signal input ends of the decoder are randomly accessed into m1 paths of setting matching signals, m2 decoding signal output ends of the decoder are randomly and electrically connected with m2 x N selection signal input ends of the selector group of the first stage, and each decoding signal output end is connected with one selection signal input end of N multiplexers of the selector group of the first stage; wherein m2 is greater than m1 and m2 is less than or equal to 2 m1 ；
The decoder is used for decoding the setting matching signal input by the decoding signal input end to generate a decoding signal and outputting the decoding signal through the decoding signal output end.
The embodiment of the invention provides a dynamic unit matching circuit, which comprises a sequence generating circuit, a multi-path selecting circuit and a unit array circuit, wherein the multi-path selecting circuit is respectively and electrically connected with the sequence generating circuit and the unit element array circuit and comprises a plurality of cascaded selector groups, and each selector group comprises a plurality of multi-path selectors. The sequence generating circuit is used for generating a random sequence signal according to a clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit, the multi-path selecting circuit is used for carrying out random shift on a set matching signal transmitted to the multi-path selector according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the unit array circuit, the unit array circuit is used for gating unit elements in the unit array circuit according to the random matching signal, namely the multi-path selecting circuit can convert the set matching signal transmitted to the multi-path selecting circuit into the random matching signal according to the random sequence signal, the unit array circuit can carry out multiple random gating on the unit elements according to the random matching signal, so that the deviation of the unit elements in the unit array circuit is averaged, the dynamic matching of different unit elements with the same nominal standard is realized, each unit element can be utilized averagely, the influence of the mismatch problem on the linearity of the unit elements is reduced.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a dynamic unit matching circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a sequence generating circuit according to an embodiment of the present application;
FIG. 3 is a timing diagram of a shift unit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a combinational logic unit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a multiplexing circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a structure of another multiplexing circuit according to an embodiment of the application.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. Throughout this specification, the same or similar reference numerals indicate the same or similar structures, elements or processes. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
The embodiment of the invention provides a dynamic unit matching circuit which comprises a sequence generating circuit, a multiplexing circuit and a unit array circuit, wherein the multiplexing circuit is respectively and electrically connected with the sequence generating circuit and the unit element array circuit and comprises a plurality of cascaded selector groups, and each selector group comprises a plurality of multiplexers. The sequence generating circuit is used for generating a random sequence signal according to the clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit, the multi-path selecting circuit is used for randomly shifting the setting matching signal transmitted to the multi-path selector according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the unit array circuit, and the unit array circuit is used for gating the unit elements in the unit array circuit according to the random matching signal.
In the chip manufacturing process, due to the uncertainty of each procedure in the manufacturing process, there is a problem that the nominally identical devices have limited mismatching, that is, deviation exists between the actual parameter values and the ideal parameter values of the devices inevitably, and mismatching has a great influence on the matching precision of the components, so that the linearity of the circuit is reduced. At present, in order to solve the problem of reduced circuit linearity caused by mismatch, a DWA algorithm or a random DEM algorithm is often adopted to realize the matching of dynamic units, but the currently used dynamic unit matching algorithm is all required to depend on a large number of shift registers, time sequence driving signals are involved in the shift registers, delay is serious, the internal connection structure of the shift registers is complex, power consumption is high, the shift of the matching signals is realized through the shift registers, and then the matching of the dynamic units is realized, so that the dynamic unit matching structure is complex, delay is serious, and power consumption is high.
The dynamic unit matching circuit provided by the embodiment of the invention comprises a sequence generating circuit, a multiplexing circuit and a unit array circuit, wherein the multiplexing circuit is respectively and electrically connected with the sequence generating circuit and the unit element array circuit, the multiplexing circuit comprises a plurality of cascaded selector groups, and each selector group comprises a plurality of multiplexers. The sequence generating circuit is used for generating a random sequence signal according to a clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit, the multi-path selecting circuit is used for carrying out random shift on a set matching signal transmitted to the multi-path selector according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the unit array circuit, the unit array circuit is used for gating unit elements in the unit array circuit according to the random matching signal, namely the multi-path selecting circuit can convert the set matching signal transmitted to the multi-path selecting circuit into the random matching signal according to the random sequence signal, the unit array circuit can carry out multiple random gating on the unit elements according to the random matching signal, so that the deviation of the unit elements in the unit array circuit is averaged, the dynamic matching of different unit elements with the same nominal standard is realized, each unit element can be utilized averagely, the influence of the mismatch problem on the linearity of the unit elements is reduced.
Fig. 1 is a schematic structural diagram of a dynamic unit matching circuit according to an embodiment of the present invention. As shown in fig. 1, the sequence generating circuit 1, the multiplexing circuit 2, and the cell array circuit 3, the multiplexing circuit 2 is electrically connected to the sequence generating circuit 1 and the cell array circuit 3, respectively, the multiplexing circuit 2 includes a plurality of groups of selector groups in cascade, each of which includes a plurality of multiplexers. The sequence generating circuit 1 is configured to generate a random sequence signal based on a clock signal transmitted to the sequence generating circuit 1 and transmit the random sequence signal to the multiplexing selecting circuit 2, the multiplexing selecting circuit 2 is configured to randomly shift a set matching signal transmitted to the multiplexing selecting circuit 2 based on the random sequence signal to generate a random matching signal, and transmit the random matching signal to the cell array circuit 3, and the cell array circuit 3 is configured to gate the cell elements in the cell array circuit 3 based on the random matching signal.
The random signal input end B1 is specific, the clock signal transmitted to the sequence generating circuit 1 can be a periodically-changing pulse signal, the sequence generating circuit 1 generates a random sequence signal under the triggering of the clock signal, and the multiplexing circuit 2 randomly shifts the setting matching signal according to the random sequence signal output by the sequence generating circuit 1 because the random sequence signal generated by the sequence generating circuit 1 has certain randomness, so that the multiplexing setting matching signal is converted into a multiplexing random matching signal. For example, the set matching signal transmitted to the multiple selection circuit 2 at a certain time may be set to form a sequence "00000111", the multiple selection circuit 2 may randomly shift the set matching signal according to the random sequence signal output by the sequence generation circuit 1, the generated random matching signal may form a sequence "00100101", for example, and the cell array circuit 3 gates the cell element corresponding to the valid signal "1" according to the sequence; at the next time, since the random sequence signal outputted from the sequence generating circuit 1 is randomly changed, and the multiplexing circuit 2 randomly shifts the set matching signal according to the random sequence signal, the generated random sequence signal may constitute "10011000", for example, and the cell array circuit 3 gates the cell element corresponding to the valid signal "1" according to the sequence. Accordingly, the random matching signals generated by the multi-path selection circuit 2 have certain randomness, the unit array circuit 3 performs multiple random selections on the unit elements according to the random matching signals, so that deviations of the unit elements in the unit array circuit 3 are averaged, dynamic matching of different unit elements with the same nominal is realized, each unit element can be ensured to be utilized averagely, dynamic matching of the unit elements with the same nominal is effectively realized, and influence of mismatch on linearity of the unit elements is reduced.
As shown in fig. 1, the sequence generating circuit 1 includes a clock signal input terminal A1 and a plurality of random signal output terminals A2, and the sequence generating circuit 1 is configured to adjust an output signal of the random signal output terminal A2 according to the clock signal transmitted to the clock signal input terminal A1. The output signals of the random signal output terminals A2 have randomness, and the output signals of the random signal output terminals A2 form random sequence signals.
Fig. 2 is a schematic diagram of a sequence generating circuit according to an embodiment of the present invention. Referring to fig. 1 and 2, the sequence generating circuit 1 includes a combinational logic unit 11 and a cascade of multi-stage shift units 12, the combinational logic unit 11 including a plurality of shift signal inputs D1 and a logic signal output D2, each of the stage shift units 12 including a shift clock signal input E1, a logic signal input E2 and a shift signal output Q, here exemplarily shown as n-stage shift units 12, the shift signal outputs Q of the n-stage shift units 12 being denoted as Q1 to Qn, respectively. All shift clock signal inputs E1 are electrically connected as clock signal inputs A1 of the sequence generating circuit 1, and shift signal outputs Q are respectively as random signal outputs A2 of the sequence generating circuit 1. The logic signal output end D2 is electrically connected to the logic signal input end E2 of the first stage shift unit 12, the shift signal output end Q is electrically connected to the shift signal input end D1 in a one-to-one correspondence manner, and the shift signal output end Q of the ith stage shift unit 12 is electrically connected to the logic signal input end E2 of the (i+1) th stage shift unit 12, where i is a positive integer, i.e., the shift signal output end Q of the previous stage shift unit 12 is electrically connected to the logic signal input end E2 of the next stage shift unit 12.
The shift unit 12 is configured to shift the logic signal input from the logic signal input terminal E2 according to the clock signal input from the shift clock signal input terminal E1 to generate a shift signal and output the shift signal through the shift signal output terminal Q. As illustrated in fig. 2, the shift unit 12 may include a flip-flop 121, the flip-flop 121 including a clock signal terminal CLK, a trigger signal terminal D, and a trigger signal output terminal Q0, the clock signal terminal CLK of the flip-flop 121 serving as the shift clock signal input terminal E1 of the shift unit 12, the trigger signal input terminal D of the flip-flop 121 serving as the logic signal input terminal E2 of the shift unit 12, and the trigger signal output terminal Q0 of the flip-flop 121 serving as the shift signal output terminal Q of the shift unit 12.
Fig. 3 is a timing chart of the operation of the shift unit according to the embodiment of the present invention. Referring to fig. 2 and 3, the flip-flop 121 may be, for example, a D flip-flop, and the shift unit 12 shifts the shift signal output Q of the flip-flop backward in time sequence with respect to the logic signal input from the logic signal input E2 thereof by the clock signal input from the shift clock signal input E1, taking the rising edge trigger level transition of the clock signal as an example. And the shift signal output end Q of the shift unit 12 of the previous stage is electrically connected with the logic signal input end E2 of the shift unit 12 of the next stage, so that the shift signals output by the shift signal output end Q of each stage of shift register realize stage-by-stage shift.
Fig. 4 is a schematic structural diagram of a combinational logic unit according to an embodiment of the present invention. Referring to fig. 1, 2 and 4, the combinational logic unit 11 includes a first logic processor XOR, a second logic processor NOR1 and a third logic processor NOR2, and the sequence generating circuit 1 includes a cascaded n-stage shift unit 12, where n is an integer greater than 2. The first logic processor XOR includes two first processing signal inputs F1 and one first processing signal output F2, the second logic processor NOR1 includes a plurality of second processing signal inputs G1 and one second processing signal output G2, and the third logic processor NOR2 includes two third processing signal inputs H1 and one third processing signal output H2. The first processing signal input end F1 is electrically connected to the shift signal output end Qn-1 of the n-1 stage shift unit 12 and the shift signal output end Qn-2 of the n-2 stage shift unit 12, respectively, the second processing signal input end G1 is electrically connected to the n shift signal output ends Q1 to Qn, respectively, the third processing signal input end H1 is electrically connected to the first processing signal output end F2 and the second processing signal output end G2, respectively, and the third processing signal output end H2 serves as a logic signal output end D2 of the combinational logic unit 11.
The first logic processor XOR is configured to adjust the level of the output signal of the first processing signal output end F2 according to whether the levels of the input signals of the two first processing signal input ends F1 are consistent, and the first logic processor XOR may include, for example, an exclusive or gate, and adjust the output signal of the first processing signal output end F2 to be a low level when the levels of the input signals of the two first processing signal input ends F1 are consistent, and adjust the output signal of the first processing signal output end F2 to be a high level when the levels of the input signals of the two first processing signal input ends F1 are inconsistent, that is, to be a high level and a low level. The second logic processor NOR1 is configured to adjust the level of the output signal of the second processing signal output terminal G2 according to whether the level of the input signal of the second processing signal input terminal G1 is low, where the second logic processor NOR1 may include, for example, a NOR gate, and adjust the output signal of the second processing signal output terminal G2 to be high when the level of the input signal of the second processing signal input terminal G1 is low, and adjust the output signal of the second processing signal output terminal G2 to be low when the level of the input signal of the second processing signal input terminal G1 is high. The third logic processor NOR2 is configured to adjust the level of the output signal of the third processing signal output terminal H2 according to whether the level of the input signal of the third processing signal input terminal H1 is low, and the third logic processor NOR2 may also be a NOR gate.
Referring to fig. 1 to 4, the combinational logic unit 11 is configured to randomly select a random signal input from the shift signal input terminal D1 and output the random signal through the logic signal output terminal D2. Specifically, the level of the output signal of the first processing signal output terminal F2 of the first logic processor XOR is related to the level of the input signal of each first signal processing input terminal thereof, the level of the output signal of the second processing signal output terminal G2 of the second logic processor NOR1 is related to the level of the input signal of each second signal processing input terminal thereof, and the level of the output signal of the third processing signal output terminal H2 of the third logic processor NOR2 is related to the level of the input signal of each third signal processing input terminal thereof, so that the level of the output signal of the third processing signal output terminal H2 of the third logic processor NOR2 is randomly switched between the high and low levels. The third processing signal output end H2 of the third logic processor NOR2 is used as the logic signal output end D2 of the logic combining circuit, the output logic signal is transmitted to the first stage shift unit 12, the level of the output signal of the third processing signal output end H2 of the third logic processor NOR2 is randomly switched between high and low levels, so that the shift signal output by the shift signal output end Q of each stage shift unit 12 has randomness, the shift signal output by the shift unit 12 corresponds to the random sequence signal generated by the sequence generating circuit 1, and the random sequence signal generated by the sequence generating circuit 1 realizes randomness.
The sequence generating circuit 1 may be a random sequence generating circuit or a pseudo random sequence generating circuit, that is, the random sequence signal generated by the sequence generating circuit 1 may be a completely random sequence signal, or may output the completely random sequence signal periodically, and the effect of outputting the completely random sequence signal may be achieved by extending the period.
It should be noted that, the purpose of using the shift unit 12 in the embodiment of the present invention is to generate a random sequence signal, and a device that implements the same function as the shift register mentioned in the prior art in the embodiment of the present invention is a multiplexing circuit, that is, the embodiment of the present invention uses a multiplexing circuit with a simple structure to replace the shift register in the prior art, so that a large number of shift registers with complex structure, large power consumption and serious delay are not required to be used to shift a set matching signal to implement matching of a dynamic unit, the circuit structure of the dynamic unit matching circuit is simplified, the power consumption of the dynamic unit matching circuit is reduced, and the working speed of the dynamic unit matching circuit is increased.
As shown in fig. 1, the multi-path selection circuit 2 includes a plurality of random signal input terminals B1, a plurality of set matching signal input terminals B2, and a plurality of random matching signal output terminals B3, and the cell array circuit 3 includes a plurality of random matching signal input terminals C1, the random signal input terminals B1 are electrically connected to the random signal output terminals A2, and the random matching signal input terminals C1 are electrically connected to the random matching signal output terminals B3. The multiplexing selection circuit 2 is configured to randomly shift the set matching signal transmitted to the set matching signal input terminal B2 according to the random signal input by the random signal input terminal B1 to generate a multiplexing random matching signal, and output the random matching signal through the random matching signal output terminal B3, and the cell array circuit 3 is configured to gate the cell elements in the cell array circuit 3 according to the random matching signal input by the random matching signal input terminal C1.
Fig. 5 is a schematic structural diagram of a multiplexing circuit according to an embodiment of the present invention. Referring to fig. 1 and 5, the multiplexing circuit 2 is connected to m 1-way setting matching signals, the multiplexing circuit 2 includes cascaded multi-stage selector groups 21, here, only the first three selector groups 21 are exemplarily shown, each of the stage selector groups 21 includes m2 multiplexer muxes, each of the multiplexer muxes includes a selection control signal input terminal J1, a selection signal output terminal J2, and N selection signal input terminals J3. All the selection control signal input terminals J1 of the same selector group 21 are electrically connected to a random signal input terminal B1 of the multiplexing circuit 2, the selection signal input terminals J3 of the first selector group 21 are respectively used as the setting matching signal input terminals B2 of the multiplexing circuit 2, and the selection signal output terminals J2 of the last selector group 21 are respectively used as the random matching signal output terminals B3 of the multiplexing circuit 2.
Each path of setting matching signal is transmitted to a selection signal input terminal J3 of at least N multiplexers MUX of the first-stage selector group 21, m2 selection signal output terminals J2 of the J-th-stage selector group 21 are randomly and electrically connected to m2 x N selection signal input terminals J3 of the j+1th-stage selector group 21, each selection signal output terminal J2 of the J-th-stage selector group 21 is electrically connected to a selection signal input terminal J3 of N multiplexers MUX of the j+1th-stage selector group 21, m1, m2 and N are integers greater than 1, and J is a positive integer. The multiplexer MUX is configured to select one of the selection signal input terminals J3 to be in communication with the selection signal output terminal J2 according to the random sequence signal input from the selection control signal input terminal J1.
Referring to fig. 1 and 5, the number m1 of the setting matching signals to which the multiplexers MUX are connected may be set equal to the number m2 of the multiplexers MUX in each of the selector groups 21, the selection signal input terminals J3 of the first-stage selector group 21 are respectively used as the setting matching signal input terminals B2 of the multiplexing circuit 2, the m2×n selection signal input terminals J3 of the first-stage selector group 21 are randomly connected to the m1 of the setting matching signals, and each of the setting matching signals is transmitted to one of the selection signal input terminals J3 of the N multiplexers MUX of the first-stage selector group 21.
Fig. 5 exemplarily sets m1 and m2 equal to 7, n equal to 2, i.e. exemplarily sets the multiplexing circuit 2 to access 7-way set matching signals, which are marked on the corresponding transmission conductors in the form of D < i >, each group of selectors 21 comprising 7 multiplexers MUX each comprising two selection signal inputs J3, i.e. each multiplexer MUX being a one-out-of-two multiplexer MUX.
Referring to fig. 2 and 5, since all the selection control signal input terminals J1 of the same selector group 21 are electrically connected as one random signal input terminal B1 of the multiplexing circuit 2, the multiplexed shift signals having randomness outputted from the shift signal output terminals Q of the respective stages of the shift units 12 in the sequence generating circuit 1 constitute random sequence signals, and the multiplexer MUX in each selector group 21 selects one of the selection signal input terminals J3 to communicate with the selection signal output terminal J2 according to the corresponding random sequence signal.
The selection signal input terminal J3, which is connected to the selection signal output terminal J2, selected by the multiplexer MUX also has a certain randomness due to the randomness of the random sequence signal. In addition, the m2×n selection signal input terminals J3 of the first-stage selector group 21 are set to randomly access the m 1-path setting matching signal, and the m2 selection signal output terminals J2 of the J-th-stage selector group 21 are electrically connected with the m2×n selection signal input terminals J3 of the j+1th-stage selector group 21 at random, so that the selection control signal for controlling the multiplexer MUX to perform gating action is random, the access of the setting matching signal is random and the connection relation of the adjacent selector groups 21 is random, the multi-stage random selection of the setting matching signal by the multiplexer circuit 2 is realized, and the random shift of the setting matching signal is realized by the multiplexer circuit 2.
Referring to fig. 2 and 5, 14 selection signal input terminals J3 of the first-stage selector group 21 are set to be randomly connected to 7-way setting matching signals D <0> to D <6>, and each-way setting matching signal is transmitted to the selection signal input terminals J3 of two multiplexer muxes of the first-stage selector group 21, i.e., the selection signal input terminals J3 of two multiplexer muxes in the first-stage selector group 21 are randomly connected to one-way setting matching signal D < i >. Meanwhile, 7 selection signal output terminals J2 of the preceding selector set 21 are set to be electrically connected with 14 selection signal input terminals J3 of the following selector set 21 at random, each selection signal output terminal J2 of the preceding selector set 21 is electrically connected with one selection signal input terminal J3 of two multiplexers MUX of the following selector set 21, the first selector set 21 performs random shift on the setting matching signal according to the corresponding random sequence signal to output D <0> to D <6>, fig. 5 only illustrates that the order of the actual D <0> to D <6> is random according to the order of the selection signal output terminals J2 of the first selector set 21, and likewise, the connection of the other adjacent selector sets 21 is satisfied. In this way, it is ensured that the multiplexing selection circuit 2 randomly shifts the multiplexing setting matching signals, and the multiplexing selection circuit 2 can select all the setting matching signals D <0> to D <6> each time in the process of randomly selecting, that is, the random matching signal output from the selection signal output terminal J2 of the last selector group 21 does not lose valid selection bits with respect to the setting matching signals, thereby ensuring that the number of unit elements of the unit array circuit 3 that is selected each time is the same.
As shown in fig. 5, the corresponding electrical connection relationship of the selection signal output terminal J2 of the J-th selector group 21 and the selection signal input terminal J3 of the j+1th selector group 21 may be set to be different from the corresponding electrical connection relationship of the selection signal output terminal J2 of the j+1th selector group 21 and the selection signal input terminal J3 of the j+2th selector group 21. Taking the corresponding connection relationship between the first-stage selector set 21 and the second-stage selector set 21 and the corresponding connection relationship between the second-stage selector set 21 and the third-stage selector set 21 as an example, the corresponding electrical connection between the selection signal output terminals J2 and the selection signal input terminals J3 of different adjacent two-stage selector sets 21 is set to have a certain intersection, so as to increase the randomness of shifting the setting matching signals by the multiplexing circuit 2.
Fig. 6 is a schematic diagram of a structure of another multiplexing circuit according to an embodiment of the invention. Unlike the multiplexing circuit of the configuration shown in fig. 5, the multiplexing circuit 2 of the configuration shown in fig. 6 has a setting matching signal corresponding to a binary code, and the multiplexing circuit further includes a decoder 22, wherein the decoder 22 includes m1 decoding signal input terminals K1 and m2 decoding signal output terminals K2, and the decoding signal input terminals K1 are respectively used as setting matching signal input terminals B2 of the multiplexing circuit 2. M1 decoding signal input terminals K1 of the decoder 22 are randomly connected to m1 paths of setting matching signals, m2 decoding signal output terminals K2 of the decoder 22 are randomly and electrically connected to m2 x N selection signal input terminals J3 of the first-stage selector group 21, each decoding signal output terminal K2 is greater than m1 and m2 is less than or equal to 2 with one selection signal input terminal J3 of N multiplexers MUX of the first-stage selector group 21 m1 . The decoder 22 is configured to decode the setting matching signal input from the decoded signal input terminal K1 to generate a decoded signal and output the decoded signal through the decoded signal output terminal K2.
Specifically, as shown in fig. 6, since the set match signal corresponds to the binary code, the decoder 22 decodes the set match signal and outputs the decoded signal through the decoding signal output terminal K2, that is, decodes the set match signal corresponding to the binary code into the set match signal corresponding to the thermometer code. Fig. 6 exemplarily sets m1 equal to 3 and m2 equal to 7, i.e. decoder 22 accesses 3-way set match signal D<0>To D<2>The decoder 22 may convert the set match signal of the corresponding binary code of at most 3 channels into 8 channels of decoding signals, and fig. 6 schematically sets the decoder 22 to output 7 channels of decoding signals D<0>To D<6>Ensure that m2 is greater than m1 and m2 is less than or equal to 2 m1 And (3) obtaining the product.
The 7 decoding signals D <0> to D <6> outputted from the decoder 22 are randomly transmitted to the 14 selection signal input terminals J3 of the first-stage selector group 21, and each decoding signal is transmitted to the selection signal input terminals J3 of the two multiplexer muxes of the first-stage selector group 21, i.e., the selection signal input terminals J3 of the two multiplexer muxes in the first-stage selector group 21 are randomly connected to one decoding signal D < i >, and the rest of the operation of the multiplexing circuit 2 is similar to that of the multiplexing circuit 2 with the structure shown in fig. 5, and will not be repeated here. The multiplexing circuit 2 having the configuration shown in fig. 6 can also ensure that all the set matching signals D <0> to D <6> can be selected by the multiplexing circuit 2 each time in the process of performing the random selection while ensuring that the set matching signals are subjected to the multi-stage random selection by the multiplexing circuit 2, that is, the random matching signals outputted from the selection signal output terminal J2 of the last selector group 21 do not lose valid selection bits with respect to the set matching signals, thereby ensuring that the number of the unit elements of the unit array circuit 3 selected each time is the same.
It should be noted that, fig. 5 and fig. 6 are only exemplary embodiments of setting the multiplexer MUX as an alternative multiplexer MUX, and the number of the selection signal input terminals J3 of the multiplexer MUX is not limited in the embodiments of the present invention. In addition, fig. 5 and 6 are only exemplary embodiments for setting each selector group 21 to include 7 multiplexers MUX, and the number of multiplexers MUX in the selector group 21 may be limited according to the number of the unit cells to be gated in the unit array circuit 3, which is not limited in the embodiment of the present invention.
The dynamic unit matching circuit provided by the embodiment of the invention comprises a sequence generating circuit, a multiplexing circuit and a unit array circuit, wherein the multiplexing circuit is respectively and electrically connected with the sequence generating circuit and the unit element array circuit, the multiplexing circuit comprises a plurality of cascaded selector groups, and each selector group comprises a plurality of multiplexers. The sequence generating circuit is used for generating a random sequence signal according to a clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit, the multi-path selecting circuit is used for carrying out random shift on a set matching signal transmitted to the multi-path selector according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the unit array circuit, the unit array circuit is used for gating unit elements in the unit array circuit according to the random matching signal, namely the multi-path selecting circuit can convert the set matching signal transmitted to the multi-path selecting circuit into the random matching signal according to the random sequence signal, the unit array circuit can carry out multiple random gating on the unit elements according to the random matching signal, so that the deviation of the unit elements in the unit array circuit is averaged, the dynamic matching of different unit elements with the same nominal standard is realized, each unit element can be utilized averagely, the influence of the mismatch problem on the linearity of the unit elements is reduced.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A dynamic cell matching circuit, comprising:
the multi-path selection circuit is respectively and electrically connected with the sequence generation circuit and the unit element array circuit;
the sequence generating circuit is used for generating a random sequence signal according to the clock signal transmitted to the sequence generating circuit and transmitting the random sequence signal to the multi-path selecting circuit;
the multi-path selection circuit comprises a plurality of cascaded selector groups, each selector group comprises a plurality of multi-path selectors, and the multi-path selection circuit is used for randomly shifting a set matching signal transmitted to the multi-path selection circuit according to the random sequence signal to generate a random matching signal and transmitting the random matching signal to the cell array circuit;
The unit array circuit is used for gating unit elements in the unit array circuit according to the random matching signals;
the clock signal transmitted to the sequence generating circuit is a periodically varying pulse signal.
2. The dynamic cell matching circuit of claim 1, wherein said sequence generation circuit comprises a clock signal input and a plurality of random signal outputs, said sequence generation circuit for adjusting an output signal of said random signal outputs based on said clock signal transmitted to said clock signal input; the output signals of the random signal output ends have randomness, and the output signals of the random signal output ends form the random sequence signals.
3. The dynamic cell matching circuit of claim 2, wherein said sequence generation circuit comprises a combinational logic unit and a cascaded multi-stage shift unit, said combinational logic unit comprising a plurality of shift signal inputs and a logic signal output, each stage of said shift unit comprising a shift clock signal input, a logic signal input and a shift signal output;
all the shift clock signal input ends are electrically connected with the clock signal input end serving as the sequence generating circuit, and the shift signal output end serving as the random signal output end of the sequence generating circuit; the logic signal output end is electrically connected with the logic signal input end of the shifting unit of the first stage, the shifting signal output end is electrically connected with the shifting signal input end in a one-to-one correspondence manner, and the shifting signal output end of the shifting unit of the ith stage is electrically connected with the logic signal input end of the shifting unit of the (i+1) th stage; wherein i is a positive integer;
The combination logic unit is used for randomly selecting a random signal input by the shift signal input end and outputting the random signal through the logic signal output end.
4. The dynamic cell matching circuit of claim 3, wherein said shift cell comprises a flip-flop, said flip-flop comprising a clock signal terminal, a trigger signal input terminal, and a trigger signal output terminal, said clock signal terminal of said flip-flop being said shift clock signal input terminal of said shift cell, said trigger signal input terminal of said flip-flop being said logic signal input terminal of said shift cell, said trigger signal output terminal of said flip-flop being said shift signal output terminal of said shift cell.
5. The dynamic unit matching circuit of claim 3 or 4, wherein said combinational logic unit comprises a first logic processor, a second logic processor, and a third logic processor, said sequence generation circuit comprising n cascaded stages of said shift units; wherein n is an integer greater than 2;
the first logic processor comprises two first processing signal input ends and a first processing signal output end, the first processing signal input ends are respectively and correspondingly and electrically connected with the shifting signal output ends of the n-1 level and the n-2 level shifting units, and the first logic processor is used for adjusting the level of the output signals of the first processing signal output ends according to whether the level of the input signals of the two first processing signal input ends is consistent or not;
The second logic processor comprises a plurality of second processing signal input ends and a second processing signal output end, the second processing signal input ends are respectively and correspondingly and electrically connected with the n shift signal output ends, and the second logic processor is used for adjusting the level of the output signal of the second processing signal output end according to whether the level of the input signal of the second processing signal input end is low or not;
the third logic processor comprises two third processing signal input ends and a third processing signal output end, wherein the third processing signal input ends are respectively and electrically connected with the first processing signal output end and the second processing signal output end, the third processing signal output end is used as the logic signal output end of the combination logic unit, and the third logic processor is used for adjusting the level of the output signal of the third processing signal output end according to whether the level of the input signal of the third processing signal input end is low or not.
6. The dynamic cell matching circuit of claim 2, wherein the multiplexer comprises a plurality of random signal inputs, a plurality of set match signal inputs, and a plurality of random match signal outputs, the random signal inputs being electrically connected to the random signal outputs in a one-to-one correspondence;
The multipath selector is used for randomly shifting the set matching signal transmitted to the set matching signal input end according to the random signal input by the random signal input end to generate multipath random matching signals, and outputting the random matching signals through the random matching signal output end.
7. The dynamic cell matching circuit of claim 6, wherein said multiplexing circuit taps m1 of said set matching signals, each stage of said selector bank comprising m2 multiplexers, each of said multiplexers comprising a select control signal input, a select signal output, and N select signal inputs;
all the selection control signal input ends of the same selector group are electrically connected with one random signal input end serving as the multiplexing circuit, the selection signal input ends of the first-stage selector group are respectively used as the setting matching signal input ends of the multiplexing circuit, and the selection signal output ends of the last-stage selector group are respectively used as the random matching signal output ends of the multiplexing circuit;
each path of setting matching signal is transmitted to one selection signal input end of at least N multiplexers of a first-stage selector group, m2 selection signal output ends of a j-stage selector group are randomly and electrically connected with m2 x N selection signal input ends of a j+1stage selector group, and each selection signal output end of the j-stage selector group is electrically connected with one selection signal input end of N multiplexers of the j+1stage selector group; wherein m1, m2 and N are integers greater than 1, and j is a positive integer.
8. The dynamic cell matching circuit of claim 7, wherein the corresponding electrical connection of said select signal output of said selector bank at a j-th stage to said select signal input of said selector bank at a j-th+1-th stage is different from the corresponding electrical connection of said select signal output of said selector bank at a j-th+1-th stage to said select signal input of said selector bank at a j-th+2-th stage.
9. The dynamic cell matching circuit of claim 7 or 8, wherein the set matching signal corresponds to a thermometer code;
the selection signal input ends of the first-stage selector group are respectively used as the setting matching signal input ends of the multi-path selection circuit, m2 x N selection signal input ends of the first-stage selector group are randomly connected into m1 paths of setting matching signals, and each path of setting matching signal is transmitted to one selection signal input end of N multi-path selectors of the first-stage selector group; wherein m1 is equal to m2.
10. The dynamic cell matching circuit according to claim 7 or 8, wherein the set matching signal corresponds to a binary code;
the multi-path selection circuit further comprises a decoder, wherein the decoder comprises m1 decoding signal input ends and m2 decoding signal output ends, and the decoding signal input ends are respectively used as the setting matching signal input ends of the multi-path selection circuit;
M1 decoding signal input ends of the decoder are randomly accessed into m1 paths of setting matching signals, m2 decoding signal output ends of the decoder are randomly and electrically connected with m2 x N selection signal input ends of the selector group of the first stage, and each decoding signal output end is connected with one selection signal input end of N multiplexers of the selector group of the first stage; wherein m2 is greater than m1 and m2 is less than or equal to 2 m1 ；
The decoder is used for decoding the setting matching signal input by the decoding signal input end to generate a decoding signal and outputting the decoding signal through the decoding signal output end.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323113A (en) * | 2001-01-19 | 2001-11-21 | 深圳市中兴集成电路设计有限责任公司 | Pseudo-random noise sequence generator with simple structure |
| CN1323105A (en) * | 2001-03-19 | 2001-11-21 | 深圳市中兴集成电路设计有限责任公司 | Correlator |
| CN1719741A (en) * | 2005-07-28 | 2006-01-11 | 上海大学 | Spread spectrum communicatoion system and non-centre wireless network for implementing CDMA by single different phase sequence of spread spectrum code |
| CN101213737A (en) * | 2005-07-01 | 2008-07-02 | Dsp集团公司 | Analog to digital converter with ping-pong architecture |
| CN101567692A (en) * | 2009-03-30 | 2009-10-28 | 东南大学 | Method for matching parallel high-speed dynamic elements |
| CN103166604A (en) * | 2013-01-29 | 2013-06-19 | 嘉兴联星微电子有限公司 | On-chip clock generating circuit with lower power consumption |
| CN103684452A (en) * | 2013-12-17 | 2014-03-26 | 华为技术有限公司 | Matching method and device for dynamic cells |
| CN104051009A (en) * | 2014-06-20 | 2014-09-17 | 中国科学院微电子研究所 | Gating circuit and gating method of resistance transformation random access memory RRAM |
| CN106303312A (en) * | 2016-08-12 | 2017-01-04 | 中国科学院上海高等研究院 | Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor |
| CN208904975U (en) * | 2018-08-30 | 2019-05-24 | 北京神经元网络技术有限公司 | A kind of dynamic cell match circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7301541B2 (en) * | 1995-08-16 | 2007-11-27 | Microunity Systems Engineering, Inc. | Programmable processor and method with wide operations |
| US9137084B2 (en) * | 2013-08-02 | 2015-09-15 | Intel Corporation | Digitally controlled edge interpolator (DCEI) for digital to time converters (DTC) |
-
2018
- 2018-08-30 CN CN201811004575.5A patent/CN108809294B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323113A (en) * | 2001-01-19 | 2001-11-21 | 深圳市中兴集成电路设计有限责任公司 | Pseudo-random noise sequence generator with simple structure |
| CN1323105A (en) * | 2001-03-19 | 2001-11-21 | 深圳市中兴集成电路设计有限责任公司 | Correlator |
| CN101213737A (en) * | 2005-07-01 | 2008-07-02 | Dsp集团公司 | Analog to digital converter with ping-pong architecture |
| CN1719741A (en) * | 2005-07-28 | 2006-01-11 | 上海大学 | Spread spectrum communicatoion system and non-centre wireless network for implementing CDMA by single different phase sequence of spread spectrum code |
| CN101567692A (en) * | 2009-03-30 | 2009-10-28 | 东南大学 | Method for matching parallel high-speed dynamic elements |
| CN103166604A (en) * | 2013-01-29 | 2013-06-19 | 嘉兴联星微电子有限公司 | On-chip clock generating circuit with lower power consumption |
| CN103684452A (en) * | 2013-12-17 | 2014-03-26 | 华为技术有限公司 | Matching method and device for dynamic cells |
| CN104051009A (en) * | 2014-06-20 | 2014-09-17 | 中国科学院微电子研究所 | Gating circuit and gating method of resistance transformation random access memory RRAM |
| CN106303312A (en) * | 2016-08-12 | 2017-01-04 | 中国科学院上海高等研究院 | Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor |
| CN208904975U (en) * | 2018-08-30 | 2019-05-24 | 北京神经元网络技术有限公司 | A kind of dynamic cell match circuit |
Non-Patent Citations (2)
| Title |
|---|
| High speed true random number generator with a new structure of coarse-tuning PDL in FPGA;Hongzhen Fang;Pengjun Wang;Xu Cheng;Keji Zhou;;Journal of Semiconductors(第03期);622-627 * |
| 基于FPGA的全数字化2DPSK调制系统的实现;李冉;贺绍林;徐善永;;通信技术(第01期);334-339 * |
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