CN106133902B - 半导体封装中具有焊球连接的正面朝上基板集成 - Google Patents

半导体封装中具有焊球连接的正面朝上基板集成 Download PDF

Info

Publication number
CN106133902B
CN106133902B CN201580014299.9A CN201580014299A CN106133902B CN 106133902 B CN106133902 B CN 106133902B CN 201580014299 A CN201580014299 A CN 201580014299A CN 106133902 B CN106133902 B CN 106133902B
Authority
CN
China
Prior art keywords
substrate
laminated substrate
group
semiconductor packages
encapsulation welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580014299.9A
Other languages
English (en)
Other versions
CN106133902A (zh
Inventor
D·D·金
J·金
C·左
C·H·尹
M·F·维纶茨
R·P·米库尔卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106133902A publication Critical patent/CN106133902A/zh
Application granted granted Critical
Publication of CN106133902B publication Critical patent/CN106133902B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/1003—Non-printed inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10719—Land grid array [LGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/4902—Electromagnet, transformer or inductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

半导体封装中具有焊球连接的正面朝上基板集成。系统和方法涉及半导体封装200，其包括第一基板或具有形成在玻璃基板202的正面上的无源组件204以及第一组一个或多个封装焊盘203的2D玻璃上无源器件(POG)结构。该半导体封装还包括第二或层压基板207，其具有形成在第二或层压基板的正面上的第二组一个或多个封装焊盘205。焊球206被滴落、配置成使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构被正面朝上置于第二或层压基板的正面上。印刷电路板(PCB)208可耦合至第二或层压基板的底侧。

Description

半导体封装中具有焊球连接的正面朝上基板集成
公开领域
所公开的实施例涉及具有使用焊球的倒装基板附连的半导体封装。更具体地，示例性实施例涉及使用焊球将倒装或正面朝上的2D玻璃上封装(POG)结构附连至层压基板并将该层压基板附连至印刷电路板(PCB)以减少电感构建和Q因数降级。
背景技术
半导体封装通常涉及集成在基板(诸如玻璃基板)上的一个或多个半导体管芯。基板随后被附连至封装基底，诸如印刷电路板(PCB)。无源组件(诸如电容器和电感器)通常形成在基板的一侧(诸如底侧)上。基板可面朝下地附连至PCB，以使得包括无源组件的底侧最靠近PCB。包括焊球的球栅阵列(BGA)可被用于形成基板与PCB之间的连接和附连。可用本领域已知的焊线和焊盘来形成PCB与基板之间的电连接。
例如，参照图1，解说了常规半导体封装100的侧视图。封装100包括玻璃基板102，该玻璃基板102具有无源组件——附连在玻璃基板102的底面上的电感器104。玻璃基板与电感器104的组合被称为二维(2D)玻璃上无源器件(POG)。如所解说的，包括玻璃基板102和电感器104的2D POG使用形成BGA 106的焊球在常规面朝下配置中附连至PCB 108。在该配置中，在电感器与PCB 108之间形成不期望的高电感。具体而言，电感器104与PCB 108的接地平面110之间的间隔112与所形成的显著高电感干扰有关。接地平面110是连接到电接地的导电表面。例如，接地平面110可以是大面积铜箔，其连接到PCB 108的接地端子(未解说)，并且充当来自PCB 108上集成的各种组件的电流的接地或返回路径。
为使不期望的电感干扰和伴随的Q因数降级最小化，有必要将间隔112维持在尽可能高的距离。用于形成封装100的常规办法依赖BGA 106提供必要的间隔112。然而，BGA 106并不是很适合于满足这种需求。难以在形成BGA 106的各种焊球间达成一致且期望的高度。这些焊球也往往非常易受回流降级的影响。此外，在操作过程中，由于半导体封装中常见的高热和高压，焊球的退化可能导致PCB 108上的2D POG的崩溃。
即使这些电感器和无源组件被放置在半导体基板的相对侧上，在倒装(或倒装芯片或正面朝上)配置(未解说，其中电感器104例如形成在玻璃基板102的顶侧)中，焊线也常规地被用于形成电连接。焊线引入高电阻，尤其是随着半导体管芯复杂性的增加。焊线还往往是昂贵且不稳定的。
因此，本领域需要避免上述问题的高效且可靠的半导体封装(诸如2D POG结构)集成。
概述
示例性实施例涉及具有使用焊球的倒装基板附连的半导体封装。更具体地，示例性实施例涉及使用焊球将倒装或正面朝上的第一基板(诸如2D玻璃上封装(POG)结构)附连至第二基板(诸如层压基板)以及将第二/层压基板附连至印刷电路板(PCB)以减少电感构建和Q因数降级。
例如，一示例性实施例涉及一种半导体封装，包括：2D玻璃上无源器件(POG)结构，其具有形成在玻璃基板的正面上的无源组件和第一组一个或多个封装焊盘；层压基板，其具有形成在该层压基板的正面上的第二组一个或多个封装焊盘；以及焊球，其被配置成使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中该2D POG结构被正面朝上置于层压基板的正面上。
另一示例性实施例涉及一种半导体封装，包括：第一基板，其包括形成在第一基板的正面上的第一组一个或多个封装焊盘；第二基板，其具有形成在第二基板的正面上的第二组一个或多个封装焊盘；以及焊球，其被配置成使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板被正面朝上置于第二基板的正面上。
另一示例性实施例涉及一种形成半导体封装的方法，该方法包括：形成具有集成在玻璃基板的正面上的无源组件的2D玻璃上无源器件(POG)结构；在玻璃基板的正面上形成第一组一个或多个封装焊盘；形成层压基板，该层压基板的正面上具有第二组一个或多个封装焊盘；将2D POG结构正面朝上置于该层压基板上；以及用焊球使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触。
又一示例性实施例涉及一种半导体封装，包括：第一基板，其包括形成在第一基板的正面上的第一组一个或多个封装焊盘；第二基板，其具有形成在第二基板的正面上的第二组一个或多个封装焊盘；以及用于使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触的装置，其中第一基板被正面朝上置于第二基板的正面上。
附图简述
给出附图以帮助各种实施例的描述，并且提供这些附图仅仅是为了解说实施例而非对其进行限制。
图1解说了包括形成在PCB上的2D POG结构的常规面朝下半导体封装。
图2A-C解说了具有使用焊球附连至层压基板的倒装或正面朝上的2DPOG结构的示例性半导体封装。
图3解说了形成具有使用焊球附连至层压基板的倒装或正面朝上的2DPOG结构的示例性半导体封装的方法的流程图。
详细描述
在以下针对具体实施例的描述和相关附图中公开了各种实施例的各方面。可以设计替换实施例而不会脱离本发明的范围。另外，各种实施例的众所周知的元素将不被详细描述或将被省去以免湮没各种实施例的相关细节。
措辞“示例性”在本文中用于表示“用作示例、实例或解说”。本文中描述为“示例性”的任何实施例不必被解释为优于或胜过其他实施例。同样，术语“实施例”并不要求所有实施例都包括所讨论的特征、优点、或工作模式。
本文所使用的术语仅出于描述特定实施例的目的，而并不旨在限定各实施例。如本文所使用的，单数形式的“一”、“某”和“该”旨在也包括复数形式，除非上下文另有明确指示。还将理解，术语“包括”、“具有”、“包含”和/或“含有”在本文中使用时指明所陈述的特征、整数、步骤、操作、元素、和/或组件的存在，但并不排除一个或多个其他特征、整数、步骤、操作、元素、组件和/或其群组的存在或添加。
示例性实施例包括克服了常规封装的上述不足的封装结构。一般而言，示例性方面涉及连接两个半导体基板的系统和方法。例如，第一基板和第二基板可按倒装布置堆叠，其中这两个基板皆正面朝上。第一基板可包括形成在第一基板的第一侧(也被称为正面或顶侧)上的一个或多个半导体管芯和/或无源组件。焊盘(诸如BGA焊盘)可形成在第一基板的正面上。具体地，第一组焊盘可形成在第一基板正面的侧边或边界处。可通过第一组焊盘来建立至第一基板正面上的组件的电连接。
第二基板具有比第一基板更大的横向面积。第一基板堆叠在第二基板上，以使得第一基板覆盖第二基板正面上的内部区域同时使第二基板正面的侧边或外边界未被覆盖。第二组焊盘形成在第二基板的外边界或侧边上。
焊球滴落在第一基板的外边缘上，以使得这些焊球接触第一组焊盘和第二组焊盘两者。这些焊球不仅用于附连，而且还用于分别通过第一和第二组焊盘来形成第一基板与第二基板之间的电连接。在一些情形中，可形成通孔(诸如，基于第二基板由硅还是玻璃制成，分别为穿硅通孔或穿玻通孔)以将第二组焊盘连接至第二基板的相对面、第二表面或底面上的第三组焊盘。第三组焊盘可连接至任何合适的外部半导体封装元件，诸如PCB。因此，示例性实施例的各方面可涉及在两个半导体基板之间的正面朝上堆叠配置中通过焊球提供电连接和机械连接。因此，示例性实施例可避免先前讨论的焊线和相关缺陷。
此外，在这些示例性方面，第一基板的正面至少通过第一基板的材料和厚度与第二基板分隔开。由此，形成在第一基板正面上的无源组件与第二基板的正面以及附连至第二基板的相对侧的其他组件(诸如PCB)充分绝缘且分隔开，由此避免或减轻电感干扰和Q因数降级。
在一些示例性实施例中，可从以上各方面中讨论的第一基板形成2D POG，并且第二基板可被形成为层压基板。以下参照图2A-C讨论这些示例性实施例，其中解说了与封装结构200的逐步形成有关的侧视图。
首先参照图2A，解说了第一基板。第一基板被示为包括2D集成无源器件(IPD)POG，其具有玻璃基板202以及在玻璃基板202正面(或顶侧或第一侧)上的电感器204。由于示例性配置，玻璃基板202无需由增加的厚度形成以避免电感效应，而是可被减薄到约50-100um。POG焊盘203形成在玻璃基板202正面的侧边上。
继续参照图2A，第二基板可作为层压基板207来提供。层压基板207的横向面积大于玻璃基板202的横向面积。可在层压基板207的第一侧(或顶侧或正面)的侧边或外边缘上提供封装焊盘205。封装焊盘205可以是BGA焊盘。可在层压基板207的相对侧(或底侧或第二侧)的相应外边缘上形成面栅阵列(LGA)封装焊盘或LGA焊盘211。贯穿通孔209可形成在层压基板207内以连接封装焊盘205和LGA焊盘211。在一些方面，贯穿通孔209可以是穿玻通孔(TGV)。
现在参照图2B，具有电感器204的玻璃基板202被正面朝上地或在倒装配置中被置于层压基板207正面上的中央或内部区域内，以使得封装焊盘205围绕玻璃基板202或位于玻璃基板202的侧面。滴落或形成足够大小的焊球206，以使得焊球206接触玻璃基板202正面上的BGA焊盘203以及层压基板207正面上的封装焊盘205。以此方式，焊球206提供封装焊盘205与BGA焊盘203之间的电连接。焊球206还提供用于将玻璃基板202附连在层压基板207上的机械连接或装置。如将领会的，焊球206的示例性焊球结构避免了对常规地在倒装封装设计中用于形成电连接的不期望、昂贵且时常不稳定的焊线的需求。具有焊球连接或焊球附连的示例性配置也启用层压基板207，以便提供针对不同引脚配置的快速适应性，这在使用焊线的情况下或许是不可能。
参照图2C，封装结构200被示为集成在PCB 208上。具体地，具有经由焊球206附连的玻璃基板202的层压基板207附连至PCB 208。可在PCB 208的正面(或第一侧或顶侧)的外边缘处提供焊盘213，并且焊盘213可与层压基板207的相对侧上的LGA焊盘211对齐。可通过将LGA焊盘211与焊盘213接触来实现层压表面207与PCB 208的附连。如将领会的，PCB的接地平面210通过间隔212与玻璃基板202正面上的电感器204分隔开，该间隔212显著大于在参照图1所描述的常规封装结构100中所观察到的间隔112。由此，在PCB 208的正面与电感器204之间构建的电感效应以及封装结构200的相关Q因数降级被显著减小。
封装结构200的又一有益方面源自于示例性正面朝上配置，其中电感器204暴露在空气中或不受妨碍结构(诸如在图1的电感器104的情形中的PCB 108)的影响。玻璃基板202上的电感器204的这种2D POG配置受益于高品质磁介质——空气，同时电感器的磁场在顶侧或第一侧不被阻塞。
虽然在一些情形中层压基板207的相对侧或底侧可能引起细微的电感，但是层压基板的射频(RF)性质已知优于面朝下或倒装封装结构的RF性质。因此可以看出，在图2A-C的示例性封装结构200中存在层压基板207减轻了电感干扰和Q因数降级。在一些情形中，示例性封装结构200可达成与本领域已知的昂贵三维(3D)封装结构的性能水平相当的性能水平，但成本显著更低。
尽管未显式地解说，但在一些示例性实施例中有可能提供模塑以便覆盖示例性2DPOG结构正面上的无源组件。这样的模塑将提供若干功能，包括保护无源组件和2D POG结构、以及在示例性封装结构上启用激光标记。如本领域已知的，此类激光标记可被用于标识和分档目的。
将领会，各实施例包括用于执行本文中所公开的过程、功能和/或算法的各种方法。例如，如图4所解说的，一实施例可包括一种形成半导体封装(例如，封装结构200)的方法，该方法包括：形成具有集成在玻璃基板(例如，玻璃基板202)的正面上的无源组件(例如，电感器204)的2D玻璃上无源器件(POG)结构——框302；在玻璃基板的正面上形成第一组一个或多个封装焊盘(例如，POG焊盘203)——框304；形成层压基板(例如，层压基板207)，其中在层压基板的正面上具有第二组一个或多个封装焊盘(例如，封装焊盘205)——框306；将2D POG结构正面朝上置于层压基板上——框308；以及用焊球(例如，焊球206)使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触——框310。
本领域技术人员将领会，信息和信号可使用各种不同技术和技艺中的任何一种来表示。例如，贯穿上面描述始终可能被述及的数据、指令、命令、信息、信号、位(比特)、码元、和码片可由电压、电流、电磁波、磁场或磁粒子、光场或光粒子、或其任何组合来表示。
此外，本领域技术人员将领会，结合本文中所公开的实施例描述的各种解说性逻辑块、模块、电路、和算法步骤可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这一可互换性，各种解说性组件、块、模块、电路、以及步骤在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体系统的设计约束。技术人员对于每种特定应用可用不同的方式来实现所描述的功能性，但这样的实现决策不应被解读成导致脱离了本发明的范围。
结合本文中所公开的实施例描述的方法、序列和/或算法可直接在硬件中、在由处理器执行的软件模块中、或者在这两者的组合中体现。软件模块可驻留在RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM或者本领域中所知的任何其他形式的存储介质中。示例性存储介质耦合到处理器以使得该处理器能从/向该存储介质读写信息。在替换方案中，存储介质可以被整合到处理器。
因此，本发明的一实施例可包括实施用于形成具有在倒装配置中用焊球附连的2D集成无源器件的封装结构的方法的计算机可读介质。相应地，本发明并不限于所解说的示例且任何用于执行本文所描述的功能性的手段均被包括在本发明的实施例中。
尽管上述公开示出了本发明的解说性实施例，但是应当注意到，在其中可作出各种更换和改动而不会脱离如所附权利要求定义的本发明的范围。根据本文中所描述的本发明实施例的方法权利要求的功能、步骤和/或动作不必按任何特定次序来执行。此外，尽管本发明的要素可能是以单数来描述或主张权利的，但是复数也是已料想了的，除非显式地声明了限定于单数。

Claims (13)

1.一种半导体封装，包括：
2D玻璃上无源器件(POG)结构，其具有形成在玻璃基板的正面上的无源组件和第一组一个或多个封装焊盘；
层压基板，其具有形成在所述层压基板的正面上的第二组一个或多个封装焊盘；以及
焊球，其被配置成使所述第一组一个或多个封装焊盘与所述第二组一个或多个封装焊盘接触，其中所述2D POG结构被正面朝上置于所述层压基板的正面上。
2.如权利要求1所述的半导体封装，其特征在于，进一步包括印刷电路板(PCB)，其中所述PCB耦合至所述层压基板的底侧。
3.如权利要求2所述的半导体封装，其特征在于，所述PCB通过形成在所述层压基板的底侧上的面栅阵列(LGA)封装焊盘耦合至所述层压基板的底侧。
4.如权利要求3所述的半导体封装，其特征在于，所述无源组件通过所述层压基板和所述玻璃基板与所述PCB的接地平面分隔开。
5.如权利要求3所述的半导体封装，其特征在于，所述层压基板的底侧上的所述LGA封装焊盘通过通孔耦合至形成在所述层压基板的正面上的所述第二组一个或多个封装焊盘。
6.如权利要求1所述的半导体封装，其特征在于，进一步包括形成在所述无源组件上的模塑，其中所述模塑被配置成保护所述无源组件以及启用激光标记。
7.如权利要求1所述的半导体封装，其特征在于，所述无源组件为电感器。
8.一种形成半导体封装的方法，所述方法包括：
形成具有集成在玻璃基板的正面上的无源组件的2D玻璃上无源器件(POG)结构；
在玻璃基板的正面上形成第一组一个或多个封装焊盘；
形成层压基板，所述层压基板的正面上具有第二组一个或多个封装焊盘；
将所述2D POG结构正面朝上置于所述层压基板上；以及
用焊球使所述第一组一个或多个封装焊盘与所述第二组一个或多个封装焊盘接触。
9.如权利要求8所述的方法，其特征在于，进一步包括通过所述层压基板的底侧上的面栅阵列(LGA)封装焊盘将印刷电路板(PCB)附连至所述层压基板的底侧。
10.如权利要求9所述的方法，其特征在于，进一步包括通过通孔将所述层压基板的底侧上的所述LGA封装焊盘连接到形成在所述层压基板的正面上的所述第二组一个或多个封装焊盘。
11.如权利要求8所述的方法，其特征在于，进一步包括在所述无源组件上形成模塑以用于保护所述无源组件以及启用激光标记。
12.如权利要求8所述的方法，其特征在于，所述无源组件为电感器。
13.一种半导体封装，包括：
2D玻璃上无源器件(POG)结构，其具有形成在玻璃基板的正面上的无源组件和第一组一个或多个封装焊盘；
层压基板，其具有形成在所述层压基板的正面上的第二组一个或多个封装焊盘；以及
用于使所述第一组一个或多个封装焊盘与所述第二组一个或多个封装焊盘接触的装置，其中所述2D POG结构被正面朝上置于所述层压基板的正面上。
CN201580014299.9A 2014-03-20 2015-03-11 半导体封装中具有焊球连接的正面朝上基板集成 Active CN106133902B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/220,913 US9468098B2 (en) 2014-03-20 2014-03-20 Face-up substrate integration with solder ball connection in semiconductor package
US14/220,913 2014-03-20
PCT/US2015/020021 WO2015142591A1 (en) 2014-03-20 2015-03-11 Face-up substrate integration with solder ball connection in semiconductor package

Publications (2)

Publication Number Publication Date
CN106133902A CN106133902A (zh) 2016-11-16
CN106133902B true CN106133902B (zh) 2018-08-31

Family

ID=52706304

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580014299.9A Active CN106133902B (zh) 2014-03-20 2015-03-11 半导体封装中具有焊球连接的正面朝上基板集成

Country Status (6)

Country Link
US (2) US9468098B2 (zh)
EP (1) EP3120674B1 (zh)
JP (1) JP2017510075A (zh)
KR (1) KR20160135186A (zh)
CN (1) CN106133902B (zh)
WO (1) WO2015142591A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469190B2 (en) 2016-03-15 2022-10-11 Intel Corporation Parasitic-aware integrated substrate balanced filter and apparatus to achieve transmission zeros
WO2017160281A1 (en) 2016-03-15 2017-09-21 Intel Corporation Integrated substrate communication frontend
US9930783B2 (en) 2016-03-24 2018-03-27 Qualcomm Incorporated Passive device assembly for accurate ground plane control
US10044390B2 (en) 2016-07-21 2018-08-07 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
US9780048B1 (en) * 2016-08-03 2017-10-03 Qualcomm Incorporated Side-assembled passive devices
US10361149B2 (en) 2016-08-10 2019-07-23 Qualcomm Incorporated Land grid array (LGA) packaging of passive-on-glass (POG) structure
US9807882B1 (en) * 2016-08-17 2017-10-31 Qualcomm Incorporated Density-optimized module-level inductor ground structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641874A (zh) * 2004-01-13 2005-07-20 三星电子株式会社 多芯片封装
CN101233614A (zh) * 2005-09-06 2008-07-30 松下电器产业株式会社 电容器装载型半导体器件
CN103077933A (zh) * 2011-10-26 2013-05-01 马克西姆综合产品公司 三维的芯片到晶圆级集成

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118200A (ja) * 2000-10-05 2002-04-19 Fujitsu Ltd 半導体パッケージ
JP2003163459A (ja) * 2001-11-26 2003-06-06 Sony Corp 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。
US7414505B2 (en) 2003-05-13 2008-08-19 Samsung Electronics Co., Ltd. High frequency inductor having low inductance and low inductance variation and method of manufacturing the same
JP2005050882A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
KR100854031B1 (ko) 2006-07-28 2008-08-26 삼성전자주식회사 적층형 비지에이 반도체 패키지
JP2010109269A (ja) * 2008-10-31 2010-05-13 Panasonic Corp 半導体装置
US8362599B2 (en) * 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
US8492874B2 (en) 2011-02-04 2013-07-23 Qualcomm Incorporated High density metal-insulator-metal trench capacitor
US9058973B2 (en) 2011-04-13 2015-06-16 International Business Machines Corporation Passive devices fabricated on glass substrates, methods of manufacture and design structures
US9947688B2 (en) * 2011-06-22 2018-04-17 Psemi Corporation Integrated circuits with components on both sides of a selected substrate and methods of fabrication
US8659126B2 (en) 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US20130134553A1 (en) 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer and semiconductor package with noise suppression features

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641874A (zh) * 2004-01-13 2005-07-20 三星电子株式会社 多芯片封装
CN101233614A (zh) * 2005-09-06 2008-07-30 松下电器产业株式会社 电容器装载型半导体器件
CN103077933A (zh) * 2011-10-26 2013-05-01 马克西姆综合产品公司 三维的芯片到晶圆级集成

Also Published As

Publication number Publication date
US9468098B2 (en) 2016-10-11
EP3120674B1 (en) 2020-07-29
US20160381809A1 (en) 2016-12-29
JP2017510075A (ja) 2017-04-06
US20150271920A1 (en) 2015-09-24
EP3120674A1 (en) 2017-01-25
KR20160135186A (ko) 2016-11-25
WO2015142591A1 (en) 2015-09-24
CN106133902A (zh) 2016-11-16

Similar Documents

Publication Publication Date Title
CN106133902B (zh) 半导体封装中具有焊球连接的正面朝上基板集成
KR101046394B1 (ko) 스택 패키지
CN107230663A (zh) 具有减小的应力的半导体封装件
KR101685501B1 (ko) 패키지 온 패키지
KR101652831B1 (ko) 열적 특성을 개선하는 패키지 온 패키지
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
US9799722B1 (en) Inductive component and package structure thereof
JP2010199286A (ja) 半導体装置
KR20160066311A (ko) 반도체 패키지 및 반도체 패키지의 제조방법
KR102251001B1 (ko) 반도체 패키지
WO2016162938A1 (ja) 半導体装置
KR101207882B1 (ko) 패키지 모듈
KR20190017096A (ko) 반도체 패키지
CN109216294A (zh) 半导体封装
US11776917B2 (en) Electronic package
CN103021989B (zh) 一种多组件的芯片封装结构
CN103426869B (zh) 层叠封装件及其制造方法
US10433424B2 (en) Electronic module and the fabrication method thereof
CN112992476B (zh) 变压器，以及封装模块
US20160155559A1 (en) Electronic package
KR101219086B1 (ko) 패키지 모듈
KR101046251B1 (ko) 적층형 반도체 패키지
US10892212B2 (en) Flat no-lead package with surface mounted structure
KR101046392B1 (ko) 반도체 패키지용 기판과, 이를 포함하는 반도체 패키지 및 이를 이용한 스택 패키지
KR101332873B1 (ko) 캐패시턴스 제공용 인터포져 및 이를 이용한 리드 프레임 타입 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant