CN106133878B - 用于线路中段(mol)应用的金属有机钨的形成方法 - Google Patents

用于线路中段(mol)应用的金属有机钨的形成方法 Download PDF

Info

Publication number
CN106133878B
CN106133878B CN201580018220.XA CN201580018220A CN106133878B CN 106133878 B CN106133878 B CN 106133878B CN 201580018220 A CN201580018220 A CN 201580018220A CN 106133878 B CN106133878 B CN 106133878B
Authority
CN
China
Prior art keywords
tungsten
substrate
layer
barrier layer
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201580018220.XA
Other languages
English (en)
Other versions
CN106133878A (zh
Inventor
吴立其
柳尚澔
大东和也
朴基振
吴凯
戴维·汤普森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN106133878A publication Critical patent/CN106133878A/zh
Application granted granted Critical
Publication of CN106133878B publication Critical patent/CN106133878B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536—Use of plasma, radiation or electromagnetic fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本发明提供用于线路中段(MOL)应用的形成金属有机钨的方法。一些实施方式中，一种处理基板的方法包括下述步骤：提供基板至处理腔室，其中所述基板包括一特征，所述特征形成于所述基板的介电层的第一表面中；将所述基板暴露于等离子体，以在所述介电层顶上与所述特征内形成钨阻挡层，所述等离子体由包括金属有机钨前驱物的第一气体形成，其中形成所述钨阻挡层期间的所述处理腔室的温度低于约225摄氏度；以及于所述钨阻挡层上沉积钨填充层，以填充所述特征至所述第一表面。

Description

用于线路中段(MOL)应用的金属有机钨的形成方法
技术领域
本公开内容的实施方式一般地涉及处理基板的方法。
背景技术
传统的线路中段(middle-of-the-line,MOL)制造使用具有钛(Ti)/氮化钛(TiN)、钨成核层和钨填充层的堆叠。TiN被用作为氟阻挡层。钨成核层通过例如使用二硼烷(B2H6)和六氟化钨(WF6)的化学气相沉积形成于TiN层顶上。相较于钨填充层，TiN阻挡层和钨成核层两者都是高电阻性的。最小的TiN阻挡层厚度为至少约20埃。钨成核层通常具有约10埃至约30埃的厚度。随着电子器件的几何大小持续缩小和器件密度持续增加，整体特征尺寸已减小且深宽比已增加。发明人已观察到，当特征尺寸缩小到约10nm或更小时，TiN阻挡层与钨成核层占据了显著量的过孔(via)空间，而几乎没留下什么空位供低电阻钨生长。而且，TiN阻挡层与钨成核层的非正形沉积窄化了过孔的开口，导致后续的钨填充步骤有显著的挑战。因此，发明人相信，MOL制造需要新的处理与集成方案，以满足电阻率和填充的需求。
因此，发明人已提供了用于MOL应用的形成金属有机钨的改良方法。
发明内容
本发明提供用于线路中段(MOL)应用的形成金属有机钨的方法。一些实施方式中，一种处理基板的方法包括下述步骤：提供基板至处理腔室，其中所述基板包括一特征，所述特征形成于所述基板的介电层的第一表面中；将所述基板暴露于等离子体，以在所述介电层顶上与所述特征内形成钨阻挡层，所述等离子体由包括金属有机钨前驱物的第一气体形成，其中形成所述钨阻挡层期间的所述处理腔室的温度低于约200摄氏度；以及于所述钨阻挡层上沉积钨填充层，以填充所述特征至所述第一表面。
一些实施方式中，一种处理基板的方法包括下述步骤：提供基板至处理腔室，其中所述基板包括一特征，所述特征形成于所述基板的介电层的第一表面中；将钨种晶层沉积于所述基板顶上以及所述特征内；通过将所述基板暴露于等离子体而在所述钨种晶层顶上沉积钨阻挡层，所述等离子体由包括金属有机钨前驱物的第一气体形成，其中形成所述钨阻挡层期间的所述处理腔室的温度低于约225摄氏度；以及于所述钨阻挡层上沉积钨填充层，以填充所述特征至所述第一表面。
一些实施方式中，提供一种计算机可读介质，所述计算机可读介质上储存有多个指令，当执行所述指令时，会引发处理腔室执行处理基板的方法。所述方法可包括任一种本发明所公开的方法。
本公开内容的其它和进一步的实施方式在下文中描述。
附图说明
于上文中简要总结且于下文中更详细讨论的本公开内容的实施方式可通过参照附图中所描绘的本公开内容的说明性实施方式而理解。然而，附图仅说明本公开内容的典型实施方式，因而不应被视为对范围的限制，因为本公开内容可允许其它等效的实施方式。
图1描绘了根据本公开内容的一些实施方式的处理基板的方法的流程图。
图2A至图2C描绘了根据本公开内容的一些实施方式的形成于基板中的互连结构(interconnect struct)的侧剖面视图。
图3描绘了根据本公开内容的一些实施方式的适合执行用于处理基板的方法的组合工具。
为了便于理解，已尽可能使用相同的附图标号指代各附图共通的相同元件。所述附图并未按照比例绘制，且为了简明起见而被简化。一个实施方式的元件和特征可有利地并入其它实施方式而无需进一步赘述。
具体实施方式
在此提供一种用于线路中段(MOL)应用的形成金属有机钨阻挡层的方法。本发明所描述的创造性方法可有利地用于通过以钨阻挡层代替传统的氮化钛阻挡层和钨成核层而促进形成改良的金属接触、过孔和栅极(gate)。相较于传统的氮化钛和钨成核层，钨阻挡层在特征内占据较少空间，从而为低电阻钨填充材料提供空间。此外，相较于常规的传统氮化钛阻挡层，钨阻挡层减少了电阻并且促进了钨填充处理。
本发明所述的创造性方法可与任何器件节点一并利用，但可特别有利于约10nm或更小的器件节点。如在本发明中所使用的“阻挡层”可指这样的层：所述层沿着特征的侧壁和/或下表面的至少一部分一致地形成，使得在沉积所述层前的所述特征的实质性部分在沉积所述层后维持未填充状态。一些实施方式中，阻挡层可沿着特征的侧壁与下表面的整体而形成。
图1描绘了根据本公开内容的一些实施方式的用于MOL应用的形成金属有机钨层的方法100的流程图。方法100可在任何适合的处理腔室中执行，所述适合的处理腔室配置成用于化学气相沉积(CVD)或等离子体增强原子层沉积(PEALD)中的一种或多种。可用于执行本发明所公开的创造性方法的示例性处理系统可包括(但不限于)
Figure GDA0001260147120000041
或
Figure GDA0001260147120000042
处理系统线路，以及
Figure GDA0001260147120000043
Plus或SIP
Figure GDA0001260147120000044
PVD处理腔室，上述处理系统线路和处理腔室都可购自美国加州Santa Clara的应用材料公司。包括购自其它制造商的其它处理腔室也可合适地与本发明所提供的教导一并使用。
如图A所示，方法100一般地开始于步骤102，步骤102为提供基板200，基板200具有形成于基板200的第一表面204中的特征202，特征202朝向基板200的相对的第二表面206延伸进入基板200。基板200可以是任何能够在上面具有沉积材料的基板，诸如硅基板、Ⅲ-Ⅴ族化合物基板、硅锗(SiGe)基板、外延基板、绝缘体上覆硅(SOI)基板、显示器基板(诸如液晶显示器(LCD)、等离子体显示器、电致发光(EL)灯显示器)、太阳能电池阵列、太阳能板、发光二极管(LED)基板、半导体晶片或类似物。一些实施方式中，一个或多个额外层可设置于基板上，使得如下文所述的钨阻挡层可至少部分地形成于额外层上。例如，一些实施方式中，可于基板上设置包括金属、氮化物、氧化物或类似物或前述材料的组合的层，且在所述层上可形成有钨层。
基板200可以是具有特征202形成在基板中的任何适合的基板。例如，基板200可包括介电材料、硅(Si)、金属或类似物中的一种或多种。此外，基板200可包括额外材料层，或者可具有一个或多个已完成或部分完成的结构，所述结构形成在基板中或基板上。例如，基板200可包括第一介电层212，第一介电层212诸如为氧化硅、低k材料(例如，介电常数低于氧化硅或低于约3.9的材料)或类似物。特征202可形成在第一介电层212中。一些实施方式中，第一介电层212可设置于第二介电层214顶上，第二介电层214诸如为氧化硅、氮化硅、碳化硅或类似物。导电材料(例如导电材料220)可设置于第二介电层214中，并且可对齐特征202，使得特征202在填充有导电材料时提供往返导电材料的电子路径。例如，导电材料可以是互连件所耦接的接线或过孔的一部分。
特征202可以是任何开口，诸如过孔、沟槽、双镶嵌结构或类似物。一些实施方式中，特征202可具有高深宽比，例如约5:1或更大的深宽比。如在本发明中所用的，深宽比是特征深度对特征宽度的比。特征202可通过使用任何适合的蚀刻工艺蚀刻基板200而形成。特征202包括底表面208与侧壁210。
一些实施方式中，且如图2A至图2C中的虚线所示，特征202可完全地延伸通过基板200和第二基板228的上表面226，且可形成特征202的底表面208。第二基板228可设置于邻近基板200的第二表面206。进一步(且也由虚线所示)，导电材料(例如导电材料220)可设置在第二基板228的上表面226中且对齐特征202。导电材料例如可为器件(诸如逻辑器件或类似物)的一部分或为至器件的电子路径的一部分，以向器件提供电连接性，所述器件诸如为栅极、接触垫、导电线或过孔或者类似物。
接着，在步骤104中，且如图2B所示，基板200暴露至由包括金属有机钨前驱物的第一气体所形成的等离子体，以于基板200顶上形成钨阻挡层216。例如，特征202的侧壁210、特征202的底表面208和基板200的第一表面204可被钨阻挡层216覆盖。第一气体进一步包括反应物气体(诸如氢气(H2)或氨气(NH3))以及伴随金属有机钨前驱物气体的载气，诸如氩气、氦气或氮气。第一气体中氢气的存在有利地将钨阻挡层216中的碳不纯物减至最少。载气以约300sccm至约600sccm的流速提供。
钨阻挡层216可作用为防止后续沉积的金属层扩散进入下面的层(诸如第一介电层212)以及作为适合的表面以供后续钨填充层的形成(如下文所述)。钨阻挡层216的存在有利地消除了对由例如氮化钛形成的典型阻挡层的需求，所述典型阻挡层也使用钨成核层建立适合的表面以供后续钨填充层形成。钨阻挡层216还提供比TiN阻挡层低约2至3倍的电阻率，从而减少过孔的电阻。钨阻挡层216可具有适合防止后续沉积材料扩散至下面的层中的任何厚度。例如，一些实施方式中，钨阻挡层216可具有约15埃至约40埃的厚度。
一些实施方式中，适合的钨前驱物可包括化学式为W(A)(B)2(C)、或W(A)(B)3(D)、或W(B)6、或W(A)2(D)2、或W(B)6-x(B2)x、或W(E)4、或W(F)3、或W(F)2(B)2、或W(F)(B)4的前驱物，其中A是带负电的六电子供体，B是中性的二电子供体、C是带正电的二电子供体、D是带负电的二电子供体、E是带负电的四电子供体、F是中性的四电子供体、且x是从0至6的正整数。适合的前驱物的范例包括：W(CO)6、CpW(CO)2NO、EtCpW(CO)2NO、Cp*W(CO)3NO、Cp2WH2、C4H9CNW(CO)5、(C5H11CN)W(CO)5、W(C3H5)4、W(C3H4CH3)4、W(C4H6)3、W(C4H6)2(CO)2或W(C4H6)(CO)4。
如前文所述，钨阻挡层216是经过等离子体增强原子层沉积工艺(PEALD)通过将基板200暴露至处于等离子体态的钨前驱物而形成。等离子体可通过下述方式形成：将足够的能量(例如射频(RF)能量)从电源耦合，以引燃第一气体而形成所述等离子体。一些实施方式中，电源可示意性提供处于适合频率(诸如约13.56MHz)的约100瓦至约1.2千瓦的电力。所述等离子体促进前驱物的分解，造成材料沉积于基板200上，从而形成钨阻挡层216。
用于形成上文所讨论的钨阻挡层216的通常处理条件包括将处理腔室压力维持在约5托至约20托。而且，形成钨阻挡层期间的处理腔室的温度低于约225摄氏度，诸如约175摄氏度至约225摄氏度。与其中腔室温度必须大于约250摄氏度以分解钨前驱物材料的热化学气相沉积工艺不同，发明人已发现PEALD工艺可用于在低于约225摄氏度的温度下沉积钨阻挡层。发明人已发现低温PEALD工艺有利地于例如沟槽、过孔或其它高深宽比特征中形成具有期望性质(诸如高密度、低电阻率和良好的阶梯覆盖率)的钨阻挡层。如在本发明中所使用的，阶梯覆盖率定义为结构侧壁上沉积的材料的最小厚度对场(例如基板的上表面)上沉积的材料的厚度的比。
一些实施方式中，在钨阻挡层216形成前，钨种晶层先沉积于基板200顶上。钨种晶层具有充分的厚度，以促进下面的硅或氧化物表面上的钨等离子体增强原子层沉积(PEALD)的生长。一些实施方式中，种晶层可具有低于约2个单层钨的厚度。钨种晶层可通过等离子体增强化学气相沉积工艺使用上文所列的钨前驱物形成。发明人已发现，在PEALD钨阻挡层形成前提供钨种晶层提供了PEALD钨膜性质的显著改善，诸如较低的粗糙度(例如从约5.9埃减少至约3.7埃(Rms))以及较低的电阻率(例如从约304μΩ-cm减少至3.7μΩ-cm)。
接着，在步骤106中，且如图3C中所示，将钨填充层224沉积于钨阻挡层216上以填充特征202。一些实施方式中，钨填充层224可通过化学气相沉积工艺使用例如WF6或WF6与氢气(诸如H2或NH3)的组合沉积。
特征202可填充至超过基板200的上表面的位高(level)，且沉积材料(例如钨阻挡层216)与钨填充层224可留在基板200的上表面上。因此，可使用诸如酸性溶液中的湿清洁(wetclean)、化学或电化学机械研磨或类似技术的技术从上表面移除过量的沉积材料，使得特征202填充有沉积的导电材料最多达大约与基板上表面相当的位高，如图2C所示。
可于个别的处理腔室中执行本发明所描述的方法，所述个别的处理腔室可以独立配置(standalone configuration)的方式提供，或提供成组合工具的一部分，所述组合工具例如为下文中针对图3所描述的整合工具300(即，组合工具)。整合工具300的范例包括
Figure GDA0001260147120000091
与
Figure GDA0001260147120000092
整合工具，可购自美国加州Santa Clara的应用材料公司。本发明所述的方法可通过使用耦接适合处理腔室的其它组合工具实施，或是在其它适合的处理腔室中实施。例如，一些实施方式中，上文所讨论的创造性的方法可有利地在整合工具中执行，使得在处理步骤之间有受限的真空破坏或无真空破坏。例如，减少的真空破坏可限制或防止种晶层或基板的其它部分的污染。
整合工具300包括真空密封处理平台301、工厂界面304与系统控制器302。处理平台301包括多个处理腔室，诸如314A、314B、314C与314D，所述处理腔室在操作上耦接至真空基板移送室(移送室303)。工厂界面304在操作上通过一个或多个装载锁定腔室(两个装载锁定腔室，诸如图4中所示306A和306B)耦接至移送室303。
一些实施方式中，工厂界面304包括至少一个坞站(docking station)307、至少一个工厂界面机械手338，以促进移送半导体基板。坞站307配置成接收一个或多个前开式标准舱(FOUP)。图3的实施方式中显示四个FOUP，诸如305A、305B、305C与305D。工厂界面机械手338配置成从工厂界面304移送基板通过装载锁定腔室(诸如306A和306B)至处理平台301。装载锁定腔室306A和306B的各自具有耦接至工厂界面304的第一通口以及耦接至移送室303的第二通口。装载锁定腔室306A与306B耦接至压力控制系统(未示出)，所述压力控制系统泵抽压降装载锁定腔室306A与306B且使装载锁定腔室306A与306B通气，以促进在移送室303的真空环境与工厂界面304的实质上周围(例如大气)环境之间传送基板。移送室303具有设置在移送室303中的真空机械手342。真空机械手342能够在装载锁定腔室306A与306B和处理腔室314A、314B、314C与314D之间移送基板321。
一些实施方式中，处理腔室314A、314B、314C与314D耦接至移送室303。处理腔室314A、314B、314C与314D包括至少等离子体增强原子层沉积(PEALD)腔室与化学气相沉积(CVD)腔室。也可设置额外的腔室，诸如额外的CVD腔室和/或退火腔室、物理气相沉积(PVD)腔室或类似腔室。CVD腔室与退火腔室可包括任何一个那些适合执行所有或部分本发明所述方法的腔室(如前文所讨论的)。
一些实施方式中，可将一个或多个可选的服务腔室(显示为316A与316B)耦接至移送室303。服务腔室316A与316B可配置成执行其它基板处理，诸如去气、定向、基板度量、冷却与类似处理。
系统控制器302利用直接控制处理腔室314A、314B、314C与314D而控制工具300的操作，或者是通过控制与处理腔室314A、314B、314C和314D以及工具300相联的计算机(或控制器)而控制工具300的操作。在操作上，系统控制器302实现来自各自腔室和系统的数据收集与反馈，而使工具300的性能优化。系统控制器302一般地包括中央处理单元(CPU)330、内存334与支持电路332。CPU 330可以是任何形式的可用于工业设施中的通用计算机处理器中的一种。支持电路332常规地耦接至CPU 330且可包括高速缓存、时钟电路、输入/输出子系统、电源、以及类似物。诸如前文所述的处理方法的软件程序可储存于内存334中，且当由CPU 330执行时，将CPU 330转换成专用计算机(系统控制器302)。所述软件程序也可由第二控制器(未示出)所储存和/或执行，所述第二控制器位于远离工具300之处。
虽然前述内容涉及本公开内容的实施方式，但是在不脱离本公开内容的基本范围下可以设计本公开内容的其它和进一步的实施方式。

Claims (14)

1.一种处理基板的方法，所述方法包括下述步骤：
提供所述基板至处理腔室，其中所述基板包括一特征，所述特征形成于所述基板的介电层的第一表面中；
将所述基板暴露于等离子体，以通过等离子体增强原子层沉积(PEALD)在所述介电层顶上与所述特征内形成钨阻挡层，所述等离子体由包括金属有机钨前驱物的第一气体形成，其中形成所述钨阻挡层期间的所述处理腔室的温度低于225摄氏度；以及
于所述钨阻挡层上沉积钨填充层，以填充所述特征至所述第一表面，
其中所述方法进一步包括：在沉积所述钨阻挡层之前沉积钨种晶层于所述基板顶上和所述特征内。
2.如权利要求1所述的方法，其中所述特征具有大于5:1的深度对宽度的深宽比。
3.如权利要求1所述的方法，其中所述第一气体进一步包括含氢气体。
4.如权利要求3所述的方法，其中所述含氢气体是H2或NH3。
5.如权利要求1所述的方法，其中所述第一气体进一步包括载气。
6.如权利要求5所述的方法，其中所述载气是氩气、氦气或氮气。
7.如权利要求6所述的方法，其中所述载气的流速为300sccm至600sccm。
8.如权利要求1至7任一项所述的方法，其中所述处理腔室处于5托至20托的压力。
9.如权利要求1至7任一项所述的方法，其中所述金属有机钨前驱物是W(CO)6、CpW(CO)2NO、EtCpW(CO)2NO、Cp*W(CO)3NO、Cp2WH2、C4H9CNW(CO)5、(C5H11CN)W(CO)5、W(C3H5)4、W(C3H4CH3)4、W(C4H6)3、W(C4H6)2(CO)2或W(C4H6)(CO)4中的一个。
10.如权利要求1至7任一项所述的方法，其中所述钨阻挡层具有15埃至40埃的厚度。
11.如权利要求1所述的方法，其中所述钨种晶层具有低于2个单层钨的厚度。
12.如权利要求1所述的方法，其中所述钨种晶层通过等离子体增强化学气相沉积工艺形成。
13.如权利要求1所述的方法，其中所述钨种晶层通过等离子体增强化学气相沉积工艺采用钨前驱物而形成，所述钨前驱物包括W(CO)6、CpW(CO)2NO、EtCpW(CO)2NO、Cp*W(CO)3NO、Cp2WH2、C4H9CNW(CO)5、(C5H11CN)W(CO)5、W(C3H5)4、W(C3H4CH3)4、W(C4H6)3、W(C4H6)2(CO)2或W(C4H6)(CO)4中的一个。
14.一种计算机可读介质，所述计算机可读介质上储存有多个指令，当执行所述指令时，会引发处理腔室执行处理基板的方法，所述方法包括权利要求1至13的任一项所述的方法。
CN201580018220.XA 2014-04-11 2015-03-13 用于线路中段(mol)应用的金属有机钨的形成方法 Expired - Fee Related CN106133878B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461978540P 2014-04-11 2014-04-11
US61/978,540 2014-04-11
US14/300,773 US9653352B2 (en) 2014-04-11 2014-06-10 Methods for forming metal organic tungsten for middle of the line (MOL) applications
US14/300,773 2014-06-10
PCT/US2015/020503 WO2015156957A1 (en) 2014-04-11 2015-03-13 Methods for forming metal organic tungsten for middle of the line (mol) applications

Publications (2)

Publication Number Publication Date
CN106133878A CN106133878A (zh) 2016-11-16
CN106133878B true CN106133878B (zh) 2020-02-14

Family

ID=54265681

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580018220.XA Expired - Fee Related CN106133878B (zh) 2014-04-11 2015-03-13 用于线路中段(mol)应用的金属有机钨的形成方法

Country Status (6)

Country Link
US (1) US9653352B2 (zh)
KR (1) KR102345466B1 (zh)
CN (1) CN106133878B (zh)
SG (1) SG11201607671YA (zh)
TW (1) TWI669407B (zh)
WO (1) WO2015156957A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR102064627B1 (ko) 2012-03-27 2020-01-09 노벨러스 시스템즈, 인코포레이티드 텅스텐 피처 충진
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9685370B2 (en) * 2014-12-18 2017-06-20 Globalfoundries Inc. Titanium tungsten liner used with copper interconnects
US9595466B2 (en) 2015-03-20 2017-03-14 Applied Materials, Inc. Methods for etching via atomic layer deposition (ALD) cycles
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
WO2017091571A1 (en) * 2015-11-25 2017-06-01 Applied Materials, Inc. Methods for forming low-resistance contacts through integrated process flow systems
US10043607B2 (en) 2016-05-02 2018-08-07 International Business Machines Corporation Electrolessly formed high resistivity magnetic materials
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
CN110088875B (zh) * 2016-12-15 2023-09-01 应用材料公司 无成核的间隙填充ald工艺
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10886123B2 (en) * 2017-06-02 2021-01-05 Asm Ip Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
KR20190042461A (ko) * 2017-10-14 2019-04-24 어플라이드 머티어리얼스, 인코포레이티드 Beol 인터커넥트를 위한 고온 pvd 구리 증착을 이용한 ald 구리의 집적
WO2020118100A1 (en) 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
US11244903B2 (en) * 2019-12-30 2022-02-08 Micron Technology, Inc. Tungsten structures and methods of forming the structures
US11955381B2 (en) * 2020-06-22 2024-04-09 Applied Materials, Inc. Low-temperature plasma pre-clean for selective gap fill

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201145461A (en) * 2010-03-24 2011-12-16 Applied Materials Inc Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04373175A (ja) * 1991-06-21 1992-12-25 Fujitsu Ltd 半導体装置
KR100215846B1 (ko) * 1996-05-16 1999-08-16 구본준 반도체장치의 배선형성방법
CN1115723C (zh) * 1996-11-15 2003-07-23 三星电子株式会社 氮化钨层制造方法及使用同样原理的金属连线制造方法
SG87187A1 (en) 1999-10-18 2002-03-19 Applied Materials Inc Pvd-imp tungsten and tungsten nitride as a liner, barrier and/or seed layer for tungsten, aluminium and copper applications
US6383821B1 (en) * 1999-10-29 2002-05-07 Conexant Systems, Inc. Semiconductor device and process
US6458251B1 (en) * 1999-11-16 2002-10-01 Applied Materials, Inc. Pressure modulation method to obtain improved step coverage of seed layer
US20030008070A1 (en) 2001-06-12 2003-01-09 Applied Materials,Inc Low-resistivity tungsten from high-pressure chemical vapor deposition using metal-organic precursor
US7964505B2 (en) * 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7732327B2 (en) * 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US6686278B2 (en) * 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
US20030017696A1 (en) * 2001-07-13 2003-01-23 United Microelectronics Corp. Method for improving capability of metal filling in deep trench
KR100805843B1 (ko) * 2001-12-28 2008-02-21 에이에스엠지니텍코리아 주식회사 구리 배선 형성방법, 그에 따라 제조된 반도체 소자 및구리 배선 형성 시스템
US20030134504A1 (en) * 2002-01-14 2003-07-17 Denning Dean J. Method of making an inlaid structure in a semiconductor device
US20030203616A1 (en) * 2002-04-24 2003-10-30 Applied Materials, Inc. Atomic layer deposition of tungsten barrier layers using tungsten carbonyls and boranes for copper metallization
DE10255835A1 (de) * 2002-11-29 2004-06-17 Infineon Technologies Ag Niederohmige WNx-Barriere
US7192866B2 (en) * 2002-12-19 2007-03-20 Sharp Laboratories Of America, Inc. Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects
US20050095846A1 (en) * 2003-10-31 2005-05-05 Basol Bulent M. System and method for defect free conductor deposition on substrates
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US20070066060A1 (en) * 2005-09-19 2007-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and fabrication methods thereof
KR101275025B1 (ko) * 2007-07-12 2013-06-14 삼성전자주식회사 반도체 소자용 배선 구조물 및 이의 형성방법
US20090026618A1 (en) * 2007-07-25 2009-01-29 Samsung Electronics Co., Ltd. Semiconductor device including interlayer interconnecting structures and methods of forming the same
US7844705B2 (en) * 2008-05-30 2010-11-30 General Electric Company Networked image visualization image quality enhancement method and system
US8049336B2 (en) * 2008-09-30 2011-11-01 Infineon Technologies, Ag Interconnect structure
US8124531B2 (en) 2009-08-04 2012-02-28 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US8637390B2 (en) * 2010-06-04 2014-01-28 Applied Materials, Inc. Metal gate structures and methods for forming thereof
US8865594B2 (en) * 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8883637B2 (en) 2011-06-30 2014-11-11 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials
WO2013046155A1 (en) * 2011-09-27 2013-04-04 L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Tungsten diazabutadiene precursors, their synthesis, and their use for tungsten containing film depositions
JP2013128062A (ja) * 2011-12-19 2013-06-27 Elpida Memory Inc 半導体装置の製造方法
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
KR101990051B1 (ko) * 2012-08-31 2019-10-01 에스케이하이닉스 주식회사 무불소텅스텐 배리어층을 구비한 반도체장치 및 그 제조 방법
US9169556B2 (en) * 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9230815B2 (en) * 2012-10-26 2016-01-05 Appled Materials, Inc. Methods for depositing fluorine/carbon-free conformal tungsten

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201145461A (en) * 2010-03-24 2011-12-16 Applied Materials Inc Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Also Published As

Publication number Publication date
US9653352B2 (en) 2017-05-16
TW201610202A (zh) 2016-03-16
KR20160144452A (ko) 2016-12-16
TWI669407B (zh) 2019-08-21
US20150294906A1 (en) 2015-10-15
SG11201607671YA (en) 2016-10-28
KR102345466B1 (ko) 2021-12-29
WO2015156957A1 (en) 2015-10-15
CN106133878A (zh) 2016-11-16

Similar Documents

Publication Publication Date Title
CN106133878B (zh) 用于线路中段(mol)应用的金属有机钨的形成方法
CN108431924B (zh) 通过集成工艺流程系统形成低电阻触点的方法
KR102565626B1 (ko) 루테늄 도핑에 의한 증진된 코발트 내응집성 및 갭 충전 성능
US9677172B2 (en) Methods for forming a cobalt-ruthenium liner layer for interconnect structures
KR102291990B1 (ko) 텅스텐 육플루오르화물(wf6) 에치백을 이용하여 텅스텐 막을 증착하기 위한 방법
JP2016540368A (ja) シームレスのコバルト間隙充填を可能にする方法
US20120141667A1 (en) Methods for forming barrier/seed layers for copper interconnect structures
WO2016153987A1 (en) Methods for etching via atomic layer deposition (ald) cycles
KR20200133830A (ko) 3d 낸드 응용들을 위한 터널 산화물의 고압 암모니아 질화
US11171046B2 (en) Methods for forming cobalt and ruthenium capping layers for interconnect structures
US10014179B2 (en) Methods for forming cobalt-copper selective fill for an interconnect
KR102118580B1 (ko) 루테늄 필름들의 화학 기상 증착 (cvd) 및 그 용도들
US20230323543A1 (en) Integrated cleaning and selective molybdenum deposition processes
US20230197508A1 (en) Self-assembled monolayer for selective deposition
CN117501429A (zh) 用于处理基板的方法及设备
TW202314800A (zh) 用於底層金屬上之完全著底通孔之選擇性蝕刻停止封蓋及選擇性通孔開口之方法及裝置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200214