CN106094365A - The manufacture method of liquid crystal indicator, array base palte and array base palte - Google Patents
The manufacture method of liquid crystal indicator, array base palte and array base palte Download PDFInfo
- Publication number
- CN106094365A CN106094365A CN201610454751.XA CN201610454751A CN106094365A CN 106094365 A CN106094365 A CN 106094365A CN 201610454751 A CN201610454751 A CN 201610454751A CN 106094365 A CN106094365 A CN 106094365A
- Authority
- CN
- China
- Prior art keywords
- electrode
- pixel electrode
- region
- layer
- plural number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Geometry (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides the manufacture method of a kind of liquid crystal indicator, array base palte and array base palte, relates to Display Technique field.Array base palte, a substrate, there is the plural data line in cross arranged crosswise and plural number bar scan line；Active member, is arranged on the cross intersection region of this plural number data line and this plural number bar scan line；Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region, and is electrically connected with this active member by a contact hole；Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extend to the region of each this pixel electrode unit in be formed with the open area of a plurality of repeated arrangement, being also formed with the extension of this transparency electrode in the region of each this pixel electrode unit, this extension at least covers this data wire in cross arranged crosswise and this scan line.The present invention also discloses the manufacture method of this array base palte.
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of, there is the liquid crystal indicator of high transmission rate, array base
Plate and the manufacture method of array base palte.
Background technology
Transparence Display (Transparent Display) is a kind of can to realize transparent effect while picture shows
Display Technique, i.e. display itself have a certain degree of light peneration, it is possible to allow user viewing display show picture
Meanwhile, the background on rear side of display is clearly seen.Owing to being provided that the more preferable experience of user, and possess frivolous, energy-conservation
Advantage it is considered to be the Display Technique of environmental type of future generation.Along with larger panel producer active development and put on display transparent
Display concept product, transparent display market is expected to become a significant development direction in display market.
Transparence Display is the display device being provided simultaneously with display and transparent effect.Transparent display panel when closed, panel
One block of clear glass the most seemingly；When its work, beholder can not only watch the content of display on panel, simultaneously can also
Light-transmitting panel watches the object after panel.A lot of novel product has been derived at present, the most thoroughly by Transparence Display technology
Bright showcase, transparent glasses, intelligent window etc. is applied, and has been obtained the accreditation in market.
Transparence Display technology is the novel Display Technique developed based on flat-panel display device, but puts down relative to tradition
Plate Display Technique, Transparence Display technology mainly has a following feature: high permeability；Power consumption is low；Meet basic display requirement.
As transparent display, transmitance is a most important technical specification, and current industry there is no corresponding technical bid
Accurate, it is considered that the transmitance display floater more than 10% is it is believed that transparent display panel.Common LCD is as passive luminous aobvious
Show device, there is certain transmitance, but the most only 4% to 7%, relatively low for Transparence Display, how to improve material
Transmitance is the problem that liquid crystal panel transparence is to be solved.And the selfluminous elements such as OLED, PDP, need to remove self not
Luminescent material, or replace transparent material realize transparent, main work be transparent material exploitation.
Transparence Display technology can be optimized by dot structure, to reach higher transparency, for transparent passive display
For part, it is possible to use ambient light realizes display, and power consumption is the lowest.And active display part, although luminous component still expends
Electric energy, but opposed configuration is simple, and area reduces, and power consumption also can reduce relatively.Conventional liquid crystal, at CF substrate and TFT
The para-position deviation of 3～10um is there is the when of substrate para-position.In the region of pixel periphery correspondence BM, due to depositing of para-position deviation
, the BM floor of shading can enter pixel openings district, causes the actual aperture area of pixel to decline, and light utilization ratio reduces.
Summary of the invention
In view of this, the technical problem to be solved is to provide a kind of low-power consumption, high permeability transparent liquid crystal
The manufacture method of display device, array base palte and array base palte.
In order to reach above-mentioned or other purpose, one aspect of the present invention proposes a kind of array base palte, including: a substrate, tool
There are the plural data line in cross arranged crosswise and plural number bar scan line；Active member, is arranged on this plural number data line
Cross intersection region with this plural number bar scan line；Pixel electrode, is formed centered by each this cross intersection region
The pixel electrode unit of a plurality of repeated arrangement, and be electrically connected with this active member by a contact hole；Transparency electrode, in whole
EDS maps on the substrate, and this transparency electrode extend to the region of each this pixel electrode unit in be formed with a plurality of repetition
The open area of arrangement, is also formed with the extension of this transparency electrode in the region of each this pixel electrode unit, and this prolongs
Extending portion at least covers this data wire in cross arranged crosswise and this scan line.
Further, being provided with spacing distance between the pixel electrode unit of these a plurality of repeated arrangement, this transparency electrode is prolonged
It is formed at the overlay region on the direction vertical with this array base palte in extending each neighboring area of each this pixel electrode unit
Territory, the overlapping region between this transparency electrode and this pixel electrode unit forms storage capacitor.
Further, the extension of this transparency electrode is additionally provided with perforate, is used for accommodating this contact hole and extends through.
Further, this transparency electrode be perpendicular on this orientation substrate to be arranged at this pixel electrode and this data wire it
Between.
Further, columbium oxide film is covered above this transparency electrode.
Further, this transparency electrode material use tin dope three Indium sesquioxide., aluminium-doped zinc oxide, nano-silver thread or
Person's Graphene.
In order to reach above-mentioned or other purpose, another aspect of the present invention proposes a kind of array base palte, including: a substrate,
It is sequentially formed with the first metal layer, gate insulator, semiconductor layer, the second metal level on this substrate, protects insulating barrier, thick film
Insulating barrier, transparency electrode, isolated insulation layer, pixel electrode；Wherein, the pattern that the first metal layer is formed includes plural number bar scanning
Line, the pattern that the second metal level is formed includes plural number data line and drain electrode, this plural number data line and this plural number bar scan line
In cross arranged crosswise；Active member, including source electrode, is arranged on this data wire pattern of cross intersection region, grid,
It is arranged on this scan line pattern of cross intersection region, and drain electrode；Pixel electrode, with each this cross intersection region be
Be centrally formed with the pixel electrode unit of a plurality of repeated arrangement, and by a contact hole run through isolated insulation layer, insulating barrier with
The drain electrode of this active member is electrically connected with；Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extends to each
The open area of a plurality of repeated arrangement it is formed with, at each this pixel electrode unit in the region of this pixel electrode unit
Be also formed with the extension of this transparency electrode in region, this extension at least cover this data wire in cross arranged crosswise and
This scan line, the extension of this transparency electrode is additionally provided with perforate, is used for accommodating this contact hole and extends through.
In order to reach above-mentioned or other purpose, another aspect of the invention proposes a kind of array base palte, including: a substrate,
The first metal layer, gate insulator, semiconductor layer, the second metal level, protection insulating barrier, transparent electrical it is sequentially formed with on this substrate
Pole, insulating thick film layer, pixel electrode；Wherein, the pattern that the first metal layer is formed includes plural number bar scan line, the second metal level shape
The pattern become includes that plural number data line and drain electrode, this plural number data line and this plural number bar scan line are cross intersection cloth
Put；Active member, including: source electrode, it is arranged on this data wire pattern of cross intersection region, grid, is arranged on cross friendship
This scan line pattern in fork region, and drain electrode；Pixel electrode, is formed with plural number centered by each this cross intersection region
The pixel electrode unit of individual repeated arrangement, and the leakage of isolated insulation layer, insulating barrier and this active member is run through by a contact hole
Pole is electrically connected with；Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extends to each this pixel electrode unit
Region in be formed with the open area of a plurality of repeated arrangement, be also formed with in the region of each this pixel electrode unit
The extension of this transparency electrode, this extension at least covers this data wire in cross arranged crosswise and this scan line, and this is saturating
The extension of prescribed electrode is additionally provided with perforate, is used for accommodating this contact hole and extends through.
In order to reach above-mentioned or other purpose, further aspect of the present invention proposes a kind of liquid crystal indicator, including: above-mentioned
Array base palte；Counter substrate, is oppositely arranged with this array base palte；Liquid crystal layer, be interposed in this array base palte and this counter substrate it
Between；Also include public electrode, be distributed in this counter substrate in face electrode pattern；Wherein, this common electrode layer and this transparent electrical
Pole applies same potential voltage simultaneously.
In order to reach above-mentioned or other purpose, another aspect of the invention proposes a kind of LCD device array substrates
Manufacture method, including: provide array basal plate, formed first layer metal Thinfilm pattern, this first layer metal Thinfilm pattern bag
Include plural number bar scan line；The pattern of this first metal layer is formed gate insulator, is formed above this gate insulator
Semiconductor pattern；On this semiconductor pattern, forming second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes multiple
Several data wires, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include thin film transistor (TFT)
Source electrode, drain electrode；Being distributed insulating barrier on this second layer metal Thinfilm pattern, the most whole EDS maps has transparency electrode；
Being distributed isolated insulation layer in this transparency electrode, be distributed pixel electrode on this isolated insulation layer, this pixel electrode is with each
Centered by cross intersection region between this plural number data line and this plural number bar scan line, form a plurality of repeated arrangement
Pixel electrode unit, this pixel electrode unit realizes with drain electrode by running through a contact hole of this isolated insulation layer and this insulating barrier
It is electrically connected；Wherein, this transparency electrode is formed with a plurality of repeated arrangement in extending to the region of each this pixel electrode unit
Open area, in the region of each this pixel electrode unit, be also formed with the extension of this transparency electrode, this extension
At least covering this data wire in cross arranged crosswise and this scan line, the extension of this transparency electrode is additionally provided with perforate,
Extend through for accommodating this contact hole.
Accompanying drawing explanation
Fig. 1 is for schematically showing array base palte side of the present invention dot structure floor map；
Fig. 2 is for schematically showing array base palte planar structure schematic diagram of the present invention；
Fig. 3 is for schematically showing array base palte side of the present invention transparent electrode pattern floor map；
Fig. 4 is for schematically showing in one embodiment of the invention Fig. 1 dot structure along the cross-sectional view in A-A ' direction；
Fig. 5 is to schematically show the storage capacitor structures schematic diagram shown in Fig. 4；
Fig. 6 illustrates along the cross-section structure in A-A ' direction for schematically showing dot structure in another embodiment of the present invention Fig. 1
Figure；
Fig. 7 a～7e is for schematically showing an embodiment array base palte difference making step planar structure schematic diagram；
Fig. 8 is for schematically showing liquid crystal indicator cross-sectional view of the present invention；
Fig. 9 is for schematically showing liquid crystal indicator counter substrate planar structure schematic diagram of the present invention；
Figure 10 descends cross-sectional view in working order for schematically showing liquid crystal indicator of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings and specific embodiment, it is further elucidated with the present invention, it should be understood that these embodiments are merely to illustrate
The present invention rather than limit the scope of the present invention, after having read the present invention, each to the present invention of those skilled in the art
The amendment planting the equivalent form of value all falls within the application claims limited range.
Fig. 1 is for schematically showing array base palte side of the present invention dot structure floor map.As it is shown in figure 1, the present invention is real
Execute example and provide a kind of dot structure, including: scan line 101 and data wire 103 entreat perpendicular quadrature, within the pixel at data wire
103 are provided with thin film transistor (TFT) with the infall of scan line 101.The grid of thin film transistor (TFT) is this scanning of cross intersection region
The pattern of line 101, the source electrode of thin film transistor (TFT) is this data wire 103 pattern of cross intersection region, and thin film transistor (TFT)
Drain electrode 104, the raceway groove 102 of thin film transistor (TFT).Thin film transistor (TFT) drain electrode 104 be arranged over contact hole 105, pixel electrode
107 cover contact hole 105 realizes equipotential link with pixel electrode 107.
Between data line layer and pixel electrode layer, it is dispersed with transparency electrode 106.Transparent electrode layer is one layer and is provided with out
The transparency conducting layer of mouth, aperture position is in the lower section of pixel electrode, at four limits up and down of pixel, pixel electrode 107
Partly overlap with transparency electrode 106.Meanwhile, in the open area of transparent electrode layer, above data wire and scan line, cover
There is transparency electrode extension.
As it is shown in figure 1, transparency electrode 106 forms a cross chi structure in the open area of pixel.Constitute cross
The transparency electrode of type chi structure is covered each by data wire 103 and scan line 101, in order to shield data wire 103 and scan line 101
The voltage disturbance to pixel electrode voltage.Specifically, between data wire 103 and pixel electrode 107, and scan line 101 and picture
Coupling electric capacity is all there is between element electrode 107.Voltage on pixel electrode 107 is floating at retention time inner potential, at picture
In the retention time of element electrode 107 voltage, the variation in voltage in scan line 101 and data wire 103 can be by coupling capacitive effect
To pixel electrode 107, cover data wire 103 by the extension of transparency electrode 106 being arranged to cross chi structure and sweep
Retouch line 101, the display quality of liquid crystal display device can be promoted.
Fig. 2 is for schematically showing array base palte planar structure schematic diagram of the present invention.As in figure 2 it is shown, transparency electrode 106, in
Whole EDS maps on the substrate, and this transparency electrode extend to the region of each this pixel electrode unit in be formed a plurality of heavy
The open area of multiple bank row, is also formed with the extension of this transparency electrode in the region of each this pixel electrode unit, should
Extension 109 at least covers this data wire 103 and this scan line 101 in cross arranged crosswise.
Gap, left and right S1, upper and lower gap S2 is there is between the pixel electrode 107 of neighbor.Gap S1 and S2 is the least, as
The light utilization ratio of element is the highest.The factor limiting S1 with S2 size includes: the exposure accuracy of exposure machine；Adjacent pixel electrodes 107
Interference strength between voltage.Typically, gap S1 and S2 is at about 5um.In fig. 2, pixel electrode 107 and transparency electrode 106
Partly overlap, form the storage electric capacity Cs of pixel.Overlapping region L1, L2, L3 and L4 are distributed on four limits of pixel, additionally
It is distributed in cross crossover region.
Fig. 3 is for schematically showing array base palte side of the present invention transparent electrode pattern floor map.As it is shown on figure 3, it is transparent
The pattern of electrode layer includes transparency electrode 106 and transparency electrode extension 109, and transparency electrode extension 109 region hollow out
Forming perforate 106a, transparent electrode layer, between data line layer and pixel electrode layer, divides above the drain electrode 104 of data line layer
Contact hole by cloth, in order to avoid covering pixel electrode layer and the transparent electrode layer short circuit of contact hole, in the region of contact hole thoroughly
The extension region hollow out of prescribed electrode forms perforate 106a, is used for accommodating this contact hole and extends through.
Transparency electrode 106 in the dot structure that the present invention provides is transparent conductive film, mainly has metal film system, oxidation
Thing film system, other compound film systems, polymeric membrane system, compound film system etc..Specifically there are ITO (tin dope three Indium sesquioxide .), AZO
(aluminium-doped zinc oxide), nano-silver thread, Graphene etc..Preferably, ITO material is used.
The extension of the transparency electrode 106 of cross chi structure is covered in the surface of data wire 103 with scan line 101
109, in addition to the voltage disturbance of shielding data wire 103 and scan line 101, it is also possible to reduce data line layer metal and scan line layer
Metal reflective.In order to improve the annular transparent electrodes layer extinction effect to lower metal layer, reduce annular transparent electrodes simultaneously
Impedance, columbium oxide film can be covered above the transparent conductive films such as ITO.
Fig. 4 show the one of which distribution mode of the transparent electrode layer between pixel electrode and data wire metal layer.?
Pixel A A ' sectional view in direction, corresponding hierarchical relationship is: be distributed scan line above the underlay substrate such as glass, plastics 111
101, above scan line 101, it is distributed gate insulator 112, above gate insulator 112, is distributed semiconductor layer 102,
Distributed data line (source electrode) 103 and drain electrode 104 above semiconductor layer 102, distribution protection insulation above data wire 103
Layer 113, is distributed insulating thick film layer 114 above protection insulating barrier 113, distributing transparent electricity above insulating thick film layer 114
Pole layer 106, is distributed isolated insulation layer 115 above transparent electrode layer 106, is distributed pixel above isolated insulation layer 115
Electrode 107, pixel electrode 107 is by running through isolated insulation layer 115, insulating thick film layer 114 and the contact hole of protection insulating barrier 113
105 are electrically connected with drain electrode 104 realization.According to actual needs, it is convenient to omit protection insulating barrier 113.
In conjunction with Fig. 1 and Fig. 4, Fig. 5 show pixel electrode overlapping in four limit upper parts of pixel with transparency electrode and
The storage electric capacity Cs formed on cross chi structure.Because pixel electrode and transparency electrode are all transparent conductive films, overlapping
The region of part is still that transmission region, the design of such structure can improve the light utilization ratio of pixel.
Fig. 6 show the wherein another kind of distribution mode of the transparent electrode layer between pixel electrode and data wire metal layer.
In pixel A A ' sectional view in direction, corresponding hierarchical relationship is: distribution scanning above the underlay substrate such as glass, plastics 111
Line 101, is distributed gate insulator 112 above scan line 101, is distributed semiconductor layer above gate insulator 112
102, distributed data line (source electrode) 103 and drain electrode 104 above semiconductor layer 102, distribution protection above data wire 103
Insulating barrier 113, distributing transparent electrode layer 106 above protection insulating barrier 113, distribution thickness above transparent electrode layer 106
Film insulating barrier 114, is distributed pixel electrode 107 above insulating thick film layer 114, and pixel electrode 107 is by running through insulating thick film
The contact hole 105 of layer 114 and protection insulating barrier 113 is electrically connected with drain electrode 104 realization.
The invention provides the manufacture method of first substrate, as a example by the array base palte in above-described embodiment, provide making
Method step is as follows:
First, as shown in Figure 7a, it is provided that a transparency carrier, forming first layer metal Thinfilm pattern, this first layer metal is thin
Film figure includes plural number bar scan line 101；The pattern of this first metal layer forms gate insulator, at this gate insulator
Top formed semiconductor pattern, such as semiconductor channel pattern 102.
Then, as shown in Figure 7b, on this semiconductor pattern, second layer metal Thinfilm pattern, this second layer metal are formed
Thinfilm pattern includes plural number data line 103, and this plural number data line 103 intersects in cross with this plural number bar scan line 101
Arrange；Also include the source electrode of thin film transistor (TFT), drain electrode 104.
Then, as shown in Figure 7 c, this second layer metal Thinfilm pattern covers insulating barrier, such as protection insulating barrier and thick film
Insulating barrier, the most whole EDS maps has the extension 109 of transparency electrode 106 and cross chi structure thereof, in contact
The region in hole forms perforate 106a the extension region hollow out of transparency electrode, is used for accommodating this contact hole and extends through；
Then, as shown in figure 7d, after covering isolated insulation layer above transparent electrode layer, etching forms contact hole 105, connects
Contact hole runs through isolated insulation layer, insulating thick film layer and protection insulating barrier.
Finally, as shown in figure 7e, being distributed pixel electrode 107 on this isolated insulation layer, this pixel electrode is should with each
Centered by cross intersection region between plural number data line and this plural number bar scan line, form the picture of a plurality of repeated arrangement
Element electrode unit, this pixel electrode unit is real with drain electrode by the contact hole 105 running through this isolated insulation layer and this insulating barrier
Now it is electrically connected；
Wherein, this transparency electrode is formed with a plurality of repeated arrangement in extending to the region of each this pixel electrode unit
Open area, is also formed with the extension 109 of this transparency electrode, this extension in the region of each this pixel electrode unit
109 at least cover this data wire 103 and this scan line 101 in cross arranged crosswise.
Fig. 8 is for schematically showing liquid crystal indicator cross-sectional view of the present invention.As shown in Figure 8, the present invention also carries
Supply a kind of liquid crystal indicator, including: the respective embodiments described above and the array base palte 100 of corresponding each embodiment, opposed base
Plate 200, and it is located in the liquid crystal functional layer 300 between this array base palte 100 and this counter substrate 200.
Fig. 9 is for schematically showing liquid crystal indicator counter substrate planar structure schematic diagram of the present invention.As it is shown in figure 9, should
The counter substrate 200 that liquid crystal display device uses, including underlay substrate 211 (not shown), public electrode 201, light-shielding pattern
202, spacer 203.As required, it is convenient to omit light-shielding pattern 202.In Fig. 10, at counter substrate 200 and first substrate
It is liquid crystal functional layer 300 between 100, including counter substrate side alignment film 303, liquid crystal 301, array base palte side alignment film 302.
Figure 10 descends cross-sectional view in working order for schematically showing liquid crystal indicator of the present invention.Such as Figure 10 institute
Showing, ring-like transparency electrode 106 and the public electrode 201 on second substrate, current potential is fixed, and does not becomes with the change of pixel voltage
Change.Preferably, ring-like transparency electrode is equal with the current potential of the public electrode 201 on second substrate.In gap S1 and S2 region, by
Potential difference between ring-like transparency electrode and public electrode 201 is 0, and the Liquid Crystal Molecules Alignment state being positioned at this region is fixed,
Not changing with the change of pixel voltage, the state of liquid crystal molecule is controlled.Even if as it is shown in figure 9, in pixel electrode and common electrical
Applying various different current potential between pole 201, at gap S1 and the liquid crystal molecule in S2 region, ordered state is all fixing.
The dot structure that the present invention proposes, has a following features:
(1) metal wire is few: only scan line and two perpendicular metal wires of data wire.Metal wire is few, metal shading
The least with reflective impact.
(2) metal wire is thin: across protective layer and thick film layers between scan line, data wire and pixel electrode, between pixel
Coupling electric capacity little, it is the thinnest that metal wire can do.Metal wire is thin, and metal shading is the least with reflective impact.
(3) for using UV2A (Ultraviolet induced multi-domain Vertical Alignment)
The liquid crystal display mode of technology, scan line and data wire are exactly the demarcation line between liquid crystal display farmland and adjacent lcd display farmland,
Black stricture of vagina between display farmland is dispensed directly onto above metal wire, the most additionally takies lighttight region, the light utilization ratio of pixel
High.
(4) for using on the VA Display Technique of normally black mode, transparency electrode on the first substrate and second substrate
Potential difference between public electrode is set to 0, in gap S1 and S2 region, and the black state that liquid crystal display is stable, such that it is able between Sheng Lveing
The black matrix" on second substrate directly over gap S1 and S2.Use technical scheme, transparency electrode and pixel electrode
Between overlapping area abundant, the electric lines of force of pixel electrode focuses primarily upon between pixel electrode and transparency electrode, is dispersed into picture
Electric lines of force outside element electrode is few, and the disturbance to gap S1 and the liquid crystal in S2 region is faint, can solve pixel electrode voltage (electricity
The line of force) leakage problem of gap S1 and S2 that causes of disturbance.
(5) for using in the VA Display Technique of normal white mode, transparency electrode on the first substrate and counter substrate
Potential difference between public electrode is set to 6V, in gap S1 and S2 region, and the black state that liquid crystal display is stable, such that it is able between Sheng Lveing
The black matrix" in counter substrate directly over gap S1 and S2.Use technical scheme, transparency electrode and pixel electrode
Between overlapping area abundant, the electric lines of force of pixel electrode focuses primarily upon between pixel electrode and transparency electrode, is dispersed into picture
Electric lines of force outside element electrode is few, and the disturbance to gap S1 and the liquid crystal in S2 region is faint, can solve pixel electrode voltage (electricity
The line of force) leakage problem of gap S1 and S2 that causes of disturbance.
The preferred embodiment of the present invention described in detail above, but, the present invention is not limited in above-mentioned embodiment
Detail, in the technology concept of the present invention, technical scheme can be carried out multiple equivalents, this
A little equivalents belong to protection scope of the present invention.
It is further to note that each the concrete technical characteristic described in above-mentioned detailed description of the invention, at not lance
In the case of shield, can be combined by any suitable means.In order to avoid unnecessary repetition, the present invention to various can
The compound mode of energy illustrates the most separately.
Claims (10)
1. an array base palte, including:
One substrate, has the plural data line in cross arranged crosswise and plural number bar scan line；
Active member, is arranged on the cross intersection region of this plural number data line and this plural number bar scan line；
Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region,
And be electrically connected with this active member by contact hole；
Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extends to the region of each this pixel electrode unit
Inside it is formed with the open area of a plurality of repeated arrangement, in the region of each this pixel electrode unit, is also formed with this transparent
The extension of electrode, this extension at least covers this data wire in cross arranged crosswise and this scan line.
Array base palte the most according to claim 1, it is characterised in that the pixel electrode unit of these a plurality of repeated arrangement it
Between be provided with spacing distance, this transparency electrode is formed at and this battle array in extending to each neighboring area of each this pixel electrode unit
The overlapping region on direction that row substrate is vertical, the overlapping region between this transparency electrode and this pixel electrode unit forms storage
Capacitor.
Dot structure the most according to claim 1, it is characterised in that the extension of this transparency electrode is additionally provided with perforate,
Extend through for accommodating this contact hole.
Array base palte the most according to claim 1, it is characterised in that this transparency electrode sets being perpendicular on this orientation substrate
It is placed between this pixel electrode and this data wire.
5. according to the dot structure described in any one of claim 1-4, it is characterised in that cover niobium oxide above this transparency electrode
Thin film.
6. according to the array base palte described in any one of claim 1-4, it is characterised in that the material of this transparency electrode uses stannum to mix
Miscellaneous three Indium sesquioxide .s, aluminium-doped zinc oxide, nano-silver thread or Graphene.
7. an array base palte, including:
One substrate, this substrate is sequentially formed with the first metal layer, gate insulator, semiconductor layer, the second metal level, and protection is absolutely
Edge layer, insulating thick film layer, transparency electrode, isolated insulation layer, pixel electrode；
Wherein, the pattern that the first metal layer is formed includes plural number bar scan line, and the pattern that the second metal level is formed includes plural number bar
Data wire and drain electrode, this plural number data line and this plural number bar scan line are cross arranged crosswise；
Active member, including: source electrode, it is arranged on this data wire pattern of cross intersection region, grid, is arranged on cross friendship
This scan line pattern in fork region, and drain electrode；
Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region,
And the drain electrode electric connection of isolated insulation layer, insulating barrier and this active member is run through by a contact hole；
Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extends to the region of each this pixel electrode unit
Inside it is formed with the open area of a plurality of repeated arrangement, in the region of each this pixel electrode unit, is also formed with this transparent
The extension of electrode, this extension at least covers this data wire in cross arranged crosswise and this scan line, this transparency electrode
Extension be additionally provided with perforate, be used for accommodating this contact hole and extend through.
8. an array base palte, including:
One substrate, this substrate is sequentially formed with the first metal layer, gate insulator, semiconductor layer, and the second metal level, protection are absolutely
Edge layer, transparency electrode, insulating thick film layer, pixel electrode；
Wherein, the pattern that the first metal layer is formed includes plural number bar scan line, and the pattern that the second metal level is formed includes plural number bar
Data wire and drain electrode, this plural number data line and this plural number bar scan line are cross arranged crosswise；
Active member, including: source electrode, it is arranged on this data wire pattern of cross intersection region, grid, is arranged on cross friendship
This scan line pattern in fork region, and drain electrode；
Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region,
And the drain electrode electric connection of isolated insulation layer, insulating barrier and this active member is run through by a contact hole；Transparency electrode, in whole
Distribution on the substrate, and this transparency electrode extend to the region of each this pixel electrode unit in be formed and a plurality of repeat row
The open area of row, is also formed with the extension of this transparency electrode, this extension in the region of each this pixel electrode unit
Portion at least covers this data wire in cross arranged crosswise and this scan line, and the extension of this transparency electrode is additionally provided with out
Hole, is used for accommodating this contact hole and extends through.
9. a liquid crystal indicator, including:
Array base palte as described in claim 1-8；
Counter substrate, is oppositely arranged with this array base palte；
Liquid crystal layer, is interposed between this array base palte and this counter substrate；
Also include public electrode, be distributed in this counter substrate in face electrode pattern；
Wherein, this common electrode layer and this transparency electrode apply same potential voltage simultaneously.
10. a manufacture method for LCD device array substrates, including:
Thering is provided array basal plate, form first layer metal Thinfilm pattern, this first layer metal Thinfilm pattern includes plural number bar scanning
Line；
The pattern of this first metal layer is formed gate insulator, above this gate insulator, forms semiconductor pattern；
On this semiconductor pattern, forming second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number bar number
According to line, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), leakage
Pole；
Being distributed insulating barrier on this second layer metal Thinfilm pattern, the most whole EDS maps has transparency electrode；
In this transparency electrode be distributed isolated insulation layer, on this isolated insulation layer be distributed pixel electrode, this pixel electrode be with
Centered by cross intersection region between each this plural number data line and this plural number bar scan line, form a plurality of repetition and arrange
The pixel electrode unit of row, this pixel electrode unit is by running through a contact hole and the drain electrode of this isolated insulation layer and this insulating barrier
Realization is electrically connected；
Wherein, this transparency electrode is formed with the opening of a plurality of repeated arrangement in extending to the region of each this pixel electrode unit
Region, is also formed with the extension of this transparency electrode in the region of each this pixel electrode unit, and this extension at least covers
Lid this data wire in cross arranged crosswise and this scan line, the extension of this transparency electrode is additionally provided with perforate, is used for holding
Receiving this contact hole extends through.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454751.XA CN106094365A (en) | 2016-06-21 | 2016-06-21 | The manufacture method of liquid crystal indicator, array base palte and array base palte |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454751.XA CN106094365A (en) | 2016-06-21 | 2016-06-21 | The manufacture method of liquid crystal indicator, array base palte and array base palte |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106094365A true CN106094365A (en) | 2016-11-09 |
Family
ID=57237897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610454751.XA Pending CN106094365A (en) | 2016-06-21 | 2016-06-21 | The manufacture method of liquid crystal indicator, array base palte and array base palte |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106094365A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019024378A1 (en) * | 2017-08-01 | 2019-02-07 | 惠科股份有限公司 | Array substrate and display device |
| CN113097222A (en) * | 2020-10-14 | 2021-07-09 | 友达光电股份有限公司 | Display panel |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040013495A (en) * | 2002-08-07 | 2004-02-14 | 비오이 하이디스 테크놀로지 주식회사 | Vertical alingment liquid crystal display of symmetric type to all sides |
| WO2006085529A1 (en) * | 2005-02-09 | 2006-08-17 | Sharp Kabushiki Kaisha | Display device and display device manufacturing method |
| KR20080044047A (en) * | 2006-11-15 | 2008-05-20 | 삼성전자주식회사 | Thin film transistor substrate and liquid crystal display having the same |
| US20090225260A1 (en) * | 2008-03-04 | 2009-09-10 | Masaya Adachi | Liquid crystal display device |
| CN102385206A (en) * | 2011-11-01 | 2012-03-21 | 深圳市华星光电技术有限公司 | Pixel structure and corresponding liquid crystal display |
| US20120154700A1 (en) * | 2010-12-15 | 2012-06-21 | Kyoung Ju Shin | Thin film transistor array panel and liquid crystal display using the same |
| CN202330962U (en) * | 2011-11-01 | 2012-07-11 | 深圳市华星光电技术有限公司 | Pixel structure and corresponding liquid crystal display |
| CN104007591A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN104049429A (en) * | 2014-06-18 | 2014-09-17 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN104280959A (en) * | 2014-09-30 | 2015-01-14 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure, display panel and production method of pixel structure |
| CN204422935U (en) * | 2015-03-12 | 2015-06-24 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| US20150185578A1 (en) * | 2013-12-26 | 2015-07-02 | Japan Display Inc. | Liquid crystal display device |
| CN104865766A (en) * | 2015-06-17 | 2015-08-26 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure of multi-domain vertical alignment type liquid crystal |
| CN105223749A (en) * | 2015-10-10 | 2016-01-06 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
-
2016
- 2016-06-21 CN CN201610454751.XA patent/CN106094365A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040013495A (en) * | 2002-08-07 | 2004-02-14 | 비오이 하이디스 테크놀로지 주식회사 | Vertical alingment liquid crystal display of symmetric type to all sides |
| WO2006085529A1 (en) * | 2005-02-09 | 2006-08-17 | Sharp Kabushiki Kaisha | Display device and display device manufacturing method |
| KR20080044047A (en) * | 2006-11-15 | 2008-05-20 | 삼성전자주식회사 | Thin film transistor substrate and liquid crystal display having the same |
| US20090225260A1 (en) * | 2008-03-04 | 2009-09-10 | Masaya Adachi | Liquid crystal display device |
| US20120154700A1 (en) * | 2010-12-15 | 2012-06-21 | Kyoung Ju Shin | Thin film transistor array panel and liquid crystal display using the same |
| CN202330962U (en) * | 2011-11-01 | 2012-07-11 | 深圳市华星光电技术有限公司 | Pixel structure and corresponding liquid crystal display |
| CN102385206A (en) * | 2011-11-01 | 2012-03-21 | 深圳市华星光电技术有限公司 | Pixel structure and corresponding liquid crystal display |
| US20150185578A1 (en) * | 2013-12-26 | 2015-07-02 | Japan Display Inc. | Liquid crystal display device |
| CN104007591A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN104049429A (en) * | 2014-06-18 | 2014-09-17 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN104280959A (en) * | 2014-09-30 | 2015-01-14 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure, display panel and production method of pixel structure |
| CN204422935U (en) * | 2015-03-12 | 2015-06-24 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| CN104865766A (en) * | 2015-06-17 | 2015-08-26 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure of multi-domain vertical alignment type liquid crystal |
| CN105223749A (en) * | 2015-10-10 | 2016-01-06 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019024378A1 (en) * | 2017-08-01 | 2019-02-07 | 惠科股份有限公司 | Array substrate and display device |
| CN113097222A (en) * | 2020-10-14 | 2021-07-09 | 友达光电股份有限公司 | Display panel |
| CN113097222B (en) * | 2020-10-14 | 2023-06-02 | 友达光电股份有限公司 | Display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100374949C (en) | Liquid crystal display device and manufacturing method thereof | |
| CN101833200B (en) | Horizontal electric field type liquid crystal display device and manufacturing method thereof | |
| CN106019750A (en) | Liquid crystal display panel and display device | |
| CN106873226A (en) | A kind of touch-control display panel | |
| CN106842746A (en) | Active element array substrate and liquid crystal panel | |
| CN102193253A (en) | Liquid crystal display panel | |
| CN105739155A (en) | Touch substrate and touch liquid crystal display panel | |
| CN103439840A (en) | Array substrate, display device and method for manufacturing array substrate | |
| CN109445646A (en) | A kind of touch-control display panel and touch control display apparatus | |
| CN205539837U (en) | Liquid crystal display panel and display device | |
| CN106020581A (en) | Array substrate and touch display panel | |
| CN102253544A (en) | Liquid crystal display device | |
| CN105511146A (en) | Integrated touch display panel | |
| CN105093606A (en) | An array substrate, a liquid crystal display panel and a liquid crystal display device | |
| CN106298809A (en) | Thin-film transistor array base-plate and preparation method thereof, liquid crystal indicator | |
| CN103928471B (en) | A kind of array base palte and preparation method thereof, display device | |
| CN205787506U (en) | Array base palte and liquid crystal indicator | |
| CN102929056B (en) | A kind of array base palte and manufacture method, display device | |
| CN102385202A (en) | Liquid crystal display device | |
| CN104635393A (en) | Thin film transistor array substrate and liquid crystal display device | |
| CN106647058A (en) | Pixel unit and array substrate | |
| CN106094365A (en) | The manufacture method of liquid crystal indicator, array base palte and array base palte | |
| CN106125428A (en) | Pixel unit and display panel | |
| CN104181738B (en) | A kind of pixel cell, array base palte, display device and image element driving method | |
| CN206301117U (en) | A kind of liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161109 |
|
| WD01 | Invention patent application deemed withdrawn after publication |