CN103928471B - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN103928471B CN103928471B CN201410110718.6A CN201410110718A CN103928471B CN 103928471 B CN103928471 B CN 103928471B CN 201410110718 A CN201410110718 A CN 201410110718A CN 103928471 B CN103928471 B CN 103928471B
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- black matrix
- drain electrode
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- base palte
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Abstract
The embodiment of the invention discloses a kind of array base palte and preparation method thereof, display device, relate to Display Technique field, it is possible to ensure the display effect of display device.This array base palte, multiple pixel cells including array arrangement, described pixel cell includes thin film transistor (TFT) and pixel electrode, wherein, being provided with the first black matrix between drain electrode and the described pixel electrode of described thin film transistor (TFT), described first black matrix is formed with via, described drain electrode and described pixel electrode are connected by described via, described array base palte also includes: the second black matrix, and the corresponding described drain electrode of described second black matrix is arranged, and covers the via of described first black matrix.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
Owing to people in recent years are more and more higher for the requirement of the light transmittance of display device, resolution, power consumption etc., display dress
Put and all developing towards directions such as high permeability, high-resolution, low-power consumption.Wherein, resolution is the highest so that each pixel list
The size of unit is the least, when the length of side of pixel cell is become tens microns from tens microns, it is clear that the size of pixel cell obtains
Significantly reduce, now, if the width dividing the black matrix of pixel cell remains in that constant, relative to pixel cell
Speech, black matrix will be apparent from, it will affects the display effect of display device.
Therefore, BOA(Black matrix on Array) technology arises at the historic moment.Owing to now black matrix is positioned at array base
On plate, when suitably reducing the width of black matrix, also can guarantee that black matrix can fully block grid line, data wire and film crystal
Pipes etc. need the structure of shading, meanwhile, reduce the probability that light leakage phenomena occurs, protect again while improving resolution, transmitance
Demonstrate,prove the display effect of display device.
Inventor finds, after black matrix being incorporated on array base palte, owing to black matrix is usually located at film crystal
Between drain electrode and the pixel electrode of pipe, in order to realize the electrical connection between drain electrode and pixel electrode, need to be formed in black matrix
Hole, this via can affect the black matrix shaded effect to drain electrode, reduce the display effect of display device.
Summary of the invention
The technical problem to be solved is to provide a kind of array base palte and preparation method thereof, display device, energy
Enough ensure the display effect of display device.
For solving above-mentioned technical problem, the present invention adopts the following technical scheme that
First aspect present invention provides a kind of array base palte, including multiple pixel cells of array arrangement, described picture
Element unit includes thin film transistor (TFT) and pixel electrode, wherein, sets between drain electrode and the described pixel electrode of described thin film transistor (TFT)
Being equipped with the first black matrix, described first black matrix is formed with via, described drain electrode and described pixel electrode by described via even
Connecing, described array base palte also includes:
Second black matrix, the corresponding described drain electrode of described second black matrix is arranged, and covers the via of described first black matrix.
The size of described second black matrix is more than the size of described drain electrode.
Described array base palte also includes chock insulator matter, and corresponding described second black matrix of described chock insulator matter is arranged.
Described chock insulator matter and described second black matrix are formed in same patterning processes.
Described chock insulator matter is one-body molded with described second black matrix.
In the technical scheme of the embodiment of the present invention, it is provided that a kind of array base palte, this array base palte includes that array is arranged
Multiple pixel cells of cloth, each pixel cell includes the drain electrode of thin film transistor (TFT), pixel electrode, the first black matrix and second
Black matrix, wherein, the first black matrix is formed for making drain electrode and the via of pixel electrode electrical connection, and the second black matrix is corresponding
Described drain electrode is arranged, and covers the via of described first black matrix so that the via of the first black matrix will not produce reflective etc. bad
Phenomenon, it is ensured that the display effect of display device.
Second aspect present invention provides a kind of display device, including above-mentioned array base palte.
Third aspect present invention provides the preparation method of a kind of array base palte, including:
Forming the drain electrode of thin film transistor (TFT), the first black matrix and pixel electrode, wherein, described first black matrix is positioned at described
Between drain electrode and described pixel electrode, described first black matrix is formed with via, described drain electrode and described pixel electrode and passes through institute
State via to connect；
Forming the second black matrix, the corresponding described drain electrode of described second black matrix is arranged, and covers the mistake of described first black matrix
Hole.
The drain electrode of described formation thin film transistor (TFT), the first black matrix and pixel electrode include:
Form the drain electrode of thin film transistor (TFT)；
On described drain electrode, form the first black matrix；
On described first black matrix, form pixel electrode.
The size of described second black matrix is more than the size of described drain electrode.
Described preparation method also includes:
Forming chock insulator matter, corresponding described second black matrix of described chock insulator matter is arranged.
Described chock insulator matter and described second black matrix are formed in same patterning processes.
Described chock insulator matter is one-body molded with described second black matrix.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
The accompanying drawing used required in is briefly described, it should be apparent that, the accompanying drawing in describing below is only some of the present invention
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to attached according to these
Figure obtains other accompanying drawing.
Fig. 1 is the structural representation one of the array base palte in the embodiment of the present invention；
Fig. 2 is the structural representation two of the array base palte in the embodiment of the present invention；
Fig. 3 is the schematic flow sheet one of the preparation method of the array base palte in the embodiment of the present invention；
Fig. 4 is the schematic flow sheet two of the preparation method of the array base palte in the embodiment of the present invention.
Description of reference numerals:
1 underlay substrate；2 thin film transistor (TFT)s；21 drain electrodes；
22 grids；23 gate insulators；24 source electrodes；
25 active layers；3 pixel electrodes；4 first black matrix；
5 vias；6 second black matrix；7 color filter layer；
8 first insulating barriers；9 chock insulator matters；10 public electrodes；
11 second insulating barriers.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is a part of embodiment of the present invention rather than whole embodiments wholely.Based on this
Embodiment in bright, the every other enforcement that those of ordinary skill in the art are obtained under not making creative work premise
Example, broadly falls into the scope of protection of the invention.
Embodiment one
The embodiment of the present invention provides a kind of array base palte, and this array base palte includes:
Including multiple pixel cells of the array arrangement being arranged on underlay substrate 1, as it is shown in figure 1, described pixel list
Unit includes thin film transistor (TFT) 2 and pixel electrode 3, wherein, between drain electrode 21 and the described pixel electrode 3 of described thin film transistor (TFT) 2
Being provided with the first black matrix 4, described first black matrix 4 is formed with via 5, and described drain electrode 21 and described pixel electrode 3 pass through institute
Stating via 5 to connect, described array base palte also includes:
Second black matrix 6, the described second corresponding described drain electrode 21 of black matrix 6 is arranged, and covers the mistake of described first black matrix 4
Hole.
As it is shown in figure 1, owing to the first black matrix 4 needs shading for fully blocking grid line, data wire and thin film transistor (TFT) 2 etc.
Structure, therefore, the first black matrix 4 is typically to cover on thin film transistor (TFT) 2, and simultaneously in order to ensure thin film transistor (TFT) 2
Drain electrode 21 and pixel electrode 3 between connection, be formed with via 5 with the first black matrix 4, this via 5 can affect the first black square
The shaded effect of battle array 4.In order to ensure the shaded effect of the first black matrix 4 as far as possible, technical staff this via 5 is done as far as possible
Little, increase the manufacture difficulty of via 5, the material requirements to the first black matrix 4 is higher simultaneously.Further, since at via 5 region
Do not have the first black matrix 4 to cover, simultaneously because drain electrode 21 typically uses metal to make, under the external environment that light is stronger, use
Family can be clearly felt that the light that drain electrode 21 metallic reflection of via 5 correspondence goes out, and causes user not see the display of display device
Picture, reduces the experience of user.
And in embodiments of the present invention, the second black matrix 6 formed on the via 5 of the first black matrix 4 can effectively be protected
The display effect of card display device, simultaneously, it is not necessary to reduce the size of the via 5 of the first black matrix 4.
In the technical scheme of the present embodiment, it is provided that a kind of array base palte, this array base palte includes what array was arranged
Multiple pixel cells, each pixel cell includes the drain electrode of thin film transistor (TFT), pixel electrode, the first black matrix and the second black square
Battle array, wherein, the first black matrix is formed for making drain electrode and the via of pixel electrode electrical connection, described in the second black matrix correspondence
Drain electrode is arranged, and covers the via of described first black matrix so that the via of the first black matrix will not produce the bad phenomenon such as reflective,
Ensure that the display effect of display device.
Obviously, as it is shown in figure 1, thin film transistor (TFT) also includes other Rotating fields in addition to drain electrode 21, concrete, thin film is brilliant
Body pipe 2 includes from the bottom to top: grid 22, gate insulator 23, the source electrode 24 with layer setting and insulated and drain electrode 21 and connection
Source electrode 24 and the active layer 25 of drain electrode 21.
For the ease of para-position, making between the first black matrix 4 and color filter layer 7, as it is shown in figure 1, at thin film transistor (TFT) 2
On formed color filter layer 7, generally, color filter layer 7 at least includes the colors such as red, green, blue.Afterwards, in color filter layer 7
On form the first black matrix 4.For the ease of follow-up easy to make, also on the first black matrix 4, cover a layer thickness relatively
The first big insulating barrier 8.
Further, since the figure of the first black matrix 4 is different from the figure of drain electrode 21, therefore, the first black matrix 4 and drain electrode 21
It is respectively adopted different mask plate, formed by patterning processes.If when forming the first black matrix 4, covering of the first black matrix 4
Bit errors is there is, it is likely that cause via 5 part of the first black matrix 4 to be positioned at drain electrode between the mask plate of lamina membranacea and drain electrode 21
Outside the correspondence position of 21, i.e. the via 21 projection section in drain electrode 21 is positioned at outside drain electrode 21, time serious, can cause backlight
The light that source sends spills from via 5, reduces the display effect of display device.
And in embodiments of the present invention, as shown in Figure 1, it is preferred that the size of described second black matrix 6 formed is more than
The size of described drain electrode 21, can effectively prevent the generation of above-mentioned bad phenomenon.
General, display panels include array base palte, array base palte to box substrate and be encapsulated in array base palte
And to the liquid crystal layer between box substrate, typically in order to ensure the display effect of display panels, need to maintain liquid crystal layer
Thickness, prevents liquid crystal layer extrusion from cannot normally show.Accordingly, it would be desirable to array base palte and to box substrate between,
Distribution arranges some chock insulator matters.Same, in embodiments of the present invention, as it is shown in figure 1, described array base palte also includes chock insulator matter
9, in order to prevent chock insulator matter 9 from affecting the display effect of display device, it is preferred that corresponding described second black matrix 6 of described chock insulator matter 9
Arrange.
In order to reduce the preparation cost of array base palte, owing to corresponding second black matrix 6 of chock insulator matter 9 is arranged, it is therefore preferable that
, described chock insulator matter 9 is formed in same patterning processes with described second black matrix 6.
Further, described chock insulator matter 9 also can be one-body molded with described second black matrix 6.
It should be noted that the thin film transistor (TFT) 2 in array base palte in Fig. 1 of the present invention is bottom gate thin film transistor,
Being similar to, thin film transistor (TFT) 2 is also chosen as top gate type.The structure of the thin film transistor (TFT) 2 of top gate type and the bottom gate type shown in Fig. 1
Be close on the contrary, i.e. the thin film transistor (TFT) 2 of top gate type includes from the bottom to top: with layer setting and the source electrode 24 of insulation and drain electrode 21, connect
Connect source electrode 24 and active layer 25, gate insulator 23 and the grid 22 of drain electrode 21.Specific implementation is the present invention repeat no more.
Obviously, the array base palte shown in Fig. 1 is twisted nematic (Twisted Nematic the is called for short TN) mould of COA technique
The array base palte of formula.On this basis, it may be considered that the structure of the array base palte shown in Fig. 1 is improved, such as, such as Fig. 2
Shown in, this array base palte also includes the public electrode coordinated with described pixel electrode 3 on the basis of the array base palte shown in Fig. 1
10, insulation pixel electrode 3 and the second insulating barrier 11 of public electrode 10, now this array base palte is the senior super dimension of COA technique
The array base palte of field conversion (Advanced Super Dimension Switch is called for short ADS) pattern.It should be noted that
In Fig. 2, this pixel electrode 3 is positioned on public electrode 10, for slit-shaped.
Or, this array base palte also includes being positioned on described pixel electrode 3 on the basis of the array base palte shown in Fig. 1
Organic layer and conductive layer, described pixel electrode 3 coordinates with described conductive layer and common drives described organic layer luminous, the most now
Array base palte is the array base of Organic Light Emitting Diode (Organic Light-Emitting Diode is called for short OLED) pattern
Plate.
Embodiments providing a kind of display device, this display device includes above-mentioned array base palte, including above-mentioned
Any one array base palte.Concrete, this display device can be: liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid
Crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any display function.
Embodiment two
The embodiment of the present invention provides the preparation method of a kind of array base palte, as it is shown on figure 3, this preparation method includes:
Step S101, the formation drain electrode of thin film transistor (TFT), the first black matrix and pixel electrode, wherein, described first black square
Battle array is between described drain electrode and described pixel electrode, and described first black matrix is formed with via, described drain electrode and described pixel
Electrode is connected by described via.
Step S102, second black matrix that formed, the described second corresponding described drain electrode of black matrix is arranged, and covers described first black
The via of matrix.
Wherein, it is preferred that the size of described second black matrix 6 is more than the size of described drain electrode 21.
It is wherein, concrete, according to the structure of the array base palte shown in Fig. 1 or Fig. 2, it is known that, step S101 can include as follows
Step:
Step S1011, the drain electrode of formation thin film transistor (TFT).
Step S1012, on described drain electrode, form the first black matrix.
Step S1013, on described first black matrix, formed pixel electrode.
Further, preparation method provided by the present invention also includes:
Forming chock insulator matter 9, corresponding described second black matrix 6 of described chock insulator matter 9 is arranged.
Preferably, described chock insulator matter 9 is formed in same patterning processes with described second black matrix 6.
Wherein, it is preferred that described chock insulator matter 9 is one-body molded with described second black matrix 6.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art, in the technical scope that the invention discloses, can readily occur in change or replace, should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (12)
1. an array base palte, including array arrangement multiple pixel cells, described pixel cell include thin film transistor (TFT) and
Pixel electrode, wherein, is provided with the first black matrix between drain electrode and the described pixel electrode of described thin film transistor (TFT), and described first
Black matrix is formed with via, described drain electrode and described pixel electrode and is connected by described via, it is characterised in that described array base
Plate also includes:
Second black matrix, the corresponding described drain electrode of described second black matrix is arranged, and covers the via of described first black matrix.
Array base palte the most according to claim 1, it is characterised in that
The size of described second black matrix is more than the size of described drain electrode.
Array base palte the most according to claim 1 and 2, it is characterised in that described array base palte also includes chock insulator matter, described
Corresponding described second black matrix of chock insulator matter is arranged.
Array base palte the most according to claim 3, it is characterised in that described chock insulator matter and described second black matrix are same
Patterning processes is formed.
Array base palte the most according to claim 3, it is characterised in that described chock insulator matter becomes with described second black matrix one
Type.
6. a display device, it is characterised in that include the array base palte as described in any one of claim 1-5.
7. the preparation method of an array base palte, it is characterised in that including:
Forming the drain electrode of thin film transistor (TFT), the first black matrix and pixel electrode, wherein, described first black matrix is positioned at described drain electrode
With between described pixel electrode, described first black matrix is formed with via, described drain electrode and described pixel electrode by described mistake
Hole connects；
Forming the second black matrix, the corresponding described drain electrode of described second black matrix is arranged, and covers the via of described first black matrix.
Preparation method the most according to claim 7, it is characterised in that the drain electrode of described formation thin film transistor (TFT), first black
Matrix and pixel electrode include:
Form the drain electrode of thin film transistor (TFT)；
On described drain electrode, form the first black matrix；
On described first black matrix, form pixel electrode.
9. according to the preparation method described in claim 7 or 8, it is characterised in that
The size of described second black matrix is more than the size of described drain electrode.
Preparation method the most according to claim 9, it is characterised in that also include:
Forming chock insulator matter, corresponding described second black matrix of described chock insulator matter is arranged.
11. preparation methoies according to claim 10, it is characterised in that
Described chock insulator matter and described second black matrix are formed in same patterning processes.
12. preparation methoies according to claim 11, it is characterised in that
Described chock insulator matter is one-body molded with described second black matrix.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104360527A (en) * | 2014-11-03 | 2015-02-18 | 合肥鑫晟光电科技有限公司 | Array substrate and manufacturing method thereof and display device |
| TW201712417A (en) * | 2015-09-18 | 2017-04-01 | 友達光電股份有限公司 | Display panel |
| CN105353571A (en) * | 2015-11-27 | 2016-02-24 | 深圳市华星光电技术有限公司 | COA substrate, liquid crystal display panel and liquid crystal display device |
| CN109270751B (en) * | 2018-10-23 | 2020-10-30 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN112014998B (en) * | 2020-09-14 | 2023-01-24 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
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| CN1936660A (en) * | 2005-09-20 | 2007-03-28 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| CN101030586A (en) * | 2006-06-05 | 2007-09-05 | 友达光电股份有限公司 | Thin-film transistor array base-plate structure and its production |
| CN202256970U (en) * | 2011-08-09 | 2012-05-30 | 京东方科技集团股份有限公司 | Spacer, liquid crystal display panel and display device |
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|---|---|---|---|---|
| TW565720B (en) * | 2002-02-20 | 2003-12-11 | Hannstar Display Corp | Liquid crystal display with a wide viewing angle |
| KR100662780B1 (en) * | 2002-12-18 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device having test pixel and fabricating method of black matrix using the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1936660A (en) * | 2005-09-20 | 2007-03-28 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| CN101030586A (en) * | 2006-06-05 | 2007-09-05 | 友达光电股份有限公司 | Thin-film transistor array base-plate structure and its production |
| CN202256970U (en) * | 2011-08-09 | 2012-05-30 | 京东方科技集团股份有限公司 | Spacer, liquid crystal display panel and display device |
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