CN102929058B - Array substrate, manufacturing method of array substrate, and display device - Google Patents
Array substrate, manufacturing method of array substrate, and display device Download PDFInfo
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- CN102929058B CN102929058B CN201210452632.2A CN201210452632A CN102929058B CN 102929058 B CN102929058 B CN 102929058B CN 201210452632 A CN201210452632 A CN 201210452632A CN 102929058 B CN102929058 B CN 102929058B
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Abstract
The invention discloses an array substrate, a manufacturing method of the array substrate, and a display device, relating to the field of displays. The influence of alignment deviation of the array substrate and a color film substrate on transmittance can be reduced to avoid the light leakage caused by the alignment deviation, and the insulativity of a signal line can be also enhanced at the same time to reduce the power consumption of a panel. The array substrate comprises a substrate, a thin film transistor arranged on the substrate, a pixel electrode and a passivation layer, wherein the passivation layer covers the thin film transistor; and the pixel electrode is arranged above the passivation layer. The array substrate further comprises a patterned color resistance layer and a black matrix, wherein the color resistance layer is arranged between the substrate and a grid insulation layer and distributed in a region corresponding to the pixel electrode; and the black matrix is arranged on the passivation layer and positioned in a region outside the region corresponding to the color resistance layer. The method comprises the steps as follows: forming a grid line and a grid; manufacturing the color resistance layer; forming the grid insulation layer, an active layer, source and drain electrode layers and the passivation layer; forming the black matrix; and forming the pixel electrode.
Description
Technical field
The present invention relates to display field, particularly relate to a kind of array base palte and manufacture method, display device.
Background technology
Liquid crystal display has now been widely used in each display field, as family, public place, office field and personal electric Related product etc.At present, liquid crystal display is simple from making, twisted-nematic (the Twisted Nematic that with low cost but visual angle is less, TN) type liquid crystal display, develop into multi-dimensional electric field (Advanced Super Dimension Switch, AD-SDS, be called for short ADS) type liquid crystal display, and based on the HADS type liquid crystal display of high aperture that ADS pattern proposes, no matter any liquid crystal display, the manufacture craft of its liquid crystal panel is all independent manufacturing array (Array) substrate and color film (Color Filter) substrate, and then array base palte and color membrane substrates are carried out contraposition, become box (Cell).
Inventor finds: when array base palte becomes box with color membrane substrates contraposition, due to the restriction of aligning accuracy, very easily occur contraposition deviation, and contraposition deviation can cause light leak, transmitance reduction etc. bad; If that is done by black matrix enough widely avoids these problems, the transmitance of panel can be lost again, increase backlight cost.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of array base palte and manufacture method, display device, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoid the light leak that contraposition deviation causes.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprising: substrate, is arranged at the thin film transistor (TFT) on described substrate, pixel electrode, and passivation layer, and described thin film transistor (TFT) comprises grid, gate insulation layer, semiconductor layer, source electrode and drain electrode; Described passivation layer covers described thin film transistor (TFT), and described pixel electrode is arranged on the top of described passivation layer, also comprises: the color blocking layer of patterning and black matrix;
Described color blocking layer is arranged between described substrate and described gate insulation layer, and is distributed in described pixel electrode corresponding region;
Described black arranged in matrix on described passivation layer, and is positioned at the region beyond described color blocking layer corresponding region.
Particularly, the described black matrix on described passivation layer and described passivation layer, the drain electrode correspondence position of described thin film transistor (TFT) is provided with via hole, and described pixel electrode is connected to described drain electrode through described via hole.
Alternatively, described array base palte, also comprises:
Public electrode, is arranged between described substrate and described gate insulation layer, and is arranged on described pixel electrode corresponding region.
Alternatively, described pixel electrode is slit-shaped.
Alternatively, described array base palte, also comprises:
Second passivation layer, covers on described black matrix and described pixel electrode;
Public electrode, to be positioned at above described second passivation layer and to be arranged on the corresponding region of described pixel electrode.
Described public electrode is slit-shaped.
The present invention also provides a kind of display device, comprises above-mentioned arbitrary array base palte.
On the other hand, the present invention also provides a kind of manufacture method of array base palte, comprising:
Substrate is formed grid metal level, adopts patterning processes to form grid line and grid;
Color blocking layer is formed in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix;
Form transparent conductive film layer, adopt patterning processes to form pixel electrode.
The manufacture method of the second array base palte provided by the invention, comprising:
Substrate is formed the first transparent conductive film layer, adopts patterning processes to form public electrode;
Form grid metal level, adopt patterning processes to form grid line and grid;
Color blocking layer is formed in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix;
Form the second transparent conductive film layer, adopt patterning processes to form pixel electrode.
The manufacture method of the third array base palte provided by the invention, comprising:
Form grid metal level, adopt patterning processes to form grid line and grid;
Color blocking layer is formed in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix;
Form the first transparent conductive film layer, adopt patterning processes to form pixel electrode;
Form the second passivation layer;
Prepare the second transparent conductive film layer, adopt patterning processes to form public electrode.
Array base palte provided by the invention and manufacture method, display device, relate to a kind of array base palte being provided with color film color blocking and black matrix, and a kind of method color film color blocking and black matrix are formed on array base palte, this technical scheme is by being arranged on substrate by the color blocking layer of patterning, black arranged in matrix over the passivation layer, reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, can avoid the light leak that contraposition deviation causes, passivation layer can also strengthen the adhesiveness between black matrix and array base palte simultaneously.
In addition, color blocking layer as signal line (gate line) insulation course, can reduce the load of gate line, ensures pixel charging; Black matrix can as the insulation course of data signal line (data line), and reduce data line load and then reduce panel power consumption, this is even more important to high-resolution products.
Accompanying drawing explanation
The section structure schematic diagram of the array base palte that Fig. 1 provides for the embodiment of the present invention one;
Fig. 2 is the planar structure schematic diagram one of array base palte in the embodiment of the present invention one;
Fig. 3 is the planar structure schematic diagram two of array base palte in the embodiment of the present invention one;
Fig. 4 is the cross section structure schematic diagram of array base palte near grid line in the embodiment of the present invention one;
Fig. 5 is the cross section structure schematic diagram of array base palte near data line in the embodiment of the present invention one;
Fig. 6 is the process flow diagram of manufacturing method of array base plate in the embodiment of the present invention one;
The structural representation of the array base palte that Fig. 7 provides for the embodiment of the present invention two;
Fig. 8 is the planar structure schematic diagram of array base palte in the embodiment of the present invention two;
Fig. 9 is the manufacture method process flow diagram of array base palte in the embodiment of the present invention two;
The structural representation of the array base palte that Figure 10 provides for the embodiment of the present invention three;
Figure 11 is the planar structure schematic diagram of array base palte in the embodiment of the present invention three;
Figure 12 is the manufacture method process flow diagram of array base palte in the embodiment of the present invention three.
Description of reference numerals
10-substrate, 11-passivation layer, 12-pixel electrode, 13-color blocking layer, the black matrix of 14-,
15-via hole, 16-thin film transistor (TFT), 17-data line, 18-grid line, 19-public electrode wire,
20-public electrode, 21-grid, 22-gate insulation layer, 23-active layer, 24-source electrode,
25-drains, 26-second passivation layer.
Embodiment
The embodiment of the present invention provides a kind of array base palte and manufacture method, display device, array base palte and color membrane substrates contraposition deviation can be reduced on the impact of transmitance, avoid the light leak that contraposition deviation causes, also can strengthen signal wire insulativity simultaneously, reduce panel power consumption.
The embodiment of the present invention provides a kind of array base palte, this array base palte comprises: substrate, be arranged at the thin film transistor (TFT) on substrate, pixel electrode, and passivation layer, described thin film transistor (TFT) comprises grid, gate insulation layer, active layer, source electrode and drain electrode, passivation layer cover film transistor, pixel electrode is arranged on the top of passivation layer, also comprises: the color blocking layer of patterning and black matrix;
Described color blocking layer is arranged between substrate and gate insulation layer, and is distributed in pixel electrode corresponding region; Described black arranged in matrix over the passivation layer, and is positioned at the region beyond color blocking layer corresponding region.
Color blocking layer described in the present embodiment refer to cover pixel electrode corresponding region red/green/the color film of primary colors, in the present embodiment by color blocking layer and black arranged in matrix on array base palte, wherein, color blocking layer is positioned on the substrate of array base palte, black arranged in matrix over the passivation layer, and the region be positioned at beyond color blocking layer corresponding region (pixel electrode), array base palte and color membrane substrates contraposition deviation can be reduced on the impact of transmitance, avoid the light leak that contraposition deviation causes, passivation layer can also strengthen the adhesiveness between black matrix and array base palte simultaneously.In addition, color blocking layer and black Matrix cover, on signal wire (such as grid line or data line), also can be used as the insulation course of signal wire, can reduce load of signal line, and then reduce panel power consumption.
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.Embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Embodiment one
As shown in Figure 1, the embodiment of the present invention provides one to be applicable to the array base palte of TN product (TN pattern), this array base palte comprises: substrate 10, be arranged at thin film transistor (TFT) on substrate 10, pixel electrode 12, and passivation layer 11, described thin film transistor (TFT) comprises grid (Gate) 21, gate insulation layer (GI) 22, active layer (Active) 23, source electrode (Source) 24 and drain electrode 25 (Drain); Passivation layer 11 cover film transistor, pixel electrode arranges the top that 12 are arranged on passivation layer 11, in addition, also comprises: the color blocking layer 13 of patterning and black matrix 14;
Wherein, described color blocking layer 13 is arranged between substrate 10 and gate insulation layer 22, and is distributed in pixel electrode 12 corresponding region; Described black matrix 14 is arranged on passivation layer 11, and is positioned at the region beyond color blocking layer 13 corresponding region.
The present embodiment gate insulation layer is directly provided with red/green/blue block (color blocking layer 13) on the substrate of pixel electrode 12 corresponding region, color blocking layer 13 is coated with gate insulation layer 22, gate insulation layer 22 covers passivation layer 11, pixel electrode 12 is arranged on the top of color blocking layer 13 across gate insulation layer (GI) 22 and passivation layer 11.
Color blocking layer 13 described in the present embodiment, is red/green/blue (R/G/B) color lump being laid on pixel electrode 12 corresponding region, also known as color film color blocking layer; Black matrix 14 is arranged on passivation layer 11, and is distributed in the region outside red/green/blue block corresponding region.Particularly: red/green/blue block (color blocking layer 13) covers the corresponding region of pixel electrode 12, as the region that solid line A in Fig. 2 surrounds; Black matrix 14 is arranged on the region outside red/green/blue block (color blocking layer 13), as the region that two dotted line B in Fig. 3 surround.In concrete enforcement, for preventing light leak, the coverage of red/green/blue block generally exceeds the corresponding region of pixel electrode 12 a little, there is overlapping region with the joint of black matrix 14 overlay area.
The array base palte that the embodiment of the present invention provides, color blocking layer is set directly on substrate, easily obtains smooth, that thickness is consistent red/green/blue block during making, with to make color blocking layer in prior art on the substrate of color membrane substrates consistent, without the need to overcoming technical barrier; In addition, over the passivation layer, because of the adhesive attraction of passivation layer, black matrix can be bonded on array base palte black arranged in matrix more firmly.Therefore, the array base palte of the present embodiment, because being provided with color blocking layer and black matrix, can reducing array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoid the light leak that contraposition deviation causes, thus improves transmitance and the display effect of display device.
In addition, as shown in Figure 4, be the schematic cross-section of TN pattern array substrate near grid line 18 in the present embodiment.As we know from the figure, compared with the structure of existing TN pattern array substrate, resistance layer 13 (R/G/B layer) of the same colour is increased above grid line 18, and color blocking layer 18 specific inductive capacity is less, thickness is thicker, thus make grid line 18 and directly over electric capacity between public electrode 20 (being positioned on color membrane substrates) significantly reduce, thus reach load on reduction grid line 18, ensure the object of pixel charging, this is particularly important for high-resolution products.
Further, as shown in Figure 5, be the schematic cross-section of TN pattern array substrate near data line 17 in the present embodiment.As we know from the figure, compared with the structure of existing TN pattern array substrate, the black matrix 14 of one deck is added above data line 17, and because of 14 layers, black matrix, specific inductive capacity is little, thickness is large, thus make data line 17 and directly over coupling capacitance between public electrode 20, and the coupling capacitance between data line 17 and pixel electrode (not shown) significantly reduces, thus make the load reduction on data line 17, and then panel lower power consumption.
Wherein, the black matrix 14 on passivation layer 11 and passivation layer 11, drain electrode 25 correspondence position of thin film transistor (TFT) is provided with via hole 15, and pixel electrode 12 is connected to drain electrode 25 through via hole 15, as shown in fig. 1.
Array base palte described in the present embodiment is provided with color blocking layer and black matrix, therefore array base palte and the impact of color membrane substrates contraposition deviation on transmitance are minimized, the light leak simultaneously contraposition deviation also can being avoided to cause, and passivation layer can also strengthen the adhesiveness between black matrix and array base palte.In addition, color blocking layer and black matrix also can be used as the insulation course of signal wire, reduce load of signal line, and then reduce panel power consumption.
The embodiment of the present invention also provides a kind of manufacture method being applicable to the array base palte of TN product, and as shown in Figure 6, the method comprises:
Step 101, on the substrate 10 formation grid metal level, adopt patterning processes to form grid line 18 and grid 21 (for ease of understanding, please refer to shown in Fig. 1-5);
On substrate, form grid metal level in this step, adopt patterning processes to form grid line and grid, concrete formation method is consistent with prior art, does not repeat them here.
Step 102, form color blocking layer 13 in pixel electrode 12 corresponding region;
This step forms color blocking layer on the substrate of pixel electrode corresponding region, namely applies red/green/blue block, and concrete formation method is consistent with prior art.
Step 103, routinely flow process form gate insulation layer 22, active layer 23, source-drain electrode layer (source electrode 24, drain electrode 25 and data line 17), passivation layer 11;
Step 104, form black matrix layer, adopt the region of patterning processes beyond color blocking layer 13 corresponding region to form black matrix 14;
Prepare black matrix over the passivation layer in this step, utilize the adhesive attraction of passivation layer, black matrix is fixed on array base palte more firmly.
Step 105, prepare transparent conductive film layer, adopt patterning processes to form pixel electrode 12.
Wherein, adopt the region of patterning processes beyond color blocking layer 13 corresponding region to form black matrix 14 in step 104, be specially:
Adopt the region of patterning processes beyond color blocking layer 13 corresponding region to form black matrix 14, and arrange via hole 15 at drain electrode 25 correspondence position of thin film transistor (TFT), pixel electrode 12 is connected to drain electrode 25 through this via hole 15.
Particularly, for the 5Mask technique that TN pattern in prior art is conventional, the manufacturing method of array base plate technical process that the present embodiment proposes is:
Form grid and grid line → formation R/B/G color blocking layer (three exposures) → formation gate insulation layer (not needing exposure technology) → be formed with active layer → formation source, drain electrode layer → formation pixel insulation course (passivation layer) → form black matrix layer (BM) → formation transparent conductive film layer (pixel electrode) successively, altogether need through 9 exposure technologys.
In addition, for the 4Mask technique that TN pattern in prior art is conventional, the manufacturing method of array base plate technical process that the present embodiment proposes is:
Form grid and grid line → formation R/B/G color blocking layer (three exposures) → formation gate insulation layer (not needing exposure technology) → form source, drain electrode layer → formation pixel insulation course (passivation layer) → form black matrix layer (BM) → formation transparent conductive film layer (pixel electrode) successively, altogether need through 8 exposure technologys.Wherein, active layer and source, drain electrode and grid line, by single exposure, multiple etching is formed.
The manufacture method of array base palte described in the present embodiment, by color blocking layer and black arranged in matrix on array base palte, array base palte and color membrane substrates contraposition deviation can be reduced on the impact of transmitance, avoid the light leak that contraposition deviation causes, passivation layer can also strengthen the adhesiveness between black matrix and array base palte simultaneously.In addition, color blocking layer and black matrix also can be used as the insulation course of signal wire, can reduce load of signal line, and then reduce panel power consumption.
Embodiment two
The embodiment of the present invention provides one to be applicable to the array base palte of ADS product (ADS pattern), as shown in Figure 7, described in this array base palte and embodiment one, the difference part of array base palte is, also comprises: public electrode 20, is arranged between substrate 10 and color blocking layer 13; In addition, because ADS pattern array substrate adopts multi-dimensional electric field, the pixel electrode 12 therefore in the present embodiment is slit-shaped, as shown in Figure 8.
It should be noted that: pixel electrode can for tabular or slit-shaped, and public electrode is also like this, the order up and down of pixel electrode and public electrode can be put upside down, but must be slit-shaped at upper electrode, under electrode be tabular.
Particularly, this array base palte comprises: substrate 10, be arranged at the thin film transistor (TFT) 16 on substrate 10, thin film transistor (TFT) 16 comprises: grid (Gate) 21, gate insulation layer (GI) 22, active layer (Active) 23, source electrode (Source) 24 and drain electrode 25 (Drain); Public electrode 20, the color blocking layer 13 of patterning, passivation layer 11, pixel electrode 12.Wherein, passivation layer 11 covers in source electrode 24 and drain electrode 25, and pixel electrode 12 is arranged on passivation layer 11; Color blocking layer 13 is arranged on pixel electrode 12 corresponding region, is positioned on public electrode 20; Black matrix 14 is arranged on passivation layer 11, and is positioned at the region beyond color blocking layer 13 corresponding region; Passivation layer 11 and black matrix 14 are provided with via hole 15 at drain electrode 25 correspondence position, and pixel electrode 12 is connected to drain electrode 25 by this via hole 15.
Wherein, exemplarily, in described ADS pattern array substrate, the distributed areas of color blocking layer 13 and black matrix 14 as shown in Figure 8, arranges red/green/blue block (color blocking layer 13) in figure in solid line A institute region, arranges black matrix 14 in figure in two dotted line B institute regions.
A kind of ADS array base palte being provided with color blocking layer and black matrix is provided in the present embodiment, compared with existing ADS pattern array substrate, array base palte in the present embodiment, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoid the light leak that contraposition deviation causes.
And, compared with the structure of existing ADS pattern array substrate, above grid line 18, increase resistance layer 13 (R/G/B layer) of the same colour, the black matrix 14 of one deck is increased above data line 17, color blocking layer 13, as the insulation course of grid line 18, can reduce the load of gate line, ensures pixel charging; Black matrix is as the insulation course of data line 17, and can reduce data-signal linear load and then reduce panel power consumption, this is even more important to high-resolution products.
In addition, public electrode 20 in the present embodiment can be arranged between color blocking layer 13 and gate insulation layer 22, therefore public electrode 20 also can be arranged on color blocking layer 13, and be positioned at the below of gate insulation layer 22, that is: the setting position of color blocking layer 13 and public electrode 20 can be exchanged up and down, and color blocking layer 13 can be set directly on substrate, and color blocking layer 13 arranges public electrode 20 again, do not affect the concrete implementation result of the present embodiment, therefore the present embodiment does not limit this.
Accordingly, the embodiment of the present invention also provides a kind of manufacture method of array base palte, and be applicable to ADS pattern array substrate, as shown in Figure 9, the method comprises:
Step 201, on substrate, form the first transparent conductive film layer, adopt patterning processes to form public electrode (for ease of understanding, below describing and please refer to shown in Fig. 7);
Step 202, formation grid metal level, adopt patterning processes to form grid line 21 and grid;
Step 203, making color blocking layer 13, form red/green/blue block in pixel electrode 12 corresponding region:
Step 204, routinely flow process form gate insulation layer 22, active layer 23, source-drain electrode layer and passivation layer 11;
Step 205, form black matrix layer, adopt the region of patterning processes beyond color blocking layer 13 corresponding region to form black matrix 14;
Step 206, form the second transparent conductive film layer, adopt patterning processes to form pixel electrode 12.
When step 204 forms passivation layer 11 in the present embodiment and when step 205 forms black matrix 14, all via hole 15 is set at the drain same position of 25 correspondences of thin film transistor (TFT), is connected to drain electrode 25 for pixel electrode 12 through this via hole 15.
Particularly, for the 1+5Mask technique that ADS pattern in prior art is conventional, the technical process of manufacturing method of array base plate described in the present embodiment is:
Form the first transparent conductive film layer (public electrode Com) → formation grid and grid line → formed successively R/B/G color blocking layer (three exposures) → formed gate insulation layer (not needing exposure technology) → be formed with active layer → formation source, drain electrode layer → formation pixel insulation course (passivation layer) → formed black matrix (BM) → form the second transparent conductive film layer (pixel electrode), altogether need through 10 exposure technologys.
And for the 1+4Mask technique that ADS pattern in prior art is commonly used, the manufacturing method of array base plate technical process that the present embodiment proposes is:
Form the first transparent conductive film layer (public electrode Com) → formation grid and grid line → formed successively R/B/G color blocking layer (three exposures) → formed gate insulation layer (not needing exposure technology) → formed source, drain electrode layer → formation pixel insulation course (passivation layer) → formed black matrix (BM) → form the second transparent conductive film layer (pixel electrode), altogether need through 9 exposure technologys.
Wherein, above-mentioned formation public electrode can be exchanged with the exposure order forming grid.
A kind of the ADS array base palte and the manufacture method thereof that are provided with color blocking layer and black matrix is provided in the present embodiment, consistent with existing ADS pattern array substrate manufacturing process, do not need to make large improvement (only need increase step 203 and 205) to existing technique, the array base palte made can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoids the light leak that contraposition deviation causes.
Embodiment three
The embodiment of the present invention provides one to be applicable to the array base palte of HADS product (HADS pattern), and as shown in Figure 10, be with the difference part of array base palte described in embodiment one, this array base palte also comprises:
Second passivation layer 26, covers on black matrix 14 and pixel electrode 12;
Public electrode 20, to be positioned at above the second passivation layer 26 and to be arranged on the corresponding region of pixel electrode 12.
In addition, because of the employing of HADS pattern array substrate is multi-dimensional electric field, and therefore the public electrode 20 on upper strata is slit-shaped, as shown in figure 11.
ADS pattern array substrate in the present embodiment in the structure of HADS pattern array substrate and embodiment two is roughly similar, and difference is only to add the second passivation layer 26, and is arranged on the second passivation layer 26 by public electrode 20, no longer describes in detail at this.
Wherein, exemplarily, in described HADS pattern array substrate, the distribution range of color blocking layer 13 and black matrix 14 as shown in figure 11, arranges red/green/blue block (color blocking layer 13) in figure in solid line A institute region, arranges black matrix 14 in figure in two dotted line B institute regions.
A kind of HADS array base palte being provided with color blocking layer and black matrix is provided in the present embodiment, compared with existing HADS pattern array substrate, array base palte in the present embodiment, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoid the light leak that contraposition deviation causes.And, in the present embodiment array base palte grid line 18 above set up color blocking layer 13 (R/G/B layer), set up black matrix 14 above data line 17, color blocking layer 13, as the insulation course of grid line 18, can reduce the load of gate line, ensure pixel charging; Black matrix is as the insulation course of data line 17, and can reduce data-signal linear load and then reduce panel power consumption, this is even more important to high-resolution products.
Accordingly, the embodiment of the present invention also provides a kind of manufacture method of array base palte, and be applicable to HADS pattern array substrate, as shown in figure 12, the method comprises:
Step 301, form grid metal levels on the substrate 10, adopt patterning processes to form grid line 21 and grid (for ease of understanding, below describing and please refer to shown in Figure 10);
Step 302, making color blocking layer 13, form red/green/blue block in pixel electrode 12 corresponding region;
Step 303, routinely flow process form gate insulation layer 22, active layer 23, source-drain electrode layer and passivation layer 11;
Step 304, form black matrix layer, adopt the region of patterning processes beyond color blocking layer 13 corresponding region to form black matrix 14;
Step 305, form the first transparent conductive film layer, adopt patterning processes to form pixel electrode 12;
Step 306, form the second passivation layer 26;
Step 307, prepare the second transparent conductive film layer, adopt patterning processes to form public electrode 20.
On passivation layer 11 in the present embodiment and black matrix 14, all the drain same position of 25 correspondences of thin film transistor (TFT) is provided with via hole 15, pixel electrode 12 is connected to drain electrode 25 through this via hole 15.
Particularly, for the 6Mask technique that HADS pattern in prior art is conventional, the technical process of manufacturing method of array base plate described in the present embodiment is:
Form grid and grid line → formed successively R/B/G color blocking layer (needing three exposures) → formed gate insulation layer (without the need to exposure) → be formed with active layer → formation source, the black matrix B M of drain electrode layer → formation passivation layer → formed → formed the first transparent conductive film layer (pixel electrode) → form the second passivation layer (pixel insulation course) → the second transparent conductive film layer (public electrode), altogether need through 11 exposure technologys.
And for the 5Mask technique that HADS pattern in prior art is commonly used, the technical process of the manufacturing method of array base plate that the present embodiment proposes is:
Form grid and grid line → formed successively R/B/G color blocking layer (needing three exposures) → formed gate insulation layer (without the need to exposure) → formation source, the black matrix B M of drain electrode layer → formation passivation layer → formed → formed the first transparent conductive film layer (pixel electrode) → form the second passivation layer (pixel insulation course) → the second transparent conductive film layer (public electrode), altogether need through 10 exposure technologys.
Manufacturing method of array base plate provided by the invention, by the color blocking layer 13 of patterning is arranged on the substrate 10, black matrix 14 is arranged on passivation layer 11, and set up the second passivation layer 26, public electrode 20 is arranged on the second passivation layer 26, color film color blocking and black matrix are formed on HADS pattern array substrate, reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, avoid the light leak that contraposition deviation causes, passivation layer can also strengthen the adhesiveness between black matrix and array base palte simultaneously.
In addition, in like manner, color blocking layer as gate line insulation course, can reduce the load of gate line, and ensure pixel charging, this is even more important to high-resolution products; Black matrix as the insulation course of data line, can reduce data line load and then reduces panel power consumption.
The array base palte that the manufacturing method of array base plate that the embodiment of the present invention provides provides for the manufacture of above-described embodiment, is in fact not limited in the mode described in above the present embodiment, introduces no longer one by one herein.
Embodiment four
Embodiments provide a kind of display device, it comprises any one array base palte described in above-described embodiment.Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Described display device is provided with color film color blocking and black matrix because adopting on array base palte, therefore the impact for transmitance of array base palte and color membrane substrates contraposition deviation can be reduced, and red/green/primary colors color blocking layer is as grid line insulation course, the load of grid line can be reduced, significant for the charging of guarantee panel, black matrix is as data line insulation course, and can reduce data line load and then reduce panel power consumption, this requires significance for present product low-power consumption.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (10)
1. an array base palte, comprising: substrate, is arranged at the thin film transistor (TFT) on described substrate, pixel electrode, data line, grid line, and passivation layer, and described thin film transistor (TFT) comprises grid, gate insulation layer, active layer, source electrode and drain electrode; Described passivation layer covers described thin film transistor (TFT), and described pixel electrode is arranged on the top of described passivation layer, it is characterized in that, also comprises: the color blocking layer of patterning and black matrix;
Described color blocking layer is arranged between described substrate and described gate insulation layer, and is distributed in the corresponding region above described pixel electrode corresponding region and described grid line, and described grid line is arranged on the substrate;
Described black arranged in matrix on described passivation layer, and is positioned at the region beyond described color blocking layer corresponding region, and the region beyond described color blocking layer corresponding region comprises the corresponding region above described data line.
2. array base palte according to claim 1, is characterized in that, the described black matrix on described passivation layer and described passivation layer, the drain electrode correspondence position of described thin film transistor (TFT) is provided with via hole, and described pixel electrode is connected to described drain electrode through described via hole.
3. array base palte according to claim 1 and 2, is characterized in that, also comprises:
Public electrode, is arranged between described substrate and described gate insulation layer, and is arranged on the corresponding region of described pixel electrode.
4. array base palte according to claim 3, is characterized in that,
Described pixel electrode is slit-shaped.
5. array base palte according to claim 1 and 2, is characterized in that, also comprises:
Second passivation layer, covers on described black matrix and described pixel electrode;
Public electrode, to be positioned at above described second passivation layer and to be arranged on the corresponding region of described pixel electrode.
6. array base palte according to claim 5, is characterized in that,
Described public electrode is slit-shaped.
7. a display device, is characterized in that, comprises the array base palte described in any one of claim 1-6.
8. a manufacture method for array base palte, is characterized in that, comprising:
Substrate is formed grid metal level, adopts patterning processes to form grid line and grid;
Corresponding region above pixel electrode corresponding region, described grid line forms color blocking layer;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer, described source-drain electrode layer comprises data line, the source electrode of thin film transistor (TFT) and drain electrode;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix, the region beyond described color blocking layer corresponding region comprises the corresponding region above described data line;
Form transparent conductive film layer, adopt patterning processes to form pixel electrode.
9. a manufacture method for array base palte, is characterized in that, comprising:
Substrate is formed the first transparent conductive film layer, adopts patterning processes to form public electrode;
Form grid metal level, adopt patterning processes to form grid line and grid;
Corresponding region above pixel electrode corresponding region, described grid line forms color blocking layer;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer, described source-drain electrode layer comprises data line, the source electrode of thin film transistor (TFT) and drain electrode;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix, the region beyond described color blocking layer corresponding region comprises the corresponding region above described data line;
Form the second transparent conductive film layer, adopt patterning processes to form pixel electrode.
10. a manufacture method for array base palte, is characterized in that, comprising:
Form grid metal level, adopt patterning processes to form grid line and grid;
Corresponding region above pixel electrode corresponding region, described grid line forms color blocking layer;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer, described source-drain electrode layer comprises data line, the source electrode of thin film transistor (TFT) and drain electrode;
Form black matrix layer, adopt the region of patterning processes beyond described color blocking layer corresponding region to form black matrix, the region beyond described color blocking layer corresponding region comprises the corresponding region above described data line;
Form the first transparent conductive film layer, adopt patterning processes to form pixel electrode;
Form the second passivation layer;
Prepare the second transparent conductive film layer, adopt patterning processes to form public electrode.
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| CN103309081B (en) * | 2013-05-30 | 2016-12-28 | 京东方科技集团股份有限公司 | Array base palte and manufacture method, display device |
| CN104297995A (en) * | 2014-11-03 | 2015-01-21 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method of display substrate and display device |
| CN104965366B (en) * | 2015-07-15 | 2018-11-20 | 深圳市华星光电技术有限公司 | The production method and its structure of array coloured silk film integrated form liquid crystal display panel |
| WO2018090496A1 (en) * | 2016-11-17 | 2018-05-24 | 华为技术有限公司 | Array substrate and preparation method therefor, and liquid crystal display panel |
| CN107728374B (en) * | 2017-11-29 | 2021-01-29 | 深圳市华星光电半导体显示技术有限公司 | Color filter film substrate and preparation method thereof |
| CN109166895B (en) * | 2018-08-31 | 2021-01-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN111061105A (en) * | 2019-12-31 | 2020-04-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device thereof |
| CN111474784B (en) * | 2020-05-08 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and liquid crystal display panel |
| CN111580296B (en) * | 2020-06-17 | 2022-06-10 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111999946B (en) * | 2020-08-28 | 2022-07-01 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113820883A (en) * | 2021-09-29 | 2021-12-21 | Tcl华星光电技术有限公司 | Pixel unit of display panel and display panel |
| US11953795B2 (en) | 2021-09-29 | 2024-04-09 | Tcl China Star Optoelectronics Technology Co., Ltd. | Pixel unit of a display panel and display panel |
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| KR100820104B1 (en) * | 2001-07-25 | 2008-04-07 | 엘지.필립스 엘시디 주식회사 | liquid crystal display and manufacturing method of the same |
| KR101335276B1 (en) * | 2006-09-20 | 2013-11-29 | 삼성디스플레이 주식회사 | Array substrat, display panel having the same and fabricating of display panel |
| CN100559571C (en) * | 2008-07-22 | 2009-11-11 | 友达光电股份有限公司 | Production method of pixel structure |
| KR101542394B1 (en) * | 2008-10-28 | 2015-08-07 | 삼성디스플레이 주식회사 | Thin film transistor substrate and liquid crystal display including the same |
| CN202025170U (en) * | 2011-04-22 | 2011-11-02 | 京东方科技集团股份有限公司 | Display screen and display device |
| CN202855737U (en) * | 2012-11-12 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
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