CN102929058A - Array substrate, manufacturing method of array substrate, and display device - Google Patents
Array substrate, manufacturing method of array substrate, and display device Download PDFInfo
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- CN102929058A CN102929058A CN2012104526322A CN201210452632A CN102929058A CN 102929058 A CN102929058 A CN 102929058A CN 2012104526322 A CN2012104526322 A CN 2012104526322A CN 201210452632 A CN201210452632 A CN 201210452632A CN 102929058 A CN102929058 A CN 102929058A
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Abstract
The invention discloses an array substrate, a manufacturing method of the array substrate, and a display device, relating to the field of displays. The influence of alignment deviation of the array substrate and a color film substrate on transmittance can be reduced to avoid the light leakage caused by the alignment deviation, and the insulativity of a signal line can be also enhanced at the same time to reduce the power consumption of a panel. The array substrate comprises a substrate, a thin film transistor arranged on the substrate, a pixel electrode and a passivation layer, wherein the passivation layer covers the thin film transistor; and the pixel electrode is arranged above the passivation layer. The array substrate further comprises a patterned color resistance layer and a black matrix, wherein the color resistance layer is arranged between the substrate and a grid insulation layer and distributed in a region corresponding to the pixel electrode; and the black matrix is arranged on the passivation layer and positioned in a region outside the region corresponding to the color resistance layer. The method comprises the steps as follows: forming a grid line and a grid; manufacturing the color resistance layer; forming the grid insulation layer, an active layer, source and drain electrode layers and the passivation layer; forming the black matrix; and forming the pixel electrode.
Description
Technical field
The present invention relates to the demonstration field, relate in particular to a kind of array base palte and manufacture method thereof, display device.
Background technology
Liquid crystal display now has been widely used in each demonstration field, such as family, public place, office field and personal electric Related product etc.At present, liquid crystal display is simple from making, with low cost but twisted-nematic (Twisted Nematic that the visual angle is less, TN) type liquid crystal display, develop into multi-dimensional electric field (Advanced Super Dimension Switch, AD-SDS, be called for short ADS) the type liquid crystal display, and the HADS type liquid crystal display of the high aperture that proposes based on the ADS pattern, any liquid crystal display no matter, the manufacture craft of its liquid crystal panel all is independent manufacturing array (Array) substrate and color film (Color Filter) substrate, and then array base palte and color membrane substrates are carried out contraposition, become box (Cell).
The inventor finds: when array base palte becomes box with the color membrane substrates contraposition, because the restriction of aligning accuracy the contraposition deviation very easily occurs, and the contraposition deviation can cause light leak, transmitance reduction etc. bad; If will deceive enough wide these problems of avoiding that matrix is done, the transmitance that can lose again panel increases cost backlight.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of array base palte and manufacture method thereof, display device, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte comprises: substrate, be arranged at thin film transistor (TFT), pixel electrode on the described substrate, and passivation layer, described thin film transistor (TFT) comprises grid, gate insulation layer, semiconductor layer, source electrode and drain electrode; Described passivation layer covers described thin film transistor (TFT), and described pixel electrode is arranged on the top of described passivation layer, also comprises: the look resistance layer of patterning and black matrix;
Described look resistance layer is arranged between described substrate and the described gate insulation layer, and is distributed in described pixel electrode corresponding region;
Described black arranged in matrix and is positioned at zone beyond the described look resistance layer corresponding region on described passivation layer.
Particularly, the described black matrix on described passivation layer and the described passivation layer is provided with via hole at the drain electrode correspondence position of described thin film transistor (TFT), and described pixel electrode is connected to described drain electrode through described via hole.
Alternatively, described array base palte also comprises:
Public electrode is arranged between described substrate and the described gate insulation layer, and is arranged on described pixel electrode corresponding region.
Alternatively, described pixel electrode is slit-shaped.
Alternatively, described array base palte also comprises:
The second passivation layer covers on described black matrix and the described pixel electrode;
Public electrode is positioned at described the second passivation layer top and is arranged on the corresponding region of described pixel electrode.
Described public electrode is slit-shaped.
The present invention also provides a kind of display device, comprises above-mentioned arbitrary array base palte.
On the other hand, the present invention also provides a kind of manufacture method of array base palte, comprising:
Form the grid metal level at substrate, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form transparent conductive film layer, adopt composition technique to form pixel electrode.
The manufacture method of the second array base palte provided by the invention comprises:
Form the first transparent conductive film layer at substrate, adopt composition technique to form public electrode;
Form the grid metal level, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form the second transparent conductive film layer, adopt composition technique to form pixel electrode.
The manufacture method of the third array base palte provided by the invention comprises:
Form the grid metal level, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form the first transparent conductive film layer, adopt composition technique to form pixel electrode;
Form the second passivation layer;
Prepare the second transparent conductive film layer, adopt composition technique to form public electrode.
Array base palte provided by the invention and manufacture method thereof, display device, relate to a kind of array base palte that is provided with color film look resistance and deceives matrix, and a kind of with the resistance of color film look with deceive matrix and be formed on method on the array base palte, this technical scheme is arranged on the substrate by the look resistance layer with patterning, black arranged in matrix is on passivation layer, array base palte and color membrane substrates contraposition deviation have been reduced to the impact of transmitance, the light leak that can avoid the contraposition deviation to cause, passivation layer can also strengthen the adhesiveness between black matrix and the array base palte simultaneously.
In addition, the look resistance layer can be used as signal line (gate line) insulation course, reduces the load of gate line, guarantees the pixel charging; Black matrix can be used as the insulation course of data signal line (data line), reduces the data line load and then reduces the panel power consumption, and this is even more important to high-resolution products.
Description of drawings
The section structure synoptic diagram of the array base palte that Fig. 1 provides for the embodiment of the invention one;
Fig. 2 is the planar structure synoptic diagram one of array base palte in the embodiment of the invention one;
Fig. 3 is the planar structure synoptic diagram two of array base palte in the embodiment of the invention one;
Fig. 4 is near the cross section structure synoptic diagram of array base palte grid line in the embodiment of the invention one;
Fig. 5 is near the cross section structure synoptic diagram of array base palte data line in the embodiment of the invention one;
Fig. 6 is the process flow diagram of manufacturing method of array base plate in the embodiment of the invention one;
The structural representation of the array base palte that Fig. 7 provides for the embodiment of the invention two;
Fig. 8 is the planar structure synoptic diagram of array base palte in the embodiment of the invention two;
Fig. 9 is the manufacture method process flow diagram of array base palte in the embodiment of the invention two;
The structural representation of the array base palte that Figure 10 provides for the embodiment of the invention three;
Figure 11 is the planar structure synoptic diagram of array base palte in the embodiment of the invention three;
Figure 12 is the manufacture method process flow diagram of array base palte in the embodiment of the invention three.
Description of reference numerals
The 10-substrate, the 11-passivation layer, the 12-pixel electrode, 13-look resistance layer, 14-deceives matrix,
The 15-via hole, the 16-thin film transistor (TFT), the 17-data line, the 18-grid line, the 19-public electrode wire,
The 20-public electrode, the 21-grid, the 22-gate insulation layer, the 23-active layer, the 24-source electrode,
The 25-drain electrode, 26-the second passivation layer.
Embodiment
The embodiment of the invention provides a kind of array base palte and manufacture method thereof, display device, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause also can strengthen the signal wire insulativity simultaneously, reduces the panel power consumption.
The embodiment of the invention provides a kind of array base palte, this array base palte comprises: substrate, be arranged at the thin film transistor (TFT) on the substrate, pixel electrode, and passivation layer, described thin film transistor (TFT) comprises grid, gate insulation layer, active layer, source electrode and drain electrode, passivation layer cover film transistor, pixel electrode is arranged on the top of passivation layer, also comprises: the look resistance layer of patterning and black matrix;
Described look resistance layer is arranged between substrate and the gate insulation layer, and is distributed in the pixel electrode corresponding region; Described black arranged in matrix and is positioned at zone beyond the look resistance layer corresponding region on passivation layer.
The described look resistance layer of present embodiment refer to cover the pixel electrode corresponding region red/the color film of green/primary colors, in the present embodiment with look resistance layer and black arranged in matrix on array base palte, wherein, the look resistance layer is positioned on the substrate of array base palte, black arranged in matrix is on passivation layer, and be positioned at zone in addition, look resistance layer corresponding region (pixel electrode), can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause, passivation layer can also strengthen the adhesiveness between black matrix and the array base palte simultaneously.In addition, look resistance layer and black Matrix cover also can be used as the insulation course of signal wire on signal wire (for example grid line or data line), can reduce load of signal line, and then reduce the panel power consumption.
Below in conjunction with accompanying drawing the embodiment of the invention is described in detail.Embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Embodiment one
As shown in Figure 1, the embodiment of the invention provides the array base palte of a kind of TN of being applicable to product (TN pattern), this array base palte comprises: substrate 10, be arranged at substrate 10 upper film transistors, pixel electrode 12, and passivation layer 11, described thin film transistor (TFT) comprises grid (Gate) 21, gate insulation layer (GI) 22, active layer (Active) 23, source electrode (Source) 24 and drain electrode 25 (Drain); Passivation layer 11 cover film transistors, pixel electrode arrange 12 tops that are arranged on passivation layer 11, in addition, also comprise: the look resistance layer 13 of patterning and black matrix 14;
Wherein, described look resistance layer 13 is arranged between substrate 10 and the gate insulation layer 22, and is distributed in pixel electrode 12 corresponding regions; Described black matrix 14 is arranged on the passivation layer 11, and is positioned at the zone beyond look resistance layer 13 corresponding regions.
The present embodiment gate insulation layer directly is provided with on the substrate of pixel electrode 12 corresponding regions red/green/blue piece (look resistance layer 13), be coated with gate insulation layer 22 on the look resistance layer 13, cover passivation layer 11 on the gate insulation layer 22, pixel electrode 12 is arranged on the top of look resistance layer 13 across gate insulation layer (GI) 22 and passivation layer 11.
The described look resistance layer 13 of present embodiment, be laid on pixel electrode 12 corresponding regions red/green/blue (R/G/B) color lump, claim again color film look resistance layer; Black matrix 14 is arranged on the passivation layer 11, and is distributed in the zone outside red/green/blue piece corresponding region.Particularly: red/green/blue piece (look resistance layer 13) covers the corresponding region of pixel electrode 12, such as the zone of solid line A encirclement among Fig. 2; Black matrix 14 is arranged on the zone outside red/green/blue piece (look resistance layer 13), such as two zones that dotted line B surrounds among Fig. 3.In the implementation, for preventing light leak, the coverage of red/green/blue piece generally exceeds the corresponding region of pixel electrode 12 a little, has the overlapping region with the joint of black matrix 14 overlay areas.
The array base palte that the embodiment of the invention provides, the look resistance layer is set directly on the substrate, easily obtains smooth, thickness is consistent red/green/blue piece during making, with to make the look resistance layer at the substrate of color membrane substrates in the prior art consistent, need not to overcome technical barrier; In addition, black arranged in matrix is on passivation layer, and because of the adhesive attraction of passivation layer, black matrix can be bonded on the array base palte more firmly.Therefore, the array base palte of present embodiment can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance because coloured resistance layer and black matrix are set, the light leak of avoiding the contraposition deviation to cause, thereby transmitance and the display effect of raising display device.
In addition, as shown in Figure 4, be near the schematic cross-section of TN pattern array substrate grid line 18 in the present embodiment.As we know from the figure, compare with the structure of existing TN pattern array substrate, grid line 18 tops increase resistance layer 13 of the same colour (R/G/B layer), and look resistance layer 18 specific inductive capacity are less, thickness is thicker, thereby so that grid line 18 and directly over electric capacity between public electrode 20 (being positioned on the color membrane substrates) significantly reduce, reduce load on the grid line 18 thereby reach, guarantee the purpose of pixel charging, this is particularly important for high-resolution products.
Also have, as shown in Figure 5, be near the schematic cross-section of TN pattern array substrate data line 17 in the present embodiment.As we know from the figure, compare with the structure of existing TN pattern array substrate, above data line 17, increased the black matrix 14 of one deck, and specific inductive capacity is little, thickness is large because of 14 layers in black matrix, thereby make data line 17 and directly over coupling capacitance between the public electrode 20, and the coupling capacitance between data line 17 and pixel electrode (not shown) significantly reduces, thereby the load on the data line 17 is reduced, and then the panel power-dissipation-reduced.
Wherein, the black matrix 14 on passivation layer 11 and the passivation layer 11 is provided with via hole 15 at drain electrode 25 correspondence positions of thin film transistor (TFT), and pixel electrode 12 is connected to drain electrode 25 through via hole 15, as shown in fig. 1.
Coloured resistance layer and black matrix are set on the array base palte described in the present embodiment, therefore array base palte and color membrane substrates contraposition deviation are minimized the impact of transmitance, the light leak that simultaneously also can avoid the contraposition deviation to cause, and passivation layer can also strengthen the adhesiveness between black matrix and the array base palte.In addition, look resistance layer and black matrix also can be used as the insulation course of signal wire, reduce load of signal line, and then reduce the panel power consumption.
The embodiment of the invention also provides a kind of manufacture method of array base palte of the TN of being applicable to product, and as shown in Figure 6, the method comprises:
Form the grid metal level at substrate in this step, adopt composition technique to form grid line and grid, it is consistent with prior art specifically to form method, does not repeat them here.
This step forms the look resistance layer at the substrate of pixel electrode corresponding region, namely applies red/green/blue piece, and it is consistent with prior art specifically to form method.
At the black matrix of passivation layer preparation, utilize the adhesive attraction of passivation layer in this step, will deceive matrix and be fixed on the array base palte more firmly.
Wherein, adopt the zone of composition technique beyond in look resistance layer 13 corresponding regions to form black matrix 14 in the step 104, be specially:
Adopt the zone of composition technique beyond in look resistance layer 13 corresponding regions to form black matrix 14, and at drain electrode 25 correspondence positions of thin film transistor (TFT) via hole 15 is set, pixel electrode 12 is connected to drain electrode 25 through this via hole 15.
Particularly, for the 5Mask technique commonly used of TN pattern in the prior art, the manufacturing method of array base plate technical process that present embodiment proposes is:
Formation grid and grid line → form successively R/B/G look resistance layer (three exposures) → formation gate insulation layer (not needing exposure technology) → formation active layer → formation source, the black matrix layer (BM) of drain electrode layer → formation pixel insulation course (passivation layer) → formation → formation transparent conductive film layer (pixel electrode), altogether need be through 9 exposure technologys.
In addition, for the 4Mask technique commonly used of TN pattern in the prior art, the manufacturing method of array base plate technical process that present embodiment proposes is:
Formation grid and grid line → form successively R/B/G look resistance layer (three exposures) → formation gate insulation layer (not needing exposure technology) → formation source, the black matrix layer (BM) of drain electrode layer → formation pixel insulation course (passivation layer) → formation → formation transparent conductive film layer (pixel electrode), altogether need be through 8 exposure technologys.Wherein, active layer and source, drain electrode and grid line, by single exposure, multiple etching forms.
The manufacture method of the described array base palte of present embodiment, with look resistance layer and black arranged in matrix on array base palte, can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause, passivation layer can also strengthen the adhesiveness between black matrix and the array base palte simultaneously.In addition, look resistance layer and black matrix also can be used as the insulation course of signal wire, can reduce load of signal line, and then reduce the panel power consumption.
Embodiment two
The embodiment of the invention provides the array base palte of a kind of ADS of being applicable to product (ADS pattern), as shown in Figure 7, the difference part of this array base palte and embodiment one described array base palte is, also comprises: public electrode 20 is arranged between substrate 10 and the look resistance layer 13; In addition, because ADS pattern array substrate adopts multi-dimensional electric field, so the pixel electrode in the present embodiment 12 is slit-shaped, as shown in Figure 8.
Need to prove: pixel electrode can be tabular or slit-shaped, and public electrode also is so, and the up and down order of pixel electrode and public electrode can be put upside down, but must be slit-shaped at upper electrode, under electrode be tabular.
Particularly, this array base palte comprises: substrate 10 is arranged at the thin film transistor (TFT) 16 on the substrate 10, thin film transistor (TFT) 16 comprises: grid (Gate) 21, gate insulation layer (GI) 22, active layer (Active) 23, source electrode (Source) 24 and drain electrode 25 (Drain); Public electrode 20, the look resistance layer 13 of patterning, passivation layer 11, pixel electrode 12.Wherein, passivation layer 11 covers in source electrode 24 and the drain electrode 25, and pixel electrode 12 is arranged on the passivation layer 11; Look resistance layer 13 is arranged on pixel electrode 12 corresponding regions, is positioned on the public electrode 20; Black matrix 14 is arranged on the passivation layer 11, and is positioned at the zone beyond look resistance layer 13 corresponding regions; Passivation layer 11 and black matrix 14 are provided with via hole 15 at drain electrode 25 correspondence positions, and pixel electrode 12 is connected to drain electrode 25 by this via hole 15.
Wherein, exemplarily, the distributed areas of look resistance layer 13 and black matrix 14 arrange red/green/blue piece (look resistance layer 13) as shown in Figure 8 in the described ADS pattern array substrate in the solid line A institute region among the figure, in two dotted line B institute regions black matrix 14 are set among the figure.
A kind of ADS array base palte that coloured resistance layer and black matrix are set is provided in the present embodiment, compare with existing ADS pattern array substrate, array base palte in the present embodiment can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause.
And, to compare with the structure of existing ADS pattern array substrate, grid line 18 tops increase resistance layer 13 of the same colour (R/G/B layer), data line 17 tops increase the black matrix 14 of one deck, look resistance layer 13 can reduce the load of gate line as the insulation course of grid line 18, guarantees the pixel charging; Black matrix can reduce the data-signal linear load and then reduce the panel power consumption as the insulation course of data line 17, and this is even more important to high-resolution products.
In addition, public electrode 20 in the present embodiment can be arranged between look resistance layer 13 and the gate insulation layer 22, therefore public electrode 20 also can be arranged on the look resistance layer 13, and be positioned at the below of gate insulation layer 22, that is: the setting position of look resistance layer 13 and public electrode 20 can be changed up and down, and look resistance layer 13 can be set directly on the substrate, and public electrode 20 is set on look resistance layer 13 again, do not affect the implementation effect of present embodiment, so present embodiment is not done restriction to this.
Accordingly, the embodiment of the invention also provides a kind of manufacture method of array base palte, is applicable to ADS pattern array substrate, and as shown in Figure 9, the method comprises:
When step 204 forms passivation layer 11 in the present embodiment and step 205 when forming black matrix 14, all at the drain same position of 25 correspondences of thin film transistor (TFT) via hole 15 is set, is used for pixel electrode 12 and is connected to through this via hole 15 and drains 25.
Particularly, for the 1+5Mask technique commonly used of ADS pattern in the prior art, the technical process of the described manufacturing method of array base plate of present embodiment is:
Form the first transparent conductive film layer (public electrode Com) → formation grid and grid line → form successively R/B/G look resistance layer (three exposures) → form gate insulation layer (not needing exposure technology) → formations active layer → formation source, matrix (BM) → formation the second transparent conductive film layer (pixel electrode) is deceived in drain electrode layer → formations pixel insulation course (passivation layer) → formations, being total to need be through 10 exposure technology.
And for the 1+4Mask technique commonly used of ADS pattern in the prior art, the manufacturing method of array base plate technical process that present embodiment proposes is:
Form the first transparent conductive film layer (public electrode Com) → formation grid and grid line → form successively R/B/G look resistance layer (three exposures) → form gate insulation layer (not needing exposure technology) → formation source, the black matrix (BM) of drain electrode layer → formations pixel insulation course (passivation layer) → formations → formation the second transparent conductive film layer (pixel electrode), being total to need be through 9 exposure technology.
Wherein, above-mentioned formation public electrode can be changed with the exposure order that forms grid.
A kind of ADS array base palte and manufacture method thereof that coloured resistance layer and black matrix are set is provided in the present embodiment, consistent with existing ADS pattern array substrate manufacturing process, do not need existing technique is made large improvement (only needing to increase step 203 and 205), the array base palte of making can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause.
Embodiment three
The embodiment of the invention provides the array base palte of a kind of HADS of being applicable to product (HADS pattern), as shown in figure 10, is that with the difference part of embodiment one described array base palte this array base palte also comprises:
The second passivation layer 26 covers on black matrix 14 and the pixel electrode 12;
In addition, what adopt because of HADS pattern array substrate is multi-dimensional electric field, so the public electrode 20 on upper strata is slit-shaped, as shown in figure 11.
The structure of HADS pattern array substrate and the ADS pattern array substrate among the embodiment two are roughly similar in the present embodiment, and difference only is to have increased the second passivation layer 26, and public electrode 20 is arranged on the second passivation layer 26, no longer is described in detail at this.
Wherein, exemplarily, the distribution range of look resistance layer 13 and black matrix 14 arranges red/green/blue piece (look resistance layer 13) as shown in figure 11 in the described HADS pattern array substrate in the solid line A institute region among the figure, in two dotted line B institute regions black matrix 14 is set among the figure.
A kind of HADS array base palte that coloured resistance layer and black matrix are set is provided in the present embodiment, compare with existing HADS pattern array substrate, array base palte in the present embodiment can reduce array base palte and color membrane substrates contraposition deviation to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause.And look resistance layer 13 (R/G/B layer) is set up in grid line 18 tops of array base palte in the present embodiment, and black matrix 14 is set up in data line 17 tops, and look resistance layer 13 can reduce the load of gate line as the insulation course of grid line 18, guarantees the pixel charging; Black matrix can reduce the data-signal linear load and then reduce the panel power consumption as the insulation course of data line 17, and this is even more important to high-resolution products.
Accordingly, the embodiment of the invention also provides a kind of manufacture method of array base palte, is applicable to HADS pattern array substrate, and as shown in figure 12, the method comprises:
On the passivation layer 11 and black matrix 14 in the present embodiment, all be provided with via hole 15 at the drain same position of 25 correspondences of thin film transistor (TFT), pixel electrode 12 is connected to drain electrode 25 through this via hole 15.
Particularly, for the 6Mask technique commonly used of HADS pattern in the prior art, the technical process of the described manufacturing method of array base plate of present embodiment is:
Formation grid and grid line → form successively R/B/G look resistance layer (needing three exposures) → formation gate insulation layer (need not exposure) → formation active layer → formation source, the black matrix B M of drain electrode layer → formation passivation layer → formation → formation the first transparent conductive film layer (pixel electrode) → formation the second passivation layer (pixel insulation course) → the second transparent conductive film layer (public electrode), altogether need be through 11 exposure technologys.
And for the 5Mask technique commonly used of HADS pattern in the prior art, the technical process of the manufacturing method of array base plate that present embodiment proposes is:
Form grid and grid line → form successively R/B/G look resistance layer (needing three exposures) → form gate insulation layer (need not exposure) → formation source, the black matrix B M of drain electrode layer → formations passivation layer → formations → formation the first transparent conductive film layer (pixel electrode) → formation the second passivation layer (pixel insulation course) → the second transparent conductive film layer (public electrode), being total to need be through 10 exposure technology.
Manufacturing method of array base plate provided by the invention, be arranged on the substrate 10 by the look resistance layer 13 with patterning, black matrix 14 is arranged on the passivation layer 11, and set up the second passivation layer 26, public electrode 20 is arranged on the second passivation layer 26, with the resistance of color film look with deceive matrix and be formed on the HADS pattern array substrate, array base palte and color membrane substrates contraposition deviation have been reduced to the impact of transmitance, the light leak of avoiding the contraposition deviation to cause, passivation layer can also strengthen the adhesiveness between black matrix and the array base palte simultaneously.
In addition, in like manner, the look resistance layer can be used as the gate line insulation course, reduces the load of gate line, guarantees the pixel charging, and this is even more important to high-resolution products; Black matrix can be used as the insulation course of data line, reduces the data line load and then reduces the panel power consumption.
In fact the array base palte that the manufacturing method of array base plate that the embodiment of the invention provides provides for the manufacture of above-described embodiment is not limited in the described mode of above present embodiment, introduces no longer one by one herein.
Embodiment four
The embodiment of the invention provides a kind of display device, and it comprises described any one array base palte of above-described embodiment.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Described display device is provided with color film look resistance and deceives matrix because adopting on the array base palte, therefore can reduce array base palte and color membrane substrates contraposition deviation for the impact of transmitance, and red/green/primary colors look resistance layer is as the grid line insulation course, can reduce the load of grid line, for guaranteeing that the panel charging is significant, black matrix can reduce the data line load and then reduce the panel power consumption as the data line insulation course, this for present product low-power consumption require significant.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection domain with claim.
Claims (10)
1. array base palte comprises: substrate, be arranged at the thin film transistor (TFT) on the described substrate, and pixel electrode, and passivation layer, described thin film transistor (TFT) comprises grid, gate insulation layer, active layer, source electrode and drain electrode; Described passivation layer covers described thin film transistor (TFT), and described pixel electrode is arranged on the top of described passivation layer, it is characterized in that, also comprises: the look resistance layer of patterning and black matrix;
Described look resistance layer is arranged between described substrate and the gate insulation layer, and is distributed in described pixel electrode corresponding region;
Described black arranged in matrix and is positioned at zone beyond the described look resistance layer corresponding region on described passivation layer.
2. array base palte according to claim 1 is characterized in that, the described black matrix on described passivation layer and the described passivation layer is provided with via hole at the drain electrode correspondence position of described thin film transistor (TFT), and described pixel electrode is connected to described drain electrode through described via hole.
3. array base palte according to claim 1 and 2 is characterized in that, also comprises:
Public electrode is arranged between described substrate and the described gate insulation layer, and is arranged on the corresponding region of described pixel electrode.
4. array base palte according to claim 3 is characterized in that,
Described pixel electrode is slit-shaped.
5. array base palte according to claim 1 and 2 is characterized in that, also comprises:
The second passivation layer covers on described black matrix and the described pixel electrode;
Public electrode is positioned at described the second passivation layer top and is arranged on the corresponding region of described pixel electrode.
6. array base palte according to claim 5 is characterized in that,
Described public electrode is slit-shaped.
7. a display device is characterized in that, comprises each described array base palte of claim 1-6.
8. the manufacture method of an array base palte is characterized in that, comprising:
Form the grid metal level at substrate, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form transparent conductive film layer, adopt composition technique to form pixel electrode.
9. the manufacture method of an array base palte is characterized in that, comprising:
Form the first transparent conductive film layer at substrate, adopt composition technique to form public electrode;
Form the grid metal level, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form the second transparent conductive film layer, adopt composition technique to form pixel electrode.
10. the manufacture method of an array base palte is characterized in that, comprising:
Form the grid metal level, adopt composition technique to form grid line and grid;
Form the look resistance layer in described pixel electrode corresponding region;
Form gate insulation layer, active layer, source-drain electrode layer and passivation layer;
Form black matrix layer, adopt the zone of composition technique beyond in described look resistance layer corresponding region to form black matrix;
Form the first transparent conductive film layer, adopt composition technique to form pixel electrode;
Form the second passivation layer;
Prepare the second transparent conductive film layer, adopt composition technique to form public electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210452632.2A CN102929058B (en) | 2012-11-12 | 2012-11-12 | Array substrate, manufacturing method of array substrate, and display device |
Applications Claiming Priority (1)
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| CN201210452632.2A CN102929058B (en) | 2012-11-12 | 2012-11-12 | Array substrate, manufacturing method of array substrate, and display device |
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| CN102929058A true CN102929058A (en) | 2013-02-13 |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014190727A1 (en) * | 2013-05-30 | 2014-12-04 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN104297995A (en) * | 2014-11-03 | 2015-01-21 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method of display substrate and display device |
| WO2017008370A1 (en) * | 2015-07-15 | 2017-01-19 | 深圳市华星光电技术有限公司 | Manufacturing method of manufacturing array and color filter integrated-type liquid crystal display and structure of array and color filter integrated-type liquid crystal display |
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| CN111580296A (en) * | 2020-06-17 | 2020-08-25 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
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| US11953795B2 (en) | 2021-09-29 | 2024-04-09 | Tcl China Star Optoelectronics Technology Co., Ltd. | Pixel unit of a display panel and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030020852A1 (en) * | 2001-07-25 | 2003-01-30 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
| US20080068537A1 (en) * | 2006-09-20 | 2008-03-20 | Samsung Electronics Co., Ltd. | Array substrate, display panel having the same and method of manufacturing the same |
| CN101330060A (en) * | 2008-07-22 | 2008-12-24 | 友达光电股份有限公司 | Method for preparing pixel structure |
| CN202025170U (en) * | 2011-04-22 | 2011-11-02 | 京东方科技集团股份有限公司 | Display screen and display device |
| US8253891B2 (en) * | 2008-10-28 | 2012-08-28 | Samsung Electronics Co., Ltd. | Thin film transistor substrate and liquid crystal display including the same |
| CN202855737U (en) * | 2012-11-12 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
-
2012
- 2012-11-12 CN CN201210452632.2A patent/CN102929058B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030020852A1 (en) * | 2001-07-25 | 2003-01-30 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
| US20080068537A1 (en) * | 2006-09-20 | 2008-03-20 | Samsung Electronics Co., Ltd. | Array substrate, display panel having the same and method of manufacturing the same |
| CN101330060A (en) * | 2008-07-22 | 2008-12-24 | 友达光电股份有限公司 | Method for preparing pixel structure |
| US8253891B2 (en) * | 2008-10-28 | 2012-08-28 | Samsung Electronics Co., Ltd. | Thin film transistor substrate and liquid crystal display including the same |
| CN202025170U (en) * | 2011-04-22 | 2011-11-02 | 京东方科技集团股份有限公司 | Display screen and display device |
| CN202855737U (en) * | 2012-11-12 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9874795B2 (en) | 2013-05-30 | 2018-01-23 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method, and display device thereof |
| WO2014190727A1 (en) * | 2013-05-30 | 2014-12-04 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN104297995A (en) * | 2014-11-03 | 2015-01-21 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method of display substrate and display device |
| WO2017008370A1 (en) * | 2015-07-15 | 2017-01-19 | 深圳市华星光电技术有限公司 | Manufacturing method of manufacturing array and color filter integrated-type liquid crystal display and structure of array and color filter integrated-type liquid crystal display |
| WO2018090496A1 (en) * | 2016-11-17 | 2018-05-24 | 华为技术有限公司 | Array substrate and preparation method therefor, and liquid crystal display panel |
| CN107728374B (en) * | 2017-11-29 | 2021-01-29 | 深圳市华星光电半导体显示技术有限公司 | Color filter film substrate and preparation method thereof |
| CN107728374A (en) * | 2017-11-29 | 2018-02-23 | 深圳市华星光电半导体显示技术有限公司 | A kind of colorized optical filtering ilm substrate and preparation method thereof |
| CN109166895A (en) * | 2018-08-31 | 2019-01-08 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN111061105A (en) * | 2019-12-31 | 2020-04-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device thereof |
| CN111474784A (en) * | 2020-05-08 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and liquid crystal display panel |
| CN111474784B (en) * | 2020-05-08 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and liquid crystal display panel |
| CN111580296A (en) * | 2020-06-17 | 2020-08-25 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111580296B (en) * | 2020-06-17 | 2022-06-10 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111999946A (en) * | 2020-08-28 | 2020-11-27 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111999946B (en) * | 2020-08-28 | 2022-07-01 | 厦门天马微电子有限公司 | Display panel and display device |
| WO2023050515A1 (en) * | 2021-09-29 | 2023-04-06 | Tcl华星光电技术有限公司 | Pixel unit of display panel, and display panel |
| US11953795B2 (en) | 2021-09-29 | 2024-04-09 | Tcl China Star Optoelectronics Technology Co., Ltd. | Pixel unit of a display panel and display panel |
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