CN205787506U - Array base palte and liquid crystal indicator - Google Patents
Array base palte and liquid crystal indicator Download PDFInfo
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- CN205787506U CN205787506U CN201620618611.7U CN201620618611U CN205787506U CN 205787506 U CN205787506 U CN 205787506U CN 201620618611 U CN201620618611 U CN 201620618611U CN 205787506 U CN205787506 U CN 205787506U
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Abstract
This utility model provides a kind of array base palte and liquid crystal indicator, relates to Display Technique field.Array base palte, including: a substrate, there is the plural data line in cross arranged crosswise and plural number bar scan line；Active member, is arranged on the cross intersection region of this plural number data line and this plural number bar scan line；Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region, and is electrically connected with this active member by a contact hole；Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode extend to the region of each this pixel electrode unit in be formed with the open area of a plurality of repeated arrangement.This utility model also discloses the liquid crystal indicator including this array base palte simultaneously.
Description
Technical field
This utility model relates to Display Technique field, particularly to a kind of array base palte and liquid crystal indicator.
Background technology
The liquid crystal indicator of general vertical electric field includes TN (Twisted Nematic, twisted nematic), VA
Liquid crystal display mode such as (Vertical Alignment, vertical orientations).Mostly TN panel in the market is the TN+ of modified form
Film, film i.e. compensate film, and for making up the deficiency of TN panel visible angle, the visible angle of the TN panel of improvement all reaches at present
To 160 °.VA class panel is the panel type that the application of present advanced liquid crystal is more, belongs to wide viewing angle panel.VA class panel is divided into again
MVA (Multi-domain Vertical Alignment, many quadrants vertical orientation technology) panel, PVA (Patterned
Vertical Alignment) panel, PSVA (Polymer Stabilization Vertical Alignment, polymer
Stablize vertical orientation) panel, UV2A (UV Vertical Alignment, UV light vertical orientation) panel, etc..
The dot structure of liquid crystal display mode is divided into dot structure and the dot structure of counter substrate side of array base palte side
Two parts.The dot structure of array base palte side mainly realizes the electrical functions of Thin Film Transistor-LCD (TFT-LCD), is
Determine that pixel capacitance effect, orientation postpone effect, gray scale voltage write diagnostics and the main aspect of retention performance.Counter substrate side
Dot structure mainly realize the optical function of TFT-LCD, be to determine TFT-LCD contrast and the main aspect in colourity territory.
Fig. 1 show the dot structure of array base palte side, and general employing storage electric capacity such as is produced on (Cs on public electrode
On COM) structure.The feature of Cs on COM structure is that pixel electrode 107 covers at this pixel public electrode wire 109 (COM
Line) on storage electric capacity is set.The position of public electrode wire can be in the both sides up and down of pixel, it is also possible in the central authorities of pixel.Public
The structure of data wire 103 both sides of extending to common-battery polar curve plays the effect of shading.Pixel electrode 107 and public electrode wire 109 weight
Folded region is exactly the storage capacity area of pixel.
The pixel of counter substrate side generally comprises the structures such as black matrix" BM, RGB color resistance, spacer, public electrode.Opposed
The structure of substrate-side pixel is mainly made up of optical filtering and shading two parts: filtering structure is made up of RGB color layer 204, light-shielding structure
It is made up of black matrix" 202.The main shading size considering black matrix" 202 of design of counter substrate side dot structure, and
RGB color layer 204 and the lap of black matrix" light shield layer.Array base palte side dot structure shown in corresponding diagram 1, can be designed that
Counter substrate side black matrix" light-shielding structure as shown in Figure 2 A.In actual counter substrate side dot structure, black matrix" bag
The white opening portion enclosed is covered with RGB color layer 204.The design of black matrix" light-shielding structure, it is therefore an objective to shown in Fig. 2 B to be ensured
Laminating effect, prevent counter substrate substrate and array base palte laminating skew after light leakage phenomena occurs.As shown in Figure 2 C, if right
The Anawgy accuracy putting substrate and array base palte is 6um, then the shading line segment of public electrode wire near data wire side limit with
The black matrix" 202 distance between the limit of chromatograph 204 side at least to ensure at more than 6um.
Existing dot structure, there are the following problems:
(1) metal wire is many, and metallic area is big, obvious to the reflex of ambient light.
(2) the black matrix" area between neighbor is relatively big, affects the aperture opening ratio of pixel, and the light reducing pixel utilizes
Efficiency.
Utility model content
In view of this, technical problem to be solved in the utility model is to provide that a kind of metal wire is few, have high printing opacity
The array base palte of rate and liquid crystal indicator.
In order to reach above-mentioned or other purpose, on the one hand this utility model proposes the array base of a kind of liquid crystal indicator
Plate, including: a substrate, there is the plural data line in cross arranged crosswise and plural number bar scan line；Active member, is arranged
Cross intersection region at this plural number data line Yu this plural number bar scan line；Pixel electrode, with each this cross intersection
It is provided with the pixel electrode unit of a plurality of repeated arrangement centered by region, and is electrically connected with this active member by a contact hole
Connect；Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode has the district extending to each this pixel electrode unit
The open area of a plurality of repeated arrangement it is provided with in territory.
Further, being provided with spacing distance between the pixel electrode unit of these a plurality of repeated arrangement, this transparency electrode is prolonged
It is arranged on the overlay region on the direction vertical with this array base palte in extending each neighboring area of each this pixel electrode unit
Territory, the overlapping region between this transparency electrode and this pixel electrode unit forms storage capacitor.
Further, this transparency electrode is distributed in the top of this pixel electrode layer, or is distributed in this pixel electrode and is somebody's turn to do
Between data wire metal layer, or it is distributed between this data wire metal layer and this scan line metal level, or is distributed in this and sweeps
Retouch below line metal level.
Further, the open area in this transparency electrode extends to each neighboring area of each this pixel electrode unit
Border be irregular saw-tooth like pattern.
Further, this transparency electrode material use tin dope three Indium sesquioxide., aluminium-doped zinc oxide, nano-silver thread or
Person's Graphene.
In order to reach above-mentioned or other purpose, on the other hand this utility model proposes a kind of array base palte, including: provide
One substrate, arranges first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line；At this first gold medal
Belong to and on the pattern of layer, gate insulator is set, be provided above semiconductor pattern at this gate insulator；At this semiconductor pattern
On, second layer metal Thinfilm pattern is set, this second layer metal Thinfilm pattern includes plural number data line, this plural number data line
It is cross arranged crosswise with this plural number bar scan line；Also include the source electrode of thin film transistor (TFT), drain electrode；Thin at this second layer metal
Being distributed insulating thick film layer on film figure, on this insulating thick film layer, whole EDS maps has pixel electrode, and this pixel electrode is with each
Centered by cross intersection region between this plural number data line and this plural number bar scan line, a plurality of repeated arrangement is set
Pixel electrode unit, this pixel electrode unit is electrically connected with drain electrode realization by running through a contact hole of this insulating thick film layer；
Being distributed isolated insulation layer on this pixel electrode, on this isolated insulation layer, whole EDS maps has transparency electrode；Wherein, this transparent electrical
Pole is provided with plurality of openings region in extending to the region of each this pixel electrode unit, this transparency electrode and this pixel electrode
There is overlapping region on the direction vertical with this array base palte, this overlapping region forms storage capacitor.
In order to reach above-mentioned or other purpose, the another aspect of this utility model proposes a kind of array base palte, including: provide
One substrate, arranges first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line；At this first gold medal
Belong to and on the pattern of layer, gate insulator is set, be provided above semiconductor pattern at this gate insulator；At this semiconductor pattern
On, second layer metal Thinfilm pattern is set, this second layer metal Thinfilm pattern includes plural number data line, this plural number data line
It is cross arranged crosswise with this plural number bar scan line；Also include the source electrode of thin film transistor (TFT), drain electrode；Thin at this second layer metal
Being distributed insulating barrier on film figure, the most whole EDS maps has transparency electrode；This transparency electrode is distributed isolated insulation
Layer, is distributed pixel electrode on this isolated insulation layer, and this pixel electrode is for sweep with this plural number bar with each this plural number data line
Centered by retouching the cross intersection region between line, the pixel electrode unit of a plurality of repeated arrangement is set, this pixel electrode list
Unit is electrically connected with drain electrode realization by running through a contact hole of this isolated insulation layer and this insulating barrier；Wherein, this transparency electrode
Plurality of openings region it is provided with, this transparency electrode and this pixel electrode in extending to the region of each this pixel electrode unit
There is overlapping region on the direction vertical with this array base palte, this overlapping region forms storage capacitor.
In order to reach above-mentioned or other purpose, the another aspect of this utility model proposes a kind of array base palte, including: provide
One substrate, arranges first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line；At this first gold medal
Belonging to and arrange first grid insulating barrier on the pattern of layer, above this first grid insulating barrier, whole EDS maps has transparency electrode；?
Second grid insulating barrier is set in this transparency electrode, is provided above semiconductor pattern at this second grid insulating barrier；At this partly
On conductive pattern, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number data line, this plural number
Data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), drain electrode；This second
Being distributed insulating barrier on layer metal thin film patterns, the most whole EDS maps has pixel electrode, and this pixel electrode is with each
Centered by cross intersection region between this plural number data line and this plural number bar scan line, a plurality of repeated arrangement is set
Pixel electrode unit, this pixel electrode unit is electrically connected with drain electrode realization by running through a contact hole of this insulating thick film layer；
Wherein, this transparency electrode is provided with plurality of openings region in extending to the region of each this pixel electrode unit, this transparent electrical
There is overlapping region with this pixel electrode in pole on the direction vertical with this array base palte, this overlapping region forms storage electric capacity
Device.
In order to reach above-mentioned or other purpose, the another aspect of this utility model proposes a kind of array base palte, including: provide
One substrate, the most whole face is disposed with transparency electrode, is provided above flat insulator layer in transparency electrode；In smooth insulation
Layer be provided above first layer metal Thinfilm pattern, this first layer metal Thinfilm pattern include plural number bar scan line；This first
On the pattern of metal level, gate insulator is set, is provided above semiconductor pattern at this gate insulator；At this quasiconductor figure
In case, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number data line, this plural number data
Line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), drain electrode；At this second layer metal
Being distributed insulating barrier on Thinfilm pattern, be distributed pixel electrode on which insulating layer, this pixel electrode is with each this plural number data
Centered by cross intersection region between line and this plural number bar scan line, the pixel electrode list of a plurality of repeated arrangement is set
Unit, this pixel electrode unit is electrically connected with drain electrode realization by running through a contact hole of this this insulating barrier；Wherein, this transparent electrical
Pole is provided with plurality of openings region in extending to the region of each this pixel electrode unit, this transparency electrode and this pixel electrode
There is overlapping region on the direction vertical with this array base palte, this overlapping region forms storage capacitor.
In order to reach above-mentioned or other purpose, the another aspect of this utility model proposes a kind of liquid crystal indicator, bag
Include: above-mentioned array base palte；Counter substrate, is oppositely arranged with this array base palte；Liquid crystal layer, is interposed in this array base palte opposed with this
Between substrate；Also include public electrode, be distributed in this counter substrate in face electrode pattern；Wherein, this common electrode layer with should
Transparency electrode applies same potential voltage simultaneously.
This utility model compared with prior art, has an advantage in that: the utilization ratio of light is high, the probability that light is disturbed
Low, display image quality is good.
Accompanying drawing explanation
Fig. 1 is the dot structure floor map of array base palte side in prior art；
Fig. 2 A is the black matrix structure floor map of counter substrate side in prior art；
Fig. 2 B is the dot structure floor map after array base palte and counter substrate are fitted in prior art；
Fig. 2 C is the light shield layer cross-sectional view of counter substrate side dot structure in prior art；
Fig. 3 is for schematically showing this utility model one embodiment array base palte side dot structure floor map；
Fig. 4 is for schematically showing array base palte side plane structure schematic diagram in this utility model Fig. 3；
Fig. 5 is for schematically showing this utility model another embodiment array base palte side dot structure floor map；
Fig. 6 is the cross-sectional view schematically showing this utility model first embodiment array substrate pixel structure；
Fig. 7 is to schematically show the storage capacitor structures schematic diagram shown in Fig. 6；
Fig. 8 A～8C is for schematically showing first embodiment array base palte difference making step planar structure schematic diagram；
Fig. 9 is the cross-sectional view schematically showing this utility model the second embodiment array substrate pixel structure；
Figure 10 is to schematically show the storage capacitor structures schematic diagram shown in Fig. 9；
Figure 11 is the cross-sectional view schematically showing this utility model the 3rd embodiment array substrate pixel structure；
Figure 12 A～12B is for schematically showing the second embodiment array base palte difference making step planar structure schematic diagram；
Figure 13 is the cross-sectional view schematically showing this utility model the 4th embodiment array substrate pixel structure；
Figure 14 is to schematically show the storage capacitor structures schematic diagram shown in Figure 13；
Figure 15 A～15D is for schematically showing the 4th embodiment array base palte difference making step planar structure schematic diagram；
Figure 16 A is for schematically showing this utility model the 5th embodiment array base palte side dot structure floor map；
Figure 16 B is to schematically show dot structure cross-section structure signal along BB ' direction in this utility model Figure 16 A
Figure；
Figure 17 is to schematically show the storage capacitor structures schematic diagram shown in Figure 16 B；
Figure 18 A～18D is for schematically showing the 5th embodiment array base palte difference making step planar structure schematic diagram；
Figure 19 is for schematically showing this utility model liquid crystal indicator cross-sectional view；
Figure 20 is for schematically showing this utility model liquid crystal indicator counter substrate planar structure schematic diagram；
Figure 21 descends cross-sectional view in working order for schematically showing this utility model liquid crystal indicator.
Detailed description of the invention
Below in conjunction with the accompanying drawings and specific embodiment, it is further elucidated with this utility model, it should be understood that these embodiments are only used for
This utility model is described rather than limits scope of the present utility model, after having read this utility model, art technology
Personnel all fall within the application claims limited range to the amendment of the various equivalent form of values of the present utility model.
Fig. 3 is for schematically showing this utility model one embodiment array base palte side dot structure floor map.Such as Fig. 3
Shown in, this utility model provides the dot structure of a kind of array base palte, including: scan line 101, semiconductor layer raceway groove 102, number
According to line 103, source electrode (data wire), drain electrode 104, contact hole 105, pixel electrode 106, transparency electrode 107.
Wherein, scan line 101 is entreated within the pixel with data wire 103 and is intersected in cross, in data wire 103 and scan line
The infall of 101 is provided with thin film transistor (TFT).Thin film transistor (TFT) is arranged on this plural number data line 103 and this plural number bar scan line
The cross intersection region of 101, the grid of thin film transistor (TFT) is the scan line 101 pattern in cross intersection region, and thin film is brilliant
The source electrode of body pipe is the data wire 103 pattern in cross intersection region, and the drain electrode 104 of thin film transistor (TFT), film crystal
The raceway groove 102 of pipe.Thin film transistor (TFT) drain electrode 104 be arranged over contact hole 105；Drain electrode 104 covering contact hole 105 and pixel
Electrode 107 realizes equipotential link.On four limits up and down of pixel, pixel electrode 107 and transparency electrode 106 part weight
Folded.
Fig. 4 is for schematically showing array base palte side plane structure schematic diagram in this utility model Fig. 3.As shown in Figure 4, this reality
Providing a kind of array base palte with novel, including the dot structure described in a plurality of Fig. 3, wherein, pixel electrode 107, with respectively
Being provided with the pixel electrode unit of a plurality of repeated arrangement centered by this cross intersection region individual, transparency electrode 106, in whole
It is distributed on this array base palte, and this transparency electrode 106 has setting in the region extending to each this pixel electrode unit 107
There is the open area of a plurality of repeated arrangement.
As shown in Figure 4, there is gap, left and right S1, upper and lower gap S2 between the pixel electrode 107 of neighbor.Gap S1 and
S2 is the least, and the light utilization ratio of pixel is the highest.The factor limiting S1 with S2 size includes: the exposure accuracy of exposure machine；Adjacent picture
Interference strength between element electrode voltage.Typically, gap S1 and S2 is at about 5um.In the diagram, pixel electrode 107 and transparent electrical
Pole 106 partly overlaps, and arranges the storage capacitor Cs of pixel.Overlapping region L1, L2, L3 and L4 are distributed in four limits of pixel
On.
In figure 3, transparency electrode 106 with the transmitance of pixel electrode 107 overlapping portion light splitting less than pixel electrode 107 with
The central area that transparency electrode 106 is underlapped, thus luminance difference is set at transparency electrode boundary.
In order to obscure the luminance difference of transparency electrode boundary member, Fig. 5 is for schematically showing the another enforcement of this utility model
Mode array base palte side dot structure floor map.As it is shown in figure 5, this utility model provides the pixel of a kind of array base palte
Structure, this dot structure is roughly the same with the dot structure described in above-described embodiment, the difference is that only a transparency electrode 106
Border is arranged to zigzag, the opening in i.e. this transparency electrode 106 extends to each neighboring area of each this pixel electrode 107
The border in region is irregular saw-tooth like pattern 108.By the transition of saw-tooth like pattern 108, both can be with smeared out boundary at
Luminance difference, it is also possible to eliminate the position visual impression on border.In order to obscure the transparency electrode 106 luminance difference at pixel boundary
Different, it is also possible to use other irregular patterns in the side, open area of transparency electrode 106.
In the dot structure that this utility model the respective embodiments described above are provided, transparency electrode is transparent conductive film, main
Metal film system to be had, oxidation film system, other compound film systems, polymeric membrane system, compound film system etc..(stannum is mixed specifically ITO
Miscellaneous three Indium sesquioxide .s), AZO (aluminium-doped zinc oxide), nano-silver thread, Graphene etc..Preferably, ITO material is used.
In the dot structure that this utility model the respective embodiments described above are provided, transparent electrode layer can be distributed in pixel electricity
The top of pole layer, can be distributed between pixel electrode and data wire metal layer, can be distributed in data wire metal layer and scanning
Between line metal level, can be distributed in below scan line metal level.
The first embodiment top of pixel electrode layer [transparent electrode layer be distributed in]
Fig. 6 is the cross-sectional view of this utility model first embodiment array substrate pixel structure.As shown in Figure 6,
Transparency electrode is designed above pixel electrode, can preferably shield doing between the pixel electrode voltage of neighbor
Disturb.
In pixel A A ' sectional view in direction, corresponding hierarchical relationship is: above the underlay substrate such as glass, plastics 111
Distribution scan line 101, is distributed gate insulator 112 above scan line 101, distribution half above gate insulator 112
Conductor layer 102, above semiconductor layer 102, distributed data line (source electrode) 103 and drain electrode 104, divide above data wire 103
Cloth protection insulating barrier 113, is distributed insulating thick film layer 114, above insulating thick film layer 114 above protection insulating barrier 113
Distribution pixel electrode 107, pixel electrode 107 by run through the contact hole 105 of insulating thick film layer 114 and protection insulating barrier 113 with
Drain electrode 104 realization is electrically connected, layout pitch insulating barrier 115 above pixel electrode 107, upper in spacer insulator layer 115
Side's distributing transparent electrode layer 106.According to actual needs, it is convenient to omit protection insulating barrier 113.
In conjunction with reference to Fig. 3, Fig. 6 and Fig. 7, pixel electrode and transparency electrode are depositing that four limit upper parts of pixel overlap to form
Storage electric capacity Cs.Because pixel electrode and transparency electrode are all transparent conductive films, the region of lap is still that transmission region,
The design of such structure can improve the light utilization ratio of pixel.
Fig. 7 is for schematically showing the storage capacitor structures schematic diagram shown in Fig. 6.As it is shown in fig. 7, transparency electrode
106 cover above adjacent pixel electrodes 107, can shield the electricity interference of adjacent pixel electrodes completely.
This utility model one embodiment additionally provides a kind of array base palte, including: as shown in Figure 8 A, first, it is provided that one is saturating
Bright substrate, forms first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line 101；This
Form gate insulator on the pattern of one metal level, above this gate insulator, form semiconductor pattern, such as quasiconductor ditch
Road pattern 102.
As shown in Figure 8 B, on this semiconductor pattern, form second layer metal Thinfilm pattern, this second layer metal thin film figure
Case includes plural number data line 103, and this plural number data line 103 and this plural number bar scan line 101 are in cross arranged crosswise；Also
Source electrode, drain electrode 104 including thin film transistor (TFT).
As shown in Figure 8 C, this second layer metal Thinfilm pattern is distributed insulating thick film layer, carves after covering insulating thick film layer
Erosion forms contact hole 105, forms pixel electrode 107 pattern the most again, and this pixel electrode 107 is with each this plural number data line
Centered by cross intersection region between 103 and this plural number bar scan line 101, form the pixel electrode of a plurality of repeated arrangement
Unit, this pixel electrode unit is electrically connected with drain electrode realization by running through a contact hole of this insulating thick film layer.
Being distributed isolated insulation layer on this pixel electrode 107, on this isolated insulation layer, whole EDS maps has transparency electrode；Its
In, this transparency electrode is formed with plurality of openings region in extending to the region of each this pixel electrode unit, this transparency electrode
There is overlapping region with this pixel electrode on the direction vertical with this array base palte, this overlapping region forms storage capacitor.
Eventually form the array base palte described in first embodiment.
Second embodiment [transparent electrode layer is distributed between pixel electrode and data wire metal layer]
Fig. 9 is the cross-sectional view schematically showing this utility model the second embodiment array substrate pixel structure.
As it is shown in figure 9, in pixel A A ' sectional view in direction, corresponding hierarchical relationship is: upper at the underlay substrate such as glass, plastics 111
Side's distribution scan line 101, is distributed gate insulator 112 above scan line 101, is distributed above gate insulator 112
Semiconductor layer 102, distributed data line (source electrode) 103 and drain electrode 104 above semiconductor layer 102, above data wire 103
Distribution protection insulating barrier 113, is distributed insulating thick film layer 114, upper at insulating thick film layer 114 above protection insulating barrier 113
Side's distributing transparent electrode layer 106, is distributed isolated insulation layer 115, at isolated insulation layer 115 above transparent electrode layer 106
Top distribution pixel electrode 107, pixel electrode 107 is by running through isolated insulation layer 115, insulating thick film layer 114 and protection insulation
The contact hole 105 of layer 113 is electrically connected with drain electrode 104 realization.According to actual needs, it is convenient to omit protection insulating barrier 113.
In conjunction with Fig. 3, Fig. 9 and Figure 10, the storage that pixel electrode overlaps to form in four limit upper parts of pixel with transparency electrode
Electric capacity Cs.Because pixel electrode and transparency electrode are all transparent conductive films, the region of lap is still that transmission region, this
The structure design of sample can improve the light utilization ratio of pixel.
3rd embodiment [transparent electrode layer is distributed between pixel electrode and data wire metal layer]
3rd embodiment is roughly the same with the structure of the second embodiment, and difference is that transparent electrode layer is arranged on protection
Between insulating barrier and insulating thick film layer, specifically, Figure 11 is for schematically showing this utility model the 3rd embodiment array base palte picture
The cross-sectional view of element structure.As shown in figure 11, in pixel A A ' sectional view in direction, corresponding hierarchical relationship is: at glass
The top distribution scan line 101 of the underlay substrate such as glass, plastics 111, is distributed gate insulator 112 above scan line 101,
The top distribution semiconductor layer 102 of gate insulator 112, distributed data line (source electrode) 103 and leakage above semiconductor layer 102
Pole 104, distribution protection insulating barrier 113 above data wire 103, distributing transparent electrode layer above protection insulating barrier 113
106, above transparent electrode layer 106, it is distributed insulating thick film layer 114, above insulating thick film layer 114, is distributed pixel electrode
107, pixel electrode 107 is by running through contact hole 105 and drain electrode 104 realization of insulating thick film layer 114 and protection insulating barrier 113
It is electrically connected.
The another embodiment of this utility model additionally provides a kind of array base palte, including: first, as Fig. 8 A provides a transparent base
Plate, forms first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line 101；At this first gold medal
Belong to and on the pattern of layer, form gate insulator, above this gate insulator, form semiconductor pattern, such as semiconductor channel figure
Case 102；
Then, as shown in Figure 8 B, on this semiconductor pattern, second layer metal Thinfilm pattern, this second layer metal are formed
Thinfilm pattern includes plural number data line 103, and this plural number data line 103 intersects in cross with this plural number bar scan line 101
Arrange；Also include the source electrode of thin film transistor (TFT), drain electrode 104.
Then, as illustrated in fig. 12, this second layer metal Thinfilm pattern is distributed insulating barrier, such as covering protection insulating barrier
With insulating thick film layer, the most whole EDS maps has transparency electrode 106.
Then, as shown in Figure 12 B, this transparency electrode is distributed isolated insulation layer, after covering isolated insulation layer, etches shape
Becoming contact hole 105, form pixel electrode the most again, this pixel electrode is to scan with this plural number bar with each this plural number data line
Centered by cross intersection region between line, form the pixel electrode unit of a plurality of repeated arrangement, this pixel electrode unit
It is electrically connected with drain electrode realization by running through a contact hole of this isolated insulation layer and this insulating barrier.
Wherein, this transparency electrode is formed with plurality of openings region in extending to the region of each this pixel electrode unit,
There is overlapping region with this pixel electrode in this transparency electrode on the direction vertical with this array base palte, this overlapping region is formed and deposits
Storage capacitor.Eventually form the array base palte described in the second embodiment.
4th embodiment [transparent electrode layer is distributed between data wire metal layer and scan line metal level]
Figure 13 is the cross-sectional view schematically showing this utility model the 4th embodiment array substrate pixel structure.
As shown in figure 13, in pixel A A ' sectional view in direction, corresponding hierarchical relationship is: at the underlay substrate such as glass, plastics 111
Top distribution scan line 101, is distributed first grid insulating barrier 112a, at first grid insulating barrier above scan line 101
The top distributing transparent electrode layer 106 of 112a, is distributed second grid insulating barrier 112b, the above transparent electrode layer 106
The top distribution semiconductor layer 102 of two gate insulator 112b, distributed data line (source electrode) 103 above semiconductor layer 102
With drain electrode 104, distribution protection insulating barrier 113 above data wire 103, above protection insulating barrier 113, it is distributed thick film exhausted
Edge layer 114, is distributed pixel electrode 107 above insulating thick film layer 114, and pixel electrode 107 is by running through insulating thick film layer 114
It is electrically connected with drain electrode 104 realization with the contact hole 105 of protection insulating barrier 113.According to actual needs, it is convenient to omit protection insulation
Layer 113.
In conjunction with Fig. 3, Figure 13 and Figure 14, the storage that pixel electrode overlaps to form in four limit upper parts of pixel with transparency electrode
Electric capacity Cs.Because pixel electrode and transparency electrode are all transparent conductive films, the region of lap is still that transmission region, this
The structure design of sample can improve the light utilization ratio of pixel.
Another embodiment of this utility model additionally provides a kind of array base palte, including: as shown in fig. 15, first, it is provided that one
Transparency carrier, forms first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line 101；At this
Forming first grid insulating barrier on the pattern of the first metal layer, above this first grid insulating barrier, whole EDS maps has transparent electrical
Pole 106；.
As shown in fig. 15b, this transparency electrode forms second grid insulating barrier, above this second grid insulating barrier
Form semiconductor pattern, such as semiconductor channel pattern 102.
As shown in figure 15 c, on this semiconductor pattern, form second layer metal Thinfilm pattern, this second layer metal thin film
Pattern includes plural number data line 103, and this plural number data line 103 and this plural number bar scan line 101 are in cross arranged crosswise；
Also include the source electrode of thin film transistor (TFT), drain electrode 104.
As shown in figure 15d, this second layer metal Thinfilm pattern is distributed insulating thick film layer, such as covering protection insulating barrier and
After insulating thick film layer, above drain electrode 104, etching forms contact hole 105.On this insulating thick film layer, whole EDS maps has pixel
Electrode, this pixel electrode covers contact hole 105.
This pixel electrode is with the cross intersection region between each this plural number data line and this plural number bar scan line
Centered by, forming the pixel electrode unit of a plurality of repeated arrangement, this pixel electrode unit is by running through this insulating thick film layer
One contact hole is electrically connected with drain electrode realization；Wherein, shape in this transparency electrode extends to the region of each this pixel electrode unit
Becoming to have plurality of openings region, there is crossover region with this pixel electrode in this transparency electrode on the direction vertical with this array base palte
Territory, this overlapping region forms storage capacitor.Eventually form the array base palte described in the 4th embodiment.
5th embodiment [transparent electrode layer is distributed in below scan line metal level]
Figure 16 A is for schematically showing this utility model the 5th embodiment array base palte side dot structure floor map；Figure
16B is for schematically show dot structure cross-sectional view along BB ' direction in this utility model Figure 16 A.Such as Figure 16 A and
Shown in 16B, in pixel B B ' sectional view in direction, corresponding hierarchical relationship is: above the underlay substrate such as glass, plastics 111
Distributing transparent electrode 106, is distributed flat insulator layer 116 above transparency electrode 106, divides above flat insulator layer 116
Cloth scan line 101, is distributed gate insulator 112 above scan line 101, is distributed and partly leads above gate insulator 112
Body layer 102, above semiconductor layer 102, distributed data line (source electrode) 103 and drain electrode 104, divide above data wire 103
Cloth protection insulating barrier 113, is distributed insulating thick film layer 114, above insulating thick film layer 114 above protection insulating barrier 113
Distribution pixel electrode 107, pixel electrode 107 by run through the contact hole 105 of insulating thick film layer 114 and protection insulating barrier 113 with
Drain electrode 104 realization is electrically connected.According to actual needs, it is convenient to omit protection insulating barrier 113.
In conjunction with Fig. 3,16A and 16B and Figure 17, pixel electrode overlaps to form in four limit upper parts of pixel with transparency electrode
Storage electric capacity Cs.Because pixel electrode and transparency electrode are all transparent conductive films, the region of lap is still that transparent area
Territory, the design of such structure can improve the light utilization ratio of pixel.
This utility model another embodiment additionally provides a kind of array base palte, including: first, as shown in Figure 18 A, it is provided that one
Transparency carrier, the most whole face is disposed with transparency electrode 106, forms flat insulator layer above transparency electrode 106；?
The top of flat insulator layer forms first layer metal Thinfilm pattern, and this first layer metal Thinfilm pattern includes plural number bar scan line
101。
Then, as shown in figure 18b, the pattern of this first metal layer forms gate insulator, at this gate insulator
Top formed semiconductor pattern, such as semiconductor channel 102 pattern.
Then, as shown in figure 18 c, on this semiconductor pattern, second layer metal Thinfilm pattern, this second layer metal are formed
Thinfilm pattern includes plural number data line, and this plural number data line 103 and this plural number bar scan line 101 are in the cross cloth that intersects
Put；Also include the source electrode of thin film transistor (TFT), drain electrode 104.
Then, as shown in Figure 18 D, this second layer metal Thinfilm pattern is distributed insulating barrier, such as protection insulating barrier and thickness
Film insulating barrier, after continuous covering protection insulating barrier and insulating thick film layer, etching forms contact hole 105, divides the most on which insulating layer
Cloth pixel electrode.
This pixel electrode is with the cross intersection region between each this plural number data line and this plural number bar scan line
Centered by, forming the pixel electrode unit of a plurality of repeated arrangement, this pixel electrode unit is by running through the one of this this insulating barrier
Contact hole is electrically connected with drain electrode realization；Wherein, formed in this transparency electrode extends to the region of each this pixel electrode unit
Having plurality of openings region, there is crossover region with this pixel electrode in this transparency electrode on the direction vertical with this array base palte
Territory, this overlapping region forms storage capacitor.Eventually form the array base palte described in the 5th embodiment.
Figure 19 is for schematically showing this utility model liquid crystal indicator cross-sectional view.As shown in figure 19, this reality
A kind of liquid crystal indicator is additionally provided with novel, including: the respective embodiments described above and the array base palte of corresponding each embodiment
100, counter substrate 200, and it is located in the liquid crystal functional layer 300 between this array base palte 100 and this counter substrate 200.
Figure 20 is for schematically showing this utility model liquid crystal indicator counter substrate planar structure schematic diagram.Such as Figure 20 institute
Showing, the counter substrate 200 that this liquid crystal display device uses, including underlay substrate 211 (not shown), public electrode 201, shading
Pattern 202, spacer 203.As required, it is convenient to omit light-shielding pattern 202.In Figure 19, at counter substrate 200 and the first base
It is liquid crystal functional layer 300 between plate 100, including counter substrate side alignment film 303, liquid crystal 301, array base palte side alignment film 302.
Figure 19 descends cross-sectional view in working order for schematically showing this utility model liquid crystal indicator.Such as figure
Shown in 19, transparency electrode 106 and the public electrode 201 in counter substrate, current potential is fixed, and does not becomes with the change of pixel voltage
Change.Preferably, transparency electrode is equal with the current potential of the public electrode 201 in counter substrate.In gap S1 and S2 region, due to thoroughly
Potential difference between prescribed electrode and public electrode 201 is 0, and the Liquid Crystal Molecules Alignment state being positioned at this region is fixed, not with pixel
The change of voltage and change, the state of liquid crystal molecule is controlled.As shown in figure 21, though pixel electrode and public electrode 201 it
Between apply various different current potential, at gap S1 and the liquid crystal molecule in S2 region, ordered state is all fixing.
This utility model provides each way of example and the array base palte of each embodiment offer and liquid crystal indicator, has
Advantages below:
(1) metal wire is few: only scan line and two perpendicular metal wires of data wire.Metal wire is few, metal shading
The least with reflective impact.
(2) metal wire is thin: across protective layer and thick film layers between scan line, data wire and pixel electrode, between pixel
Coupling electric capacity little, it is the thinnest that metal wire can do.Metal wire is thin, and metal shading is the least with reflective impact.
(3) for using UV2A(Ultraviolet induced multi-domain Vertical Alignment)
The liquid crystal display mode of technology, scan line and data wire are exactly the demarcation line between liquid crystal display farmland and adjacent lcd display farmland,
Black stricture of vagina between display farmland is dispensed directly onto above metal wire, the most additionally takies lighttight region, the light utilization ratio of pixel
High.
(4) for using in the VA Display Technique of normally black mode, transparency electrode on the first substrate and counter substrate
Potential difference between public electrode is set to 0, in gap S1 and S2 region, and the black state that liquid crystal display is stable, such that it is able between Sheng Lveing
The black matrix" in counter substrate directly over gap S1 and S2.Use the technical solution of the utility model, transparency electrode and pixel
Overlapping area between electrode is abundant, and the electric lines of force of pixel electrode focuses primarily upon between pixel electrode and transparency electrode, distributes
Electric lines of force outside pixel electrode is few, and the disturbance to gap S1 and the liquid crystal in S2 region is faint, can solve pixel electrode electricity
The leakage problem of gap S1 and S2 that pressure (electric lines of force) disturbance causes.
(5) for using in the VA Display Technique of normal white mode, transparency electrode on the first substrate and counter substrate
Potential difference between public electrode is set to 6V, in gap S1 and S2 region, and the black state that liquid crystal display is stable, such that it is able between Sheng Lveing
The black matrix" in counter substrate directly over gap S1 and S2.Use the technical solution of the utility model, transparency electrode and pixel
Overlapping area between electrode is abundant, and the electric lines of force of pixel electrode focuses primarily upon between pixel electrode and transparency electrode, distributes
Electric lines of force outside pixel electrode is few, and the disturbance to gap S1 and the liquid crystal in S2 region is faint, can solve pixel electrode electricity
The leakage problem of gap S1 and S2 that pressure (electric lines of force) disturbance causes.
Preferred implementation of the present utility model described in detail above, but, this utility model is not limited to above-mentioned reality
Execute the detail in mode, in technology concept of the present utility model, the technical solution of the utility model can be entered
The multiple equivalents of row, these equivalents belong to protection domain of the present utility model.
It is further to note that each the concrete technical characteristic described in above-mentioned detailed description of the invention, at not lance
In the case of shield, can be combined by any suitable means.In order to avoid unnecessary repetition, this utility model is to respectively
Plant possible compound mode to illustrate the most separately.
Claims (10)
1. an array base palte, including:
One substrate, has the plural data line in cross arranged crosswise and plural number bar scan line；
Active member, is arranged on the cross intersection region of this plural number data line and this plural number bar scan line；
Pixel electrode, is formed with the pixel electrode unit of a plurality of repeated arrangement centered by each this cross intersection region,
And be electrically connected with this active member by a contact hole；
Transparency electrode, in whole EDS maps on the substrate, and this transparency electrode has and extends to each this pixel electrode unit
The open area of a plurality of repeated arrangement it is formed with in region.
Array base palte the most according to claim 1, it is characterised in that also include:
Being provided with spacing distance between the pixel electrode unit of these a plurality of repeated arrangement, this transparency electrode extends to each this picture
Element electrode unit each neighboring area in be formed at the overlapping region on the direction vertical with this array base palte, this transparency electrode with
Overlapping region between this pixel electrode unit forms storage capacitor.
Array base palte the most according to claim 2, it is characterised in that
This transparency electrode is distributed in the top of this pixel electrode, or be distributed in this pixel electrode and this data wire metal layer it
Between, or be distributed between this data wire metal layer and this scan line metal level, or be distributed in below this scan line metal level.
Array base palte the most according to claim 2, it is characterised in that
This transparency electrode extends to the border of the open area in each neighboring area of each this pixel electrode unit in not advising
Saw-tooth like pattern then.
5. according to the array base palte described in any one of claim 1-4, it is characterised in that
The material of this transparency electrode uses tin dope three Indium sesquioxide., aluminium-doped zinc oxide, nano-silver thread or Graphene.
6. an array base palte, including:
Thering is provided a substrate, arrange the first metal layer Thinfilm pattern, this first metal layer Thinfilm pattern includes plural number bar scan line；
The pattern of this first metal layer arranges gate insulator, is provided above semiconductor pattern at this gate insulator；
On this semiconductor pattern, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number bar number
According to line, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), leakage
Pole；
Being distributed insulating thick film layer on this second layer metal Thinfilm pattern, on this insulating thick film layer, whole EDS maps has pixel electricity
Pole, this pixel electrode is to be with the cross intersection region between each this plural number data line and this plural number bar scan line
The heart, arranges the pixel electrode unit of a plurality of repeated arrangement, and this pixel electrode unit connects by run through this insulating thick film layer one
Contact hole is electrically connected with drain electrode realization；
Being distributed isolated insulation layer on this pixel electrode, on this isolated insulation layer, whole EDS maps has transparency electrode；
Wherein, this transparency electrode is provided with plurality of openings region in extending to the region of each this pixel electrode unit, and this is saturating
There is overlapping region with this pixel electrode in prescribed electrode on the direction vertical with this array base palte, this overlapping region forms storage electricity
Container.
7. an array base palte, including:
Thering is provided a substrate, arrange the first metal layer Thinfilm pattern, this first metal layer Thinfilm pattern includes plural number bar scan line；
The pattern of this first metal layer arranges gate insulator, is provided above semiconductor pattern at this gate insulator；
On this semiconductor pattern, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number bar number
According to line, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), leakage
Pole；
Being distributed insulating barrier on this second layer metal Thinfilm pattern, the most whole EDS maps has transparency electrode；
In this transparency electrode be distributed isolated insulation layer, on this isolated insulation layer be distributed pixel electrode, this pixel electrode be with
Centered by cross intersection region between each this plural number data line and this plural number bar scan line, a plurality of repetition is set and arranges
The pixel electrode unit of row, this pixel electrode unit is by running through a contact hole and the drain electrode of this isolated insulation layer and this insulating barrier
Realization is electrically connected；
Wherein, this transparency electrode is provided with plurality of openings region in extending to the region of each this pixel electrode unit, and this is saturating
There is overlapping region with this pixel electrode in prescribed electrode on the direction vertical with this array base palte, this overlapping region forms storage electricity
Container.
8. an array base palte, including:
Thering is provided a substrate, arrange the first metal layer Thinfilm pattern, this first metal layer Thinfilm pattern includes plural number bar scan line；
The pattern of this first metal layer arranges first grid insulating barrier, whole EDS maps above this first grid insulating barrier
There is transparency electrode；
This transparency electrode arranges second grid insulating barrier, is provided above semiconductor pattern at this second grid insulating barrier；
On this semiconductor pattern, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number bar number
According to line, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), leakage
Pole；
Being distributed insulating thick film layer on this second layer metal Thinfilm pattern, on this insulating thick film layer, whole EDS maps has pixel electricity
Pole, this pixel electrode is to be with the cross intersection region between each this plural number data line and this plural number bar scan line
The heart, arranges the pixel electrode unit of a plurality of repeated arrangement, and this pixel electrode unit connects by run through this insulating thick film layer one
Contact hole is electrically connected with drain electrode realization；
Wherein, this transparency electrode is provided with plurality of openings region in extending to the region of each this pixel electrode unit, and this is saturating
There is overlapping region with this pixel electrode in prescribed electrode on the direction vertical with this array base palte, this overlapping region forms storage electricity
Container.
9. an array base palte, including:
There is provided a substrate, the most whole face to be disposed with transparency electrode, be provided above flat insulator layer in transparency electrode；
Being provided above the first metal layer Thinfilm pattern in flat insulator layer, this first metal layer Thinfilm pattern includes that plural number bar is swept
Retouch line；
The pattern of this first metal layer arranges gate insulator, is provided above semiconductor pattern at this gate insulator；
On this semiconductor pattern, arranging second layer metal Thinfilm pattern, this second layer metal Thinfilm pattern includes plural number bar number
According to line, this plural number data line and this plural number bar scan line are cross arranged crosswise；Also include the source electrode of thin film transistor (TFT), leakage
Pole；
Being distributed insulating barrier on this second layer metal Thinfilm pattern, be distributed pixel electrode on which insulating layer, this pixel electrode is
Centered by the cross intersection region between each this plural number data line and this plural number bar scan line, a plurality of repetition is set
The pixel electrode unit of arrangement, this pixel electrode unit realizes electricity even by running through a contact hole of this insulating barrier with drain electrode
Connect；
Wherein, this transparency electrode is provided with plurality of openings region in extending to the region of each this pixel electrode unit, and this is saturating
There is overlapping region with this pixel electrode in prescribed electrode on the direction vertical with this array base palte, this overlapping region forms storage electricity
Container.
10. a liquid crystal indicator, including:
Array base palte as described in claim 1-9；
Counter substrate, is oppositely arranged with this array base palte；
Liquid crystal layer, is interposed between this array base palte and this counter substrate；
Also include public electrode, be distributed in this counter substrate in face electrode pattern；
Wherein, this common electrode layer and this transparency electrode apply same potential voltage simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620618611.7U CN205787506U (en) | 2016-06-21 | 2016-06-21 | Array base palte and liquid crystal indicator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620618611.7U CN205787506U (en) | 2016-06-21 | 2016-06-21 | Array base palte and liquid crystal indicator |
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| Publication Number | Publication Date |
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| CN205787506U true CN205787506U (en) | 2016-12-07 |
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ID=58130317
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| CN201620618611.7U Expired - Fee Related CN205787506U (en) | 2016-06-21 | 2016-06-21 | Array base palte and liquid crystal indicator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106125423A (en) * | 2016-06-21 | 2016-11-16 | 上海纪显电子科技有限公司 | Liquid crystal indicator, array base palte and preparation method thereof |
| CN112086028A (en) * | 2020-09-17 | 2020-12-15 | Tcl华星光电技术有限公司 | Pixel arrangement structure and display panel |
| CN114114763A (en) * | 2020-08-27 | 2022-03-01 | 合肥京东方显示技术有限公司 | Display substrate and display panel |
-
2016
- 2016-06-21 CN CN201620618611.7U patent/CN205787506U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106125423A (en) * | 2016-06-21 | 2016-11-16 | 上海纪显电子科技有限公司 | Liquid crystal indicator, array base palte and preparation method thereof |
| CN114114763A (en) * | 2020-08-27 | 2022-03-01 | 合肥京东方显示技术有限公司 | Display substrate and display panel |
| CN114114763B (en) * | 2020-08-27 | 2023-08-08 | 合肥京东方显示技术有限公司 | Display substrate and display panel |
| CN112086028A (en) * | 2020-09-17 | 2020-12-15 | Tcl华星光电技术有限公司 | Pixel arrangement structure and display panel |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161207 Termination date: 20180621 |