CN104635393A - Thin film transistor array substrate and liquid crystal display device - Google Patents
Thin film transistor array substrate and liquid crystal display device Download PDFInfo
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- CN104635393A CN104635393A CN201510066841.7A CN201510066841A CN104635393A CN 104635393 A CN104635393 A CN 104635393A CN 201510066841 A CN201510066841 A CN 201510066841A CN 104635393 A CN104635393 A CN 104635393A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
- G02F1/133788—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by light irradiation, e.g. linearly polarised light photo-polymerisation
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The invention discloses a thin film transistor array substrate. The thin film transistor array substrate comprises a substrate; a first metal layer, which is formed on the substrate and connected with a corresponding scanning line; a first insulation protecting layer, which is formed on the substrate; a semiconductor layer, which is formed on the first insulation protecting layer; a pixel electrode, which is formed on the first insulation protecting layer and located at every pixel zone; a second metal layer, which is formed on the semiconductor layer, and includes a source electrode and a drain electrode, wherein the source electrode is connected with corresponding data line, and the drain electrode is connected with the corresponding pixel electrode; the second insulation protecting layer forms on the second metal layer, and covers every data line and every scanning line; a third insulation protecting layer, which forms on the second insulation protecting layer; a public electrode, which forms on the third insulation protecting layer. The thin film transistor array substrate can improve the penetration rate, decrease load and reduce power consumption. The invention further relates to a liquid crystal display device.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly a kind of thin-film transistor array base-plate and there is its liquid crystal indicator.
Background technology
At present, liquid crystal indicator (LCD, Liquid Crystal Display) display screen increasing, in large-sized display screen, number of pixels (the PPI that per inch has, Pixels Per Inch) numerical value is higher, and namely representing display screen can with higher density display image, and the details of image will be abundanter.But penetrance and the aperture opening ratio of the liquid crystal indicator of existing high PPI are still lower.In order to improve penetrance and the aperture opening ratio of liquid crystal indicator, general method uses new material or uses new technology as low-temperature polysilicon silicon technology (LTPS, Low Temperature Poly-silicon), Organic Light Emitting Diode technology (OLED, Organic Light Emitting Diode) etc., but the process conditions of new material and new technology is harsh and yield is lower.
Figure 1A to Fig. 1 F is the Making programme part section structural representation of six road optical cover process of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator.Thin-film transistor array base-plate comprises and is arranged at multi-strip scanning line on substrate 210 and a plurality of data lines, and multi-strip scanning line and a plurality of data lines are mutually intersected and limited multiple pixel region.The crossover location of every bar sweep trace and data line is provided with thin film transistor (TFT).Figure 1A to Fig. 1 F is the part section structure of a pixel region of thin-film transistor array base-plate and the thin film transistor (TFT) position of correspondence.
First, as shown in Figure 1A, utilize first optical cover process, form grid 211 at substrate 210, grid 211 is electrically connected with corresponding sweep trace.Secondly, as shown in Figure 1B, form gate insulator 212 over the substrate 210 and cover gate 211, utilize second optical cover process, gate insulator 212 is formed semiconductor layer 213, and the position of semiconductor layer 213 is positioned at directly over grid 211.Afterwards, as shown in Figure 1 C, after formation semiconductor layer 213, utilize the 3rd road optical cover process, then form pixel electrode 214 on gate insulator 212.Come again, as shown in figure ip, after pixel electrode 214 is formed, utilize the 4th road optical cover process, semiconductor layer 213 is formed source electrode 215a and drain electrode 215b, source electrode 215a does not contact each other with drain electrode 215b, and source electrode 215a is electrically connected with corresponding data line, and drain electrode 215b contacts with pixel electrode 214 and realizes being electrically connected.Then, as referring to figure 1e, forming thickness is
insulating protective layer 216 and cover source electrode 215a, drain electrode 215b and pixel electrode 214; and utilize the 5th road optical cover process; the second through hole (figure does not illustrate) is formed at insulating protective layer 216; the viewing area that second through hole is formed in thin-film transistor array base-plate is peripheral, for making periphery line.In addition after, as shown in fig. 1f, utilize the 6th road optical cover process, insulating protective layer 216 is formed public electrode 217.
But utilize the thin-film transistor array base-plate that six road optical cover process of prior art make, the thickness of insulating protective layer 216 is
make the distance between pixel electrode 214 and public electrode 217 larger, not only cause making the intensity of the electric field produced between pixel electrode 214 and public electrode 217 little, and making the response time of the liquid crystal indicator of this thin-film transistor array base-plate of employing slow, penetrance is low.In addition, between data line and public electrode 217 across thickness be only
insulating protective layer 216, the stray capacitance that data line is produced is comparatively large, thus increases load, causes power consumption larger.
Fig. 2 A to Fig. 2 G is the Making programme part section structural representation of seven road optical cover process of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator.First, as shown in Figure 2 A, utilize first optical cover process, form grid 11 at substrate 10.Secondly, as shown in Figure 2 B, form gate insulator 12 on the substrate 10 and cover gate 11, utilize second optical cover process, gate insulator 12 is formed semiconductor layer 13, and the position of semiconductor layer 13 is positioned at directly over grid 11.Then, as shown in Figure 2 C, after semiconductor layer 13 is formed, the 3rd road optical cover process is utilized, gate insulator 12 and semiconductor layer 13 form source electrode 14a and drain electrode 14b, source electrode 14a and drain electrode 14b separate and directly contact the semiconductor layer 13 of also cover part respectively with semiconductor layer 13.Afterwards, as shown in Figure 2 D, after source electrode 14a and drain electrode 14b, forming thickness is
first insulating protective layer 15, and cover source electrode 14a, drain electrode 14b and from the semiconductor layer 13 that comes out between source electrode 14a and drain electrode 14b, and utilize the 4th road optical cover process, form the first through hole 15a with the drain electrode 14b of exposed portion at the first insulating protective layer 15.Then, as shown in Figure 2 E, utilize the 5th road optical cover process, the first insulating protective layer 15 forms pixel electrode 16, pixel electrode 16 is inserted in the first through hole 15a and is contacted with drain electrode 14b.Come, as shown in Figure 2 F, forming thickness is again
second insulating protective layer 17, and utilize the 6th road optical cover process, form the second through hole (figure does not illustrate) at the second insulating protective layer 17, the viewing area that the second through hole is formed in thin-film transistor array base-plate is peripheral, for making periphery line.In addition after, as shown in Figure 2 G, utilize the 7th road optical cover process, the second insulating protective layer 17 forms public electrode 18.
But; drain electrode 14b in the pixel region of the thin-film transistor array base-plate utilizing seven road optical cover process of prior art to make needs to be designed to larger area; then the first insulating protective layer 15 above correspondence drain electrode 14b forms the first through hole 15a and contacts with pixel electrode 16; and the material of the 14b that drains is light-proof material; shelter from the partial light permeability region in the pixel region in thin-film transistor array base-plate; make the aperture area in the pixel region of thin-film transistor array base-plate less, cause the aperture opening ratio of liquid crystal indicator and penetrance still low.
Therefore, improve the aperture opening ratio of liquid crystal indicator and penetrance, promote response speed simultaneously, reduce power consumption become Dang Xia Very problem to be solved.
Summary of the invention
The object of the present invention is to provide a kind of thin-film transistor array base-plate, can aperture opening ratio be increased, improve penetrance, and can load be reduced, reduce power consumption.
Another object of the present invention is to provide a kind of liquid crystal indicator, can aperture opening ratio be increased, improve penetrance, and can load be reduced, reduce power consumption.
It is adopt following technical scheme to realize that the present invention solves its technical matters.
A kind of thin-film transistor array base-plate, it a plurality of data lines comprising substrate, arrange multi-strip scanning line on the substrate and be arranged on above this multi-strip scanning line, this multi-strip scanning line and this plurality of data lines are mutually intersected and are limited multiple pixel region.This thin-film transistor array base-plate also comprises the first metal layer, the first insulating protective layer, semiconductor layer, pixel electrode, the second metal level, the second insulating protective layer, the 3rd insulating protective layer and public electrode.This first metal layer is formed on the substrate, and connects with this corresponding sweep trace; This first insulating protective layer is formed on the substrate and covers this first metal layer and this multi-strip scanning line; This semiconductor layer to be formed on this first insulating protective layer and to be positioned at above this first metal layer; This pixel electrode to be formed on this first insulating protective layer and to be positioned at respectively this pixel region; This second metal level is formed on this semiconductor layer, and this second metal level comprises source electrode and drain electrode, and this source electrode connects with this corresponding data line, and this drain electrode connects with this corresponding pixel electrode; This second insulating protective layer is formed on this second metal level, and this second insulating protective layer also covers respectively this data line and respectively this sweep trace simultaneously, and this pixel electrode respectively in this pixel region is not covered by this second insulating protective layer; 3rd insulating protective layer is formed on this second insulating protective layer, and covers this pixel electrode respectively in this pixel region; This public electrode is formed on the 3rd insulating protective layer.
In the preferred embodiment, this drain electrode is the strip of bending, and one end of this drain electrode is connected with this semiconductor layer, and the other end of this drain electrode is directly connected with this pixel electrode.
In the preferred embodiment, the thickness of the 3rd insulating protective layer is less than the thickness of this second insulating protective layer.
In the preferred embodiment, the thickness of this second insulating protective layer is
the thickness of the 3rd insulating protective layer is
In the preferred embodiment, this second insulating protective layer also covers this source electrode, this drain electrode and from this semiconductor layer exposed between this source electrode and this drain electrode further.
A kind of liquid crystal indicator, it comprises above-mentioned thin-film transistor array base-plate.
In the preferred embodiment, this liquid crystal indicator comprises colored filter substrate that this thin-film transistor array base-plate and this thin-film transistor array base-plate be oppositely arranged, is arranged on liquid crystal layer between thin-film transistor array base-plate and colored filter substrate.
A method for making for thin-film transistor array base-plate, it is included in substrate and forms the first metal layer and multi-strip scanning line, and this first metal layer connects with this corresponding sweep trace; Form the first insulating protective layer, and cover this first metal layer and this multi-strip scanning line, and form semiconductor layer on this first insulating protective layer, this semiconductor layer is positioned at above this first metal layer; This first insulating protective layer forms pixel electrode; This semiconductor layer is formed the second metal level and a plurality of data lines, and this multi-strip scanning line and this plurality of data lines are mutually intersected and are limited multiple pixel region, and this pixel electrode is positioned at respectively this pixel region; This second metal level comprises source electrode and drain electrode, and this source electrode connects with this corresponding data line, and this drain electrode connects with this corresponding pixel electrode; This second metal level forms the second insulating protective layer, and this second insulating protective layer also covers respectively this data line and respectively this sweep trace simultaneously, and this pixel electrode respectively in this pixel region is not covered by this second insulating protective layer; This second insulating protective layer forms the 3rd insulating protective layer, and covers this pixel electrode respectively in this pixel region; 3rd insulating protective layer forms public electrode.
In the preferred embodiment, be included in further and the 3rd insulating protective layer form alignment film and covers the 3rd insulating protective layer and this public electrode, this alignment film adopts ultraviolet light to carry out orientation.
In the preferred embodiment, the thickness of the 3rd insulating protective layer is less than the thickness of this second insulating protective layer.
Thin-film transistor array base-plate of the present invention and the liquid crystal indicator with it; its the second metal level, data line and semiconductor layer are provided with the second insulating protective layer and the two-layer protective seam of the 3rd insulating protective layer; across the second insulating protective layer and the two-layer protective seam of the 3rd insulating protective layer between public electrode and data line; the stray capacitance that data line is produced voluntarily reduces; thus reduce load; reduce power consumption, and improve penetrance.In addition; only there is separately the 3rd thinner insulating protective layer of a layer thickness between pixel electrode and public electrode; therefore can produce larger electric field between pixel electrode and public electrode, thus reduce the response time of liquid crystal indicator, and improve penetrance simultaneously.And the drain electrode of the second metal level is the strip of bending, increases the aperture opening ratio of thin-film transistor array base-plate, and improves penetrance.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of instructions, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail.
Accompanying drawing explanation
Figure 1A to Fig. 1 F is the Making programme part section structural representation of six road optical cover process of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator.
Fig. 2 A to Fig. 2 G is the Making programme part section structural representation of seven road optical cover process of the thin-film transistor array base-plate of existing a kind of liquid crystal indicator.
Fig. 3 is the part plan structural representation of the thin-film transistor array base-plate of the liquid crystal indicator of present pre-ferred embodiments.
Fig. 4 A to Fig. 4 G is the section Making programme schematic diagram of thin-film transistor array base-plate along IV in Fig. 3-IV line of present pre-ferred embodiments.
Fig. 5 is the cross-sectional view of thin-film transistor array base-plate along the V-V line in Fig. 3 of present pre-ferred embodiments.
Fig. 6 is the broken section structural representation of the linear position data of liquid crystal indicator of the present invention.
Fig. 7 is the effect contrast figure of the liquid crystal indicator of the thin-film transistor array base-plate with present pre-ferred embodiments and the penetrance-voltage of existing liquid crystal indicator.
Fig. 8 is the effect contrast figure of the liquid crystal indicator of the thin-film transistor array base-plate with present pre-ferred embodiments and the penetrance-time of existing liquid crystal indicator.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the thin-film transistor array base-plate proposed according to the present invention and have the embodiment of liquid crystal indicator of thin-film transistor array base-plate, structure, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Fig. 3 is the part plan structural representation of the thin-film transistor array base-plate of the liquid crystal indicator of present pre-ferred embodiments.Fig. 4 A to Fig. 4 G is the section Making programme schematic diagram of thin-film transistor array base-plate along IV in Fig. 3-IV line of present pre-ferred embodiments.See also Fig. 3 and Fig. 4 A to Fig. 4 G, it should be noted that, thin-film transistor array base-plate 100 comprise roughly along horizontal direction arrange multi-strip scanning line 101 and be roughly arranged on a plurality of data lines 102 above multi-strip scanning line 101 along vertical direction, and multi-strip scanning line 101 and a plurality of data lines 102 mutual intersection limit multiple pixel region P, sweep trace 101 and data line 102 crossover location place are provided with thin film transistor (TFT), structure and the forming step of sweep trace 101 and data line 102 are well known to those skilled in the art technology, do not repeat them here.In order to illustrative simplicity, Fig. 3 and Fig. 4 A to Fig. 4 G only illustrates the partial structurtes schematic diagram of a pixel region P of corresponding thin-film transistor array base-plate 100, the method for making of the thin-film transistor array base-plate 100 to the present embodiment is described in further detail below.
Step S1: please refer to Fig. 3 and 4A, utilize first optical cover process to form the first metal layer 111 on substrate 110, the first metal layer 111 is electrically connected with corresponding sweep trace.In the present embodiment, substrate 110 is such as transparency carrier 110, and the first metal layer 111 is such as grid.
Step S2: please refer to Fig. 4 B, substrate 110 is formed the first insulating protective layer 112, and covers the first metal layer 111.It is worth mentioning that, it is such as gate insulator that the first insulating protective layer 112 also covers sweep trace 101, first insulating protective layer 112 simultaneously.Utilize second optical cover process to form semiconductor layer 113 on the first insulating protective layer 112, and be positioned at the top of the first metal layer 111.Semiconductor layer 113 is such as amorphous silicon (a-Si) semiconductor layer 113, but not as limit.
Step S3: please refer to Fig. 4 C, utilize the 3rd road optical cover process to form pixel electrode 114 on the first insulating protective layer 112, pixel electrode 114 is positioned at each pixel region P.In the present embodiment, pixel electrode 114 is such as be made up of transparent conductive materials such as tin indium oxides (ITO, Indium Tin Oxide), but not as limit.Pixel electrode 114 be positioned at do not cover semiconductor layer 113 the first insulating protective layer 112 on and and semiconductor layer 113 interval arrange; that is; pixel electrode 114 in orthogonal projection and the first metal layer 111 of substrate 110 and semiconductor layer 113 not overlapping in the orthogonal projection of substrate 110, also namely pixel electrode 114 is positioned at the first metal layer 111 and semiconductor layer 113 outside the orthogonal projection region of substrate 110 in the orthogonal projection of substrate 110.
Step S4: please refer to Fig. 4 D, utilizes the 4th road optical cover process on semiconductor layer 113, form the second metal level 115, and the second metal level 115 is connected with pixel electrode 114.Second metal level 115 is such as source-drain electrode metal level, and the second metal level 115 comprises source electrode 115a and drain electrode 115b.Source electrode 115a is separate and directly contact with semiconductor layer 113 respectively and the semiconductor layer 113 of cover part with drain electrode 115b.In other words, a part of semiconductor layer 113 comes out between source electrode 115a and drain electrode 115b.In the present embodiment, source electrode 115a connects with corresponding data line 102, drain electrode 115b is the strip of bending and the pixel region P extended between adjacent two data lines 102 and pixel electrode 114 are electrically connected, namely drain one end of 115b is electrically connected with semiconductor layer 113, and the other end is electrically connected with pixel electrode 114.
Step S5: please refer to Fig. 4 E; after the second metal level 115 is formed; utilize the 5th road optical cover process to form the second insulating protective layer 116, and cover source electrode 115a, drain electrode 115b, from the semiconductor layer 113 of exposed portion between source electrode 115a and drain electrode 115b and data line 102 and sweep trace 101.That is, the second insulating protective layer 116 is except the pixel electrode 114 that do not cover the pixel region P limited between each adjacent two data lines 102 and between each adjacent two sweep traces 101 and the first insulation course 112, and other part all covers.In the present embodiment, the second insulating protective layer 116 is such as the passivation layer (PV, Passivation) formed by silicon nitride (SiNx), and the thickness of the second insulating protective layer 116 is
preferably, the thickness of the second insulating protective layer 116 is such as in the present embodiment
Step S6: please refer to Fig. 4 F; second insulating protective layer 116 is formed the 3rd insulating protective layer 117 that thickness is less than the second insulating protective layer 116, and the 3rd insulating protective layer 117 covers the second insulating protective layer 116 and the pixel electrode 114 that exposes from the second insulating protective layer 116 and the first insulation course 112.The 6th road optical cover process is utilized to form through hole (figure does not illustrate) for making periphery line in periphery, the viewing area of thin-film transistor array base-plate 100 in the 3rd insulating protective layer 117; this is well known to those skilled in the art technology, does not repeat them here.In the present embodiment, the 3rd insulating protective layer 117 is such as the passivation layer (PV, Passivation) formed by silicon nitride (SiNx), and the thickness of the 3rd insulating protective layer 117 is
preferably, the thickness of the 3rd insulating protective layer 117 is such as in the present embodiment
namely the thickness of the 3rd insulating protective layer 117 is less than the thickness of the second insulating protective layer 116.
Step S7: please refer to Fig. 4 G, utilizes the 7th road optical cover process to form public electrode 118 on the 3rd insulating protective layer 117.Public electrode 118 is positioned at the top of pixel electrode 114.Public electrode 118 is made up of transparent conductive materials such as tin indium oxides (ITO, Indium Tin Oxide), but not as limit.
As shown in Fig. 3 and Fig. 4 G, thin-film transistor array base-plate 100 comprises roughly along the multi-strip scanning line 101 of horizontal direction setting with roughly along a plurality of data lines 102 that vertical direction is arranged, and multi-strip scanning line 101 and a plurality of data lines 102 mutual intersection limit multiple pixel region P, sweep trace 101 and data line 102 crossover location place are provided with thin film transistor (TFT).The thin-film transistor array base-plate 100 of corresponding each pixel region P comprises substrate 110, the first metal layer 111, first insulating protective layer 112, semiconductor layer 113, pixel electrode 114, second metal level 115, second insulating protective layer 116, the 3rd insulating protective layer 117 and public electrode 118.The first metal layer 111 is formed on substrate 110.Substrate 110 is such as transparency carrier 110, and the first metal layer 111 is such as grid, and is electrically connected with corresponding sweep trace 101.First insulating protective layer 112 to be formed on substrate 110 and to cover the first metal layer 111.Semiconductor layer 113 to be formed on the first insulating protective layer 112 and to be positioned at above the first metal layer 111.Pixel electrode 114 be formed in do not cover semiconductor layer 113 the first insulating protective layer 112 on and and semiconductor layer 113 interval arrange.Second metal level 115 is formed on semiconductor layer 113, and the second metal level 115 is connected with pixel electrode 114.Second metal level 115 comprises source electrode 115a and drain electrode 115b.Source electrode 115a is separate and directly contact and the semiconductor layer 113 of cover part with semiconductor layer 113 respectively with drain electrode 115b.Source electrode 115a is electrically connected with corresponding data line 102, and drain electrode 115b is the strip of bending and the pixel region P between adjacent two data lines 102 being electrically connected with pixel electrode 114, also namely drain electrode 115b one end is electrically connected with semiconductor layer 113, and the other end is electrically connected with pixel electrode 114.Second insulating protective layer 116 to be formed on the second metal level 115 and to cover source electrode 115a, drain electrode 115b, from the semiconductor layer 113 of exposed portion between source electrode 115a and drain electrode 115b and data line 102 and sweep trace 101.3rd insulating protective layer 117 to be formed on the first insulating protective layer 112 and to cover the second insulating protective layer 116 and the pixel electrode 114 that exposes from the second insulating protective layer 116 and the first insulating protective layer 112.Public electrode 118 is formed on the 3rd insulating protective layer 117, and is positioned at the top of pixel electrode 114.Fig. 5 is the cross-sectional view of thin-film transistor array base-plate along the V-V line in Fig. 3 of present pre-ferred embodiments.As shown in Figure 5, the data line 102 of substrate 110 is coated with thickness is
the second insulating protective layer 116 and thickness be
the 3rd insulating protective layer 117, but be only coated with thickness in the pixel region P of data line 102 both sides and be
the 3rd insulating protective layer 117.Therefore, adjacent two pixel region P and the data line between two pixel region P 102 region can exist approximately
the section of thickness is poor.
Thin-film transistor array base-plate 100 of the present invention is applied to the broken section structural representation that liquid crystal indicator 300, Fig. 6 is the linear position data of liquid crystal indicator of the present invention.Please refer to Fig. 6, particularly, liquid crystal indicator 300 comprises thin-film transistor array base-plate 100 as infrabasal plate and and the upper substrate 310 (such as colored optical filtering substrates etc.) that is oppositely arranged of thin-film transistor array base-plate 100 and the liquid crystal layer 312 that is arranged between infrabasal plate (thin-film transistor array base-plate 100) and upper substrate 310.It is worth mentioning that, the side that upper substrate 310 is positioned at towards liquid crystal layer 312 is provided with the first alignment film 311, the side that thin-film transistor array base-plate 100 as infrabasal plate is positioned at towards liquid crystal layer 312 is provided with the second alignment film 119, namely the first alignment film 311 and the second alignment film 119 positioned opposite to each other, and be liquid crystal layer 312 between the first alignment film 311 and the second alignment film 119.As shown in Figure 6, adjacent two pixel region P and the data line between two pixel region P 102 region can exist approximately
the section of thickness is poor, so, when the 3rd insulating protective layer 117 arranges the second alignment film 119, cover same between data line 102 with adjacent two pixel region P there will be closely
the offset of thickness.Therefore, when the liquid crystal layer 312 between the upper substrate 310 and infrabasal plate of liquid crystal indicator 300 is positivity liquid crystal, the frictional direction of the second alignment film 119 and the length direction of data line 102 have 6 ~ 7 degree of angles.When liquid crystal indicator 300 shows, data line 102 both sides of its pixel region P can not produce dark-state light leakage phenomena.But when the liquid crystal layer 312 between the upper substrate 310 and infrabasal plate of liquid crystal indicator 300 is negative liquid crystal, the frictional direction of the second alignment film 119 and the length direction of data line 102 have 83 ~ 84 degree of angles.When liquid crystal indicator 300 shows, data line 102 both sides of its pixel region P can produce dark-state light leakage phenomena.Now need the method adopting light orientation, ultraviolet light is utilized to carry out contactless orientation to the second alignment film 119, thus avoid the problem of the liquid crystal arrangement orientation adopting negative liquid crystal layer to cause, thus data line 102 both sides of pixel region P are avoided to produce dark-state light leakage phenomena.Such as, LCD simulation softward (such as DIMOS.2D) can be adopted to detect the light leak situation of the pixel region P of data line 102 left and right sides.
Fig. 7 is the effect contrast figure of the liquid crystal indicator of the thin-film transistor array base-plate with present pre-ferred embodiments and the penetrance-voltage of existing liquid crystal indicator.Refer to Fig. 7, curve is 1. for having the penetrance of liquid crystal indicator 300 and the relation curve of voltage of the thin-film transistor array base-plate 100 of the present embodiment, and 2. curve makes the penetrance of the liquid crystal indicator of the thin-film transistor array base-plate of making and the relation curve of voltage for having existing six road light shields, and 3. curve makes the penetrance of the liquid crystal indicator of the thin-film transistor array base-plate of making and the relation curve of voltage for having existing seven road light shields.As shown in Figure 7, penetrance increases with voltage and increases gradually and slowly tend towards stability, and in same electrical pressure, the liquid crystal indicator 300 with the thin-film transistor array base-plate 100 of the present embodiment has higher penetrance.Fig. 8 is the effect contrast figure of the liquid crystal indicator of the thin-film transistor array base-plate with present pre-ferred embodiments and the penetrance-time of existing liquid crystal indicator.Refer to Fig. 8, curve is 1. for having the penetrance of liquid crystal indicator 300 and the relation curve of time of the thin-film transistor array base-plate 100 of the present embodiment, and 2. curve makes the penetrance of the liquid crystal indicator of the thin-film transistor array base-plate of making and the relation curve of time for having existing six road light shields.And 3. curve makes the penetrance of the liquid crystal indicator of the thin-film transistor array base-plate of making and the relation curve of time for having existing seven road light shields.As shown in Figure 8, pass in time, curve 1., 3. 2. curve show Similar trend with curve, from 20ms, penetrance increases fast and reaches stationary value, this stationary value continues for some time rear decline, and 1. curve reflects that the penetrance of the liquid crystal indicator 300 of the thin-film transistor array base-plate 100 with the present embodiment is higher.Under saturation voltage, the aperture opening ratio (AR) with the liquid crystal indicator 300 of thin-film transistor array base-plate 100 of the present invention is 49.92%, penetrance (Tr) is 3.85%, load (Cdate) is 60.5, response time (RT) is 33.96, the aperture opening ratio (AR) that existing six road light shields make the liquid crystal indicator of the thin-film transistor array base-plate of making is 49.92%, penetrance (Tr) is 3.69%, load (Cdate) is 70.32, response time (RT) is 38.79, the aperture opening ratio (AR) that existing seven road light shields make the liquid crystal indicator of the thin-film transistor array base-plate of making is 44.98%, penetrance (Tr) is 3.52%, load (Cdate) is 60.5, response time (RT) is 32.95.Therefore, under same pixel area size (as 20 μm × 60 μm), identical box thick (as 3.2 μm), identical liquid crystal, compared with the liquid crystal indicator 300 with thin-film transistor array base-plate 100 of the present invention makes the liquid crystal indicator of the thin-film transistor array base-plate made from existing six road light shields, improve penetrance and reduce load and the response time of liquid crystal indicator 300 of liquid crystal indicator 300 of the present invention.Particularly, the penetrance of liquid crystal indicator 300 of the present invention improves 4.34%, and load reduction 13.96%, the response time reduces 12.45%.Compared with the liquid crystal indicator 300 with thin-film transistor array base-plate 100 of the present invention makes the liquid crystal indicator of the thin-film transistor array base-plate made from existing seven road light shields, liquid crystal indicator 300 of the present invention improves aperture opening ratio and penetrance, and reduces the response time.Particularly, the penetrance of liquid crystal indicator 300 of the present invention improves 9.38%, and aperture opening ratio improves 10.98%.Compared with the liquid crystal indicator 300 with thin-film transistor array base-plate 100 of the present invention makes the liquid crystal indicator of the thin-film transistor array base-plate made from existing six road light shields, owing to only there is thickness between the pixel electrode 114 of thin-film transistor array base-plate 100 of the present invention and public electrode 118 be
the 3rd insulating protective layer 117, therefore, between the pixel electrode 114 of liquid crystal indicator 300 of the present invention and public electrode 118, more existing liquid crystal indicator can produce larger electric field, the response time is reduced, and improves penetrance.And interval second insulating protective layer 116 and the 3rd insulating protective layer 117 between the data line 102 of liquid crystal indicator 300 of the present invention and public electrode 118; therefore distant between data line 102 and public electrode 118; the stray capacitance that data line 102 is produced is less, because this reducing the load of liquid crystal indicator 300.Compare the liquid crystal indicator that existing seven road light shields make the thin-film transistor array base-plate of making, the drain electrode 115b with the second metal level 115 of the liquid crystal indicator 300 of thin-film transistor array base-plate 100 of the present invention is the strip of bending, without the need to being designed to larger contact area, therefore, transmission region area in pixel region P in thin-film transistor array base-plate 100 increases, and the aperture opening ratio of the liquid crystal indicator 300 with thin-film transistor array base-plate 100 and penetrance are got a promotion.
Thin-film transistor array base-plate of the present invention 100 and have the liquid crystal indicator 300 of thin-film transistor array base-plate 100, its thin-film transistor array base-plate 100 is coated with thickness along the length direction of data line 102 and is
the second insulating protective layer 116 and thickness be
the 3rd insulating protective layer 117 altogether two-layer protective seam, effectively prevent thin-film transistor array base-plate 100 when manufacturing foreign object to the scratch of data line 102.And the second insulating protective layer 116 and the 3rd insulating protective layer 117 add the distance between data line 102 and public electrode 118, the stray capacitance that data line 102 is produced reduces, thus reduces load, reduces power consumption.And owing to only there is thickness between the pixel electrode 114 of thin-film transistor array base-plate 100 and public electrode 118 be
the 3rd insulating protective layer 117; namely pixel electrode 114 and public electrode 118 are at a distance of nearer; therefore; larger electric field can be produced between pixel electrode 114 and public electrode 118; reduce the response time of the liquid crystal indicator 300 with thin-film transistor array base-plate 100, and improve penetrance simultaneously.In addition, the drain electrode 115b of the second metal level 115 is the strip of bending, without the need to being designed to larger contact area, therefore, transmission region area in pixel region P in thin-film transistor array base-plate 100 increases, namely increase the aperture opening ratio of thin-film transistor array base-plate 100, and improve penetrance.
Below the preferred embodiment of the present invention is described in detail by reference to the accompanying drawings; but the present invention is not limited to the detail in above-mentioned embodiment; within the scope of technical conceive of the present invention; can carry out multiple simple variant to technical scheme of the present invention, these simple variant all belong to protection scope of the present invention.Each concrete technical characteristic described in above-mentioned embodiment, in reconcilable situation, can be combined by any suitable mode.In order to avoid unnecessary repetition, the present invention illustrates no longer separately to various possible array mode.
Claims (10)
1. a thin-film transistor array base-plate, it a plurality of data lines comprising substrate, multi-strip scanning line is on the substrate set and is arranged on above this multi-strip scanning line, this multi-strip scanning line and this plurality of data lines are mutually intersected and are limited multiple pixel region, it is characterized in that, this thin-film transistor array base-plate also comprises:
The first metal layer, is formed on the substrate, and connects with this corresponding sweep trace;
First insulating protective layer, is formed on the substrate and covers this first metal layer and this multi-strip scanning line;
Semiconductor layer, to be formed on this first insulating protective layer and to be positioned at above this first metal layer;
Pixel electrode, to be formed on this first insulating protective layer and to be positioned at respectively this pixel region;
Second metal level, is formed on this semiconductor layer, and this second metal level comprises source electrode and drain electrode, and this source electrode connects with this corresponding data line, and this drain electrode connects with this corresponding pixel electrode;
Second insulating protective layer, be formed on this second metal level, this second insulating protective layer also covers respectively this data line and respectively this sweep trace simultaneously, and this pixel electrode respectively in this pixel region is not covered by this second insulating protective layer;
3rd insulating protective layer, is formed on this second insulating protective layer, and covers this pixel electrode respectively in this pixel region; And
Public electrode, is formed on the 3rd insulating protective layer.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, this drain electrode is the strip of bending, and one end of this drain electrode is connected with this semiconductor layer, and the other end of this drain electrode is directly connected with this pixel electrode.
3. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, the thickness of the 3rd insulating protective layer is less than the thickness of this second insulating protective layer.
4. thin-film transistor array base-plate as claimed in claim 3, it is characterized in that, the thickness of this second insulating protective layer is
the thickness of the 3rd insulating protective layer is
5. thin-film transistor array base-plate as claimed in claim 1, is characterized in that, this second insulating protective layer also covers this source electrode, this drain electrode and from this semiconductor layer exposed between this source electrode and this drain electrode further.
6. a liquid crystal indicator, is characterized in that, comprises the thin-film transistor array base-plate as described in any one of Claims 1 to 5.
7. liquid crystal indicator as claimed in claim 6, it is characterized in that, this liquid crystal indicator comprises colored filter substrate that this thin-film transistor array base-plate and this thin-film transistor array base-plate be oppositely arranged, be arranged on liquid crystal layer between this thin-film transistor array base-plate and this colored filter substrate.
8. a method for making for thin-film transistor array base-plate, is characterized in that, comprising:
Form the first metal layer and multi-strip scanning line at substrate, this first metal layer connects with corresponding sweep trace;
Form the first insulating protective layer, and cover this first metal layer and this multi-strip scanning line, and form semiconductor layer on this first insulating protective layer, this semiconductor layer is positioned at above this first metal layer;
This first insulating protective layer forms pixel electrode;
This semiconductor layer is formed the second metal level and a plurality of data lines, this multi-strip scanning line and this plurality of data lines are mutually intersected and are limited multiple pixel region, this pixel electrode is positioned at respectively this pixel region, this second metal level comprises source electrode and drain electrode, this source electrode connects with this corresponding data line, and drain electrode connects with this corresponding pixel electrode;
This second metal level forms the second insulating protective layer, and this second insulating protective layer also covers respectively this data line and respectively this sweep trace simultaneously, and this pixel electrode respectively in this pixel region is not covered by this second insulating protective layer;
This second insulating protective layer forms the 3rd insulating protective layer, and covers this pixel electrode respectively in this pixel region; And
3rd insulating protective layer forms public electrode.
9. the method for making of thin-film transistor array base-plate as claimed in claim 8; it is characterized in that; be included in further and the 3rd insulating protective layer form alignment film and covers the 3rd insulating protective layer and this public electrode, this alignment film adopts ultraviolet light to carry out orientation.
10. the method for making of thin-film transistor array base-plate as claimed in claim 8, it is characterized in that, the thickness of the 3rd insulating protective layer is less than the thickness of this second insulating protective layer.
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