CN106061126B - 柔性电路的制造方法、柔性电路及含该柔性电路的智能卡 - Google Patents

柔性电路的制造方法、柔性电路及含该柔性电路的智能卡 Download PDF

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CN106061126B
CN106061126B CN201610321611.5A CN201610321611A CN106061126B CN 106061126 B CN106061126 B CN 106061126B CN 201610321611 A CN201610321611 A CN 201610321611A CN 106061126 B CN106061126 B CN 106061126B
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dielectric layer
electric conductor
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C·洛朗斯德洛佩斯
S·迪厄-戈蒙
N·阿尔齐纳
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Linxens Holding SAS
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Abstract

本发明涉及柔性电路的制造方法。该制造方法包括提供电导体片(11)和介电层(50)。该制造方法还包括使介电层(50)直接接触电导体片(11)并层压它们。介电层(50)包括预浸料坯。因此电导体片(11)可在没有另外的粘结剂层的帮助下层压并粘附结合在介电层上。本发明还涉及用于智能卡的柔性电路和包含这种柔性电路的智能卡模块,该电路用所述方法制造。

Description

柔性电路的制造方法、柔性电路及含该柔性电路的智能卡
技术领域
本发明涉及柔性印刷电路领域,该柔性印刷电路可例如用于生产用于智能卡、RFID天线、发光二极管保持装置等的电子模块。
背景技术
下面通过以智能卡的电子模块为示例来说明本发明,但是换到柔性印刷电路的其它应用也是很容易的,尤其是如上面提到的那些应用。
智能卡对公众来说是众所周知的,其可用于多种应用中:信用卡、移动电话的SIM卡、交通卡、身份证等。
如图1中所示,智能卡一般包括刚性载体1,刚性载体1由例如PVC、PVC/ABS或聚碳酸酯的塑料制成,其构成卡的大部分,并且在刚性载体内结合有单独制作的电子模块2。该电子模块2包含通常是柔性的印刷电路3,印刷电路3装配有电子芯片100(集成电路)和传送装置,传送装置将数据从芯片向读卡器装置(读取)传送或从该装置向卡传送(写入)。这些传送数据的装置可以是“接触式”装置、“非接触式”装置或将前述两种装置组合的所谓“双式”装置。在“接触式”或“双式”智能卡中,连接器5包含接触垫15,接触垫15电连接到芯片100并与卡载体1的表面齐平,用于通过电接触与读卡器装置连接。
在现有技术中,模块通常由介电衬底形成,介电衬底的至少一个侧面上覆盖有电导体片,电导体片由金属制成,所述金属例如为铜、钢或铝或这些金属中的一种的合金。在该电导体片内形成有形成电接触垫的导电迹线。现有技术中使用的介电衬底通常由复合物(环氧玻璃)或塑料(PET、PEN、聚酰亚胺等)形成。为了保持与制造该电子模块所用的卷对卷或辊对辊方法兼容的柔性,这种类型的介电衬底通常是薄的(其厚度例如是约100μm)。
因而这种类型的柔性电路的制造方法例如包含:
—提供电导体片,其从而具有第一和第二主侧面;
—提供介电层,该介电层因而也具有第一和第二主侧面;以及
—层压所述电导体片和所述介电层。
电导体片通常通过预先涂覆在介电层上的粘结剂薄层粘附结合到介电层,所述粘结剂一般是热固性的(但可选的,其可是热熔的)和电绝缘的(其厚度例如是约20μm)。
发明内容
本发明的一个目的是简化这种类型的方法。
为了这个目的,提供了一种如前面提到的制造方法,进一步包含:在层压电导体片和介电层前,形成贯穿介电层的至少一个连接井(connection well)或孔的穿孔步骤。在已经层压了电导体片和介电层后,从而电导体片在至少一个连接井的底部处形成连接区域。此外,使用由预浸料坯构成的介电层。由此,可在介电层的第一侧直接接触电导体片的第一侧的同时实现层压电导体片和介电层的步骤。换句话说,表述“直接接触”在本文中意味着电导体片与介电层层压,两者之间没有任何其它中间层,并且尤其是在他们之间没有另外的粘结剂层。
通过这种配置,能够去除现有制造方法中使用的给介电层涂覆粘结剂的步骤。从而这种配置使得这种类型的方法更加经济。
本文中,预浸料坯是包含浸渍有热固性的(即可热固化的)树脂(也称作基体)的加强件(网、编织物、玻璃纤维)的半成品。树脂必须是热固化的以获得最终产品。
形成贯穿介电层的至少一个连接井的穿孔步骤在层压电导体片和介电层的步骤前执行,使得可使用经济、快速以及机械方式(如冲孔)来进行该穿孔。由于连接井通常具有约600至800μm的直径,因此对预浸料坯的树脂来说重要的是不流进井的底部、在电导体的表面上方。特别是由于这个原因,用还不稳定(例如因为还没有固化)并因此可能明显流动的介电衬底来代替现有技术中的热稳定的介电衬底(即在这种类型方法的常规操作温度下和一般低于300℃下是热稳定的)是非显而易见的。具体而言,需要防止预浸料坯的树脂覆盖井底部的导电区域并防止其危及后续的良好连接。因此选择预浸料坯使得根据标准IPC-TM-650 2.3.17.2测量的其流动性保持小于或等于0.7mm。通常,能够通过增加树脂的粘性(例如将填料加入该树脂或通过预固化树脂)来限制树脂的流动。但是,一方面树脂不足够粘且流动太大,但能粘附到电导体片上,另一方面树脂不流动(“不流动”树脂)但是在执行该方法要求的温度(低于220℃)和压力(2至6巴)下没有需求的粘附特性,在这两方面之间存在折衷。
可选的,上面的方法进一步包含彼此独立或其全部或部分结合考虑的下面的特征中的一个或者其它:
—预浸料坯包含树脂浸渍的加强件;
—该方法包含在层压电导体片和介电层步骤后固化树脂的步骤;
—从包含环氧树脂和不饱和聚酯树脂的列表中选择树脂;
—从编织纤维的织物、非编织纤维的织物、玻璃纤维、聚酯纤维、碳纤维和聚芳酰胺纤维中选择加强件;
—在80℃和200℃之间的温度并优选在100℃和150℃之间的温度下执行层压电导体片和介电层的步骤;该温度适于层压步骤的执行模式;例如,用卷对卷或辊对辊执行层压步骤,并且介电层(预浸料坯)在与电导体片层压之前在自身也被加热的辊下进行预加热;在这种情况下,辊、电导体片和介电层间的接触时间是非常短的;
—在2和6巴的压力下执行电导体片和介电层的层压步骤,特别是用卷对卷或辊对辊执行层压步骤;以及
—在介电层的第一侧上层压第一电导体片并且在介电层的第二侧上层压第二电导体片后,执行穿孔出至少一个连接井的步骤。
根据另一方面,本发明是通过上述方法获得的柔性电路并且其包含:
—具有第一和第二侧的介电层,该介电层包含预浸料坯;
—电导体片,其具有第一和第二侧,至少部分地覆盖介电层,介电层的第一侧直接接触电导体片的第一侧;和
—贯穿所述介电层的至少一个连接井,电导体片在至少一个连接井的底部处形成连接区域。
根据又一方面,本发明是包含卡体和位于卡体内的腔的智能卡,腔内放置有包含如上所述的柔性电路的电子模块,柔性电路包含固定到卡体的区域,例如用热熔粘结剂固定。
附图说明
在阅读详细说明和所附附图后,本发明的其它特征和优点将变得显而易见,在附图中:
图1以透视图示意性示出了用于接收柔性电路的智能卡;
图2a至2i示意性示出了制造印刷电路和插入该印刷电路的典型方法的各个步骤;以及
图3示意性示出了图2a至2i中示出的方法的步骤2h的一个变形。
具体实施方式
下面描述根据本发明的制造柔性电路的典型方法。该方法涉及智能卡领域,但是如已经指出的,很容易从本文描述的这些换到其它领域(RFID天线、LED等)中的应用。
如图1中所示,智能卡1包含模块2。模块2包含装配有连接器5的柔性电路3和芯片100。模块2通常以独立元件的形式形成,并插入卡1的腔4内。
因此柔性电路3包含具有多个触点15的连接器5,多个触点15连接到芯片100。柔性电路3从其正面6(接触面)显示(顶部)。也示出了其背面7(底部)。因而所示的柔性电路3对应用于“接触式”卡的单面柔性电路。但是,对于例如“双式”卡的双面柔性电路也同样适用。
图2a至2i示意性显示出根据本发明的制造柔性电路3的典型方法的各个步骤。
该方法包含提供(图2a)包含电介质的衬底50。该电介质由预浸料坯构成。该预浸料坯由环氧树脂浸渍的纤维材料构成。所述纤维材料例如是编织的玻璃纤维的织物。所述玻璃纤维织物根据国际分类号例如是1080型,但是它可以更厚。
衬底50的厚度大于50μm并优选大于75μm。例如,所述厚度包含在90和120μm之间。
构成衬底50的预浸料坯是“低流动”型。例如其根据标准IPC-TM-650 2.3.17.2测量的流动性小于或等于0.7mm。这种类型的预浸料坯是例如由Elite 公司出售。
然后对衬底50穿孔以形成连接井9、10(图2b),连接井的直径例如包含在300μm和1000μm之间。作为变形例(未示出),除了连接井9、10以外,还可对衬底穿孔以形成随后将芯片100容纳进其中的存储部。为了避免所述穿孔步骤连续地产生缺陷(例如与沉积在衬底50上的颗粒相关的额外厚度),尤其是在层压电导体片11期间,使用“无尘”品质的预浸料坯。这样的品质也使得在不损坏穿孔周围材料(见下面)的情况下能够获得更高的穿孔品质,损坏穿孔周围材料会在随后的光刻、蚀刻或电沉积(例如通过浸渍液在树脂和纤维之间的渗透)步骤中产生缺陷。
在接下来的步骤中,层压衬底50与电导体片11。所述导体片11例如是铜片(但是其也可包括钢片或铝片或铜、钢和铝这些金属中的一种的合金片)。片具有例如约18μm或35μm的厚度。所述层压步骤在高于预浸料坯的热熔温度以上的温度下执行。超过所述热熔温度,预浸料坯变得发粘。预浸料坯的热熔温度例如包含在100和150℃之间。
将导体片11层压在衬底50上使用的压力例如包含在2和6巴之间。
在所述步骤后,为了固定预浸料坯的结构,在固化温度范围中包含的温度下固化预浸料坯,固化温度范围取决于树脂特性。例如是180℃。在固化后,预浸料坯足够稳定以经受下面的步骤,而不会有明显的退化。
然后在导电片11的自由面上层压光刻胶膜12(图2d)。接着,通过掩模曝光所述光刻胶膜12(图2e),以形成用于电路的图案并形成柔性印刷电路。在未被光刻胶膜12保护的区域内化学蚀刻导电层11前,化学显影未曝光的光刻胶膜12(图2f)。然后溶解(剥离)曝光区域的光刻胶膜12,且通过在一个或多个步骤中的电镀而金属化在蚀刻导电层11后获得的迹线和接触区,以形成例如镍层13和金或铂或银层14(图2g)。
上面描述的方法的特定步骤是针对生产智能卡的模块2的,但是像层压衬底50和电导体片11的步骤,以及后续的蚀刻或金属化步骤,当然也可用于其它应用中。
这样制造的柔性电路3可用于将芯片100连接到触点15并以各种微电子装配技术中形成电子模块2。
因而图2h示意性示出了最后步骤,该步骤中芯片100使用例如用粘结剂粘附结合到衬底50。芯片100粘附结合到背面7并通过由直径25μm的金制成的连接引线102而连接到柔性电路的正面6,然后用封装树脂103保护芯片和引线。
可替换的,如图3所示,“倒装芯片”技术容许芯片100粘附结合到衬底50的背面7。然后芯片100通过位于芯片100下的导电凸块104而连接到柔性电路的正面6。因而模块2包含通过位于连接井9内的导电凸块104而直接电连接到触点15的芯片100。可选择的,芯片100也被封装。
然后将电子模块2(例如图2h和3中示出的那些电子模块)插入腔4内。模块2可通过热熔粘结剂16而紧固在腔4内。
当然能够通过在对应图2c的步骤的同时或之前或之后在衬底50上层压热的第二导体片(由铜或其它合金形成)以制造双面结构。例如,在图2a示出的步骤前,将第一导体片层压在预浸料坯上。然后,包含预浸料坯和所述第一导体片的复合物被穿孔,如在图2b中显示的步骤中那样。接着,这样穿孔后的复合物接收第二导体片,第二导体片层压在预浸料坯的还没有接收第一导体片的一侧上。对于层压第一和第二导体片,用预浸料坯的热熔粘附性质将它们固定到衬底50。但是,要注意的是,在双面衬底(即在每一面都具有导体片)的情况下,如果在比层压第一导体片的更高温度下执行层压第二导体片,那么流动性甚至会更高,并因此甚至引起比在制造单面衬底(即在单个面上具有导体片)的情况下更加严重的问题。固化后,接着与上面描述的那些类似的光刻和蚀刻步骤使得电路(导电迹线、触点、连接垫、天线等)被限定在两个面中的每个面上。
可替换的,也能够通过预浸料坯衬底50的热熔粘附特性在一面、在另一面或在两个面上层压和直接粘附结合在导体片上预切割的电路(引线框架技术),代替上面描述的光刻和蚀刻技术。
在所有上面提到的情况中,为了固化预浸料坯,需要在层压步骤后执行合适的热处理。例如,固化步骤在180℃下执行数小时(例如一个或两个小时的平稳状态以及温度上的向上和向下倾斜)。
如果需要通过上面描述的方法或其变形获得电路的配置和多功能性,那么可金属化穿过衬底50的至少部分连接井9、10。具体而言,采用上面指出的“无尘”品质的预浸料坯,能够获得洁净边缘的穿孔切割,而没有纤维延伸超过100μm,例如伸入用于连接引线102的焊接的穿孔内。
上面描述的方法及其变形的一个优点在于这样的事实:它们可用电介质带或导体带缠绕在其上的辊或卷轴辊对辊或卷对卷执行。在这种情况下预浸料坯的抗拉强度参数的值是关键。例如这些参数具有下述值:
—纵向杨氏模量(从一个辊或卷轴到另一辊或卷轴的运转方向)高于或等于3千兆帕;
—断裂时的伸长率高于或等于1%(具有例如最大10%);以及
—屈服强度大于或等于50MPa。

Claims (11)

1.一种制造柔性印刷电路(3)的方法,包括:
—提供具有第一面和第二面的电导体片(11);
—提供具有第一面和第二面的介电层(50);
—贯穿所述介电层穿孔形成至少一个连接井;以及
—在穿孔形成至少一个连接井后,使所述电导体片(11)与所述介电层(50)层压,所述电导体片(11)在至少一个连接井的底部处形成连接区域;
其中,
—所述介电层包含预浸料坯,所述预浸料坯包含树脂浸渍的加强件;
—穿孔形成至少一个连接井的步骤在使所述介电层(50)与所述电导体片(11)的第一面层压前执行;
—使所述电导体片(11)与所述介电层(50)层压的步骤在所述介电层(50)的第一面直接接触所述电导体片(11)的第一面的同时执行;
—并且,其特征在于,所述预浸料坯具有的根据标准IPC-TM-650 2.3.17.2测量的流动性低于或等于0.7mm。
2.根据权利要求1的方法,其特征在于,在80和200℃之间的温度下并且在2和6巴的压力下连续地进行使所述电导体片(11)与所述介电层(50)层压的步骤。
3.根据前述权利要求中的一个的方法,其特征在于,在使所述电导体片(11)与所述介电层(50)层压的步骤后执行固化树脂步骤。
4.根据权利要求1或2所述的方法,其特征在于,所述树脂选自包含环氧树脂和不饱和聚酯树脂的列表。
5.根据权利要求1或2所述的方法,其特征在于,所述加强件选自编织纤维的织物、非编织纤维的织物、玻璃纤维、聚酯纤维、碳纤维和聚芳酰胺纤维。
6.根据权利要求1或2所述的方法,其特征在于,所述预浸料坯具有“无尘”品质。
7.根据权利要求1或2所述的方法,其特征在于,穿孔形成至少一个连接井的步骤在使第一电导体片层压在所述介电层(50)的第一面上后执行,并且其中,使第二电导体片层压在所述介电层(50)的第二面上。
8.一种柔性印刷电路(3),包含:
—具有第一面和第二面的介电层(50);
—电导体片(11),其具有第一面和第二面,至少部分地覆盖所述介电层(50);以及
—贯穿所述介电层的至少一个连接井,所述电导体片(11)在至少一个连接井的底部处形成连接区域;
其中,所述介电层由预浸料坯构成,所述预浸料坯包含树脂浸渍的加强件,并且所述介电层(50)的第一面与所述电导体片(11)的第一面进行直接接触,其特征在于,所述预浸料坯具有的根据标准IPC-TM-650 2.3.17.2测量的流动性低于或等于0.7mm。
9.根据权利要求8所述的柔性印刷电路,其特征在于,所述树脂选自包含环氧树脂和不饱和聚酯树脂的列表。
10.根据权利要求8或9所述的柔性印刷电路,其特征在于,所述加强件选自编织纤维的织物、非编织纤维的织物、玻璃纤维、聚酯纤维、碳纤维和聚芳酰胺纤维。
11.一种智能卡,其包含卡体(1)和在所述卡体内的腔(4),并且在所述腔内放置有包含根据权利要求8至10中的一个所述的柔性印刷电路(3)的电子模块(2),所述柔性印刷电路(3)包含固定到所述卡体(1)的区域。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798014A (en) * 1995-02-02 1998-08-25 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
KR20140001547A (ko) * 2012-06-27 2014-01-07 엘지이노텍 주식회사 스마트 ic용 인쇄회로기판 및 그 제조방법

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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798014A (en) * 1995-02-02 1998-08-25 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
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