CN1060603C

CN1060603C - Single steady signal generating device

Info

Publication number: CN1060603C
Application number: CN95116245A
Authority: CN
Inventors: 吴宗训
Original assignee: Acer Computer Co Ltd
Current assignee: BenQ Corp
Priority date: 1995-09-14
Filing date: 1995-09-14
Publication date: 2001-01-10
Anticipated expiration: 2015-09-14
Also published as: CN1145552A

Abstract

The present invention relates to a monostable signal generating device which comprises a trigger, an oscillation circuit, a counter and a comparison circuit, wherein the trigger has one output end for outputting the monostable signal; the trigger starts a first edge change of the monostable signal because of a trigger signal, and starts a second edge change of the monostable signal because of a clear signal; the oscillation circuit has one output end for generating a pulse train because of the first edge change of the monostable signal; the counter counts the pulse numbers of the pulse train; the comparison circuit compares the count value of the counter and a preset value for selectivity generating the clear signal to the trigger.

Description

One single steady signal generating device

The relevant signal generation device of the present invention, You Zhiyi can produce one monostable (monostable) signal generation device of desired pulse width signal.

In field of electronic systems, for example in the monitor control system, often need the circuit that can produce certain pulse width signal, this certain pulse width signal is for other circuit utilizations.

The technology of knowing, be to adopt a resistance-capacitance (RC) circuit to cooperate a monostable multivibrator (monostable multivibrator), as IC numbering 74LS221 wafer, so that triggering signal when coming in, produces the signal of a desired pulse width at the monostable multivibrator output.The pulsewidth of signal is that the RC constant by the resistance-capacitance circuit is determined.But this kind simulates mode, do not allow to be easy to real rule in the digital integrated circuit on the one hand, and the mode that on the other hand, simulates (Analog) also is vulnerable to the interference of noise.In addition, just known to the applicant, relevant technology still comprises United States Patent (USP) 4,598,412,4,994,687,5,059,812 and 5,422, and No. 585.

In view of this, in order to solve above-mentioned the problems of the prior art, the object of the present invention is to provide a kind of signal generation device, device produces the signal of a predetermined pulse width thus, that is a monostable (monostable) signal.

Single steady signal generating device of the present invention comprises:

One trigger (flip flop), its tool one output are for the described single steady signal of output, and this trigger in response to a triggering signal, starts one first edge variation of single steady signal, and, in response to a clear signal, one second edge variation of starting single steady signal;

One oscillating circuit, its tool one output is in response to first edge variation of single steady signal, for producing a train of impulses in its output;

One counter is counted the pulse number of this train of impulses;

One comparison circuit, it is the count value and a preset value of counter relatively, and selective property ground produces described clear signal to trigger.

Purpose of the present invention, feature and advantage will be elaborated in conjunction with the embodiments with reference to the accompanying drawings.

Brief Description Of Drawings:

Fig. 1 is the basic circuit block diagram of single steady signal generating device of the present invention.

As shown in Figure 1, the present invention comprises a trigger 11, an oscillating circuit 12, a counter 14 and a comparison circuit 13.

Trigger 11 in response to a triggering signal 111, starts one first edge variation of single steady signal 112 at output (Q).

Oscillating circuit 12 input single steady signals 112, and, produce a train of impulses (pulse train) 121 in response to described first edge variation.

The umber of pulse of 14 paired pulses series 121 of counter is counted.And when one first edge variation of single steady signal 112 took place, counter 14 promptly was reset (reset) and makes zero.

Comparison circuit 13 is made comparisons a preset value of counter 14 output valves and a register 16 outputs, produces a clear signal 131 when both are equal and removes to remove trigger 11.Briefly, in response to clear signal 131, trigger 11 starts one second edge variation of single steady signal 112.

The frequency values of the train of impulses 121 is determined by the time delay that element in the oscillating circuit 12 causes.After oscillating circuit 12 decisions, the pulse duration of single steady signal 112 (pulsewidth) is determined by the storage values in the register 16.Change the parameter value in the register 16; The pulsewidth of single steady signal 112 promptly changes on demand.

One embodiment of oscillating circuit 12 have one with non-(NAND) door 20,1 first inverter (INVERTER) 21 and one second inverter 22.

NAND gate 20 has one first input, one second input and an output.First input end receives single steady signal 112, the second inputs and then links with the output of oscillating circuit 12.

The output that first inverter 21 has an input and NAND gate 20 links, and tool one output.

The output that second inverter 22 has an input and first inverter 21 links, and tool one output constitutes the output of oscillating circuit 12.

Trigger 11 has a clock input (C) and receives described triggering signal 111, have a data terminal (D) and link with a reference voltage (+5), and one removes end input clear signal 131.Except D flip-flop can be used as trigger 11, the trigger of other patterns also can be used, as long as interlock circuit is revised around it, also attainable cost is invented the purpose desiring to reach.

Claims

1, a single steady signal generating device comprises:

One trigger, its tool one output are for the described single steady signal of output, and this trigger in response to a triggering signal, starts one first edge variation of single steady signal, and, in response to a clear signal, one second edge variation of starting single steady signal;

One counter is counted the pulse number of this train of impulses;

2, device according to claim 1, wherein, it has a clock input for receiving described triggering signal described trigger, and tool one data terminal and a reference voltage link, and one is removed termination and is received described clear signal.

3, device according to claim 1, wherein, described oscillating circuit comprises:

One NAND gate, tool one first input end, one second input and an output, first input end receives single steady signal, and the output of second input and oscillating circuit links;

One first inverter, the output of tool one input and NAND gate is connected, the one output;

One second inverter, the output of tool one input and first inverter links, and the one output constitutes the output of oscillating circuit.