US4408333A - Data acquisition circuit - Google Patents
Data acquisition circuit Download PDFInfo
- Publication number
- US4408333A US4408333A US06/338,995 US33899582A US4408333A US 4408333 A US4408333 A US 4408333A US 33899582 A US33899582 A US 33899582A US 4408333 A US4408333 A US 4408333A
- Authority
- US
- United States
- Prior art keywords
- pulse
- clock pulse
- clock
- data acquisition
- conditioning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003750 conditioning effect Effects 0.000 claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
- 230000007704 transition Effects 0.000 claims description 10
- 230000003111 delayed effect Effects 0.000 claims description 5
- 102100038026 DNA fragmentation factor subunit alpha Human genes 0.000 description 4
- 101000950906 Homo sapiens DNA fragmentation factor subunit alpha Proteins 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 3
- 101150110298 INV1 gene Proteins 0.000 description 3
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 3
- 101150070189 CIN3 gene Proteins 0.000 description 1
- 102100038023 DNA fragmentation factor subunit beta Human genes 0.000 description 1
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 1
- 101100277639 Homo sapiens DFFB gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Definitions
- the present invention relates to a data acquisition circuit.
- the data is transmitted at a rate lower than the system's normal transmission rate whenever such reduced transmission rate is justified by the use of low cost narrow band transmission channels and/or by the reduction of error rate.
- the reduction of transmission rate is effected by reducing the transmission rate of the information data to one half of the system's nominal rate while transmitting the clock pulses at the nominal rate.
- the clock pulses are frequency divided by a factor of two in a divide-by-two frequency divider to generate data acquisition pulses.
- the data acquisition pulse tends to occur at different timings depending on the operating states of the frequency divider at the time the clock pulse is applied thereto, so that data acquisition is not always correctly phased.
- the data acquisition circuit comprises means responsive to a synchronization pulse and a clock pulse which is received at a rate twice as high as the transmission rate of information data, for generating a conditioning pulse of which the duration is twice as large as the duration of the clock pulse and the leading edge occurs at a time delayed by the duration of the clock pulse, and a divide-by-2 frequency divider responsive to the conditioning pulse and the clock pulse for generating a data acquisition pulse occurring at one half the rate of the clock pulse. Since the time of occurrence and duration of the conditioning pulse are determined by the received clock and synchronization pulses, the operating state of the frequency divider is predeterminable and therefore the data acquisition pulse occurs in a predetermined phase relationship with the information data.
- the conditioning pulse generating means comprises a first bistable device having a first input responsive to the synchronization pulse and a second input terminal responsive to the clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of the clock pulse.
- a second bistable device is provided having a first input terminal connected to the output of the first bistable device and a second input terminal responsive to the clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of the clock pulse, and coincidence gate means for combining the outputs of the first and second bistable devices to generate the conditioning pulse.
- the divide-by-2 frequency divider comprises a bistable device arranged to respond to the leading edge transition of the clock pulse by switching its bistable condition to a first binary state in the presence of the conditioning pulse and arranged to reverse the bistable condition in response to the leading edge transition of the clock pulses which subsequently occur in the absence of the conditioning pulse.
- FIG. 1 is a block diagram of the data acquisition circuit of the invention.
- FIGS. 2a and 2i are illustrations of waveforms which are useful for describing the operation of the FIG. 1 embodiment.
- FIG. 1 there is shown a preferred embodiment of a data acquisition circuit of the invention which is adapted to receive a clock pulse Pc at terminal 1, a data synchronization pulse Ps at terminal 2 as well as information data Sd.
- the information data is transmitted at one half the system's normal transmission rate while the clock pulse is transmitted at the nominal rate.
- the circuit comprises a first D-type flip-flop DFF1 having its clock input CK connected via an inverter INV1 to the terminal 1 to receive square wave clock pulses Pc (FIG. 2b).
- the data input D of the flip-flop DFF1 is connected to the terminal 2 to receive the synchronization pulse Ps (FIG. 2c).
- the Q output of the flip-flop DFF1 switches to the logical level of the data input terminal D in response to the trailing edge of the clock pulse Pc due to the inversion of clock pulse by inverter INV1, thereby generating a pulse P1 (FIG. 2d) having the duration of synchronization pulse Ps but delayed with respect to Ps by the duration of clock pulse Pc.
- the output of the first flip-flop DFF1 is coupled to the data input of a second D-type flip-flop DFF2 having its clock input CK connected to the output of the inverter INV1 to generate a pulse P2 (FIG. 2e) having the duration of synchronization pulse Ps but delayed with respect thereto by the pulse spacing of clock pulse Pc.
- the pulses P1 and P2, of which the latter is inverted by inverter INV2, are coupled to an AND gate 3 to generate a positive-going conditioning pulse P3 (FIG. 2f) having the duration equal to the pulse spacing of clock pulse Pc but delayed with respect to Ps by the duration of clock pulse Pc.
- the conditioning pulse P3 is inverted by an inverter INV3 providing a negative-going pulse P4 (FIG. 2g) to the J input of a J-K flip-flop J-K FF of which the K input is coupled to the ground.
- This flip-flop is conditioned by the pulse applied to its J input and operates as a frequency divider that divides the frequency of the clock pulses Pc by a factor of 2.
- the clock input CK of the J-K flip-flop is coupled to the clock input terminal 1.
- the Q output of the J-K flip-flop thus goes low in the presence of a low level input to the J terminal in response to the leading edge of a clock pulse Pc.
- the J-K flip-flop reverses its Q output state in response to the leading edge transition of each succeeding clock pulse Pc, thus generating a train of pulses P5 (FIG. 2h) at the Q output of the J-K flip-flop.
- the pulses P5 are reversed in polarity by an inverter INV4 as shown at P6 in FIG. 2i and fed to an output terminal 4 to serve as data acquisition pulses.
Abstract
Description
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981003104U JPS6347105Y2 (en) | 1981-01-13 | 1981-01-13 | |
JP56-3104[U] | 1981-01-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
US4408333A true US4408333A (en) | 1983-10-04 |
Family
ID=11548035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/338,995 Expired - Lifetime US4408333A (en) | 1981-01-13 | 1982-01-12 | Data acquisition circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US4408333A (en) |
JP (1) | JPS6347105Y2 (en) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4514719A (en) * | 1981-10-15 | 1985-04-30 | Matsushita Electric Works, Ltd. | Data transmission system utilizing power line of 3-phase alternating current |
US4580243A (en) * | 1983-09-14 | 1986-04-01 | Gte Automatic Electric Incorporated | Circuit for duplex synchronization of asynchronous signals |
US4631484A (en) * | 1984-12-21 | 1986-12-23 | Allied Corporation | Multimode pulse generator |
US4633487A (en) * | 1985-01-17 | 1986-12-30 | Itt Corporation | Automatic phasing apparatus for synchronizing digital data and timing signals |
US4656649A (en) * | 1984-12-18 | 1987-04-07 | Nec Corporation | Clock frequency divider circuit |
US4669080A (en) * | 1984-05-11 | 1987-05-26 | Aveneau Andre A | Synchronizing circuit in a plesiochronous digital signal multiplexer |
US4758737A (en) * | 1985-02-13 | 1988-07-19 | Sharp Kabushiki Kaisha | Clock generator circuit |
US4774422A (en) * | 1987-05-01 | 1988-09-27 | Digital Equipment Corporation | High speed low pin count bus interface |
US4829515A (en) * | 1987-05-01 | 1989-05-09 | Digital Equipment Corporation | High performance low pin count bus interface |
US4928290A (en) * | 1988-11-07 | 1990-05-22 | Ncr Corporation | Circuit for stable synchronization of asynchronous data |
US4973860A (en) * | 1989-05-02 | 1990-11-27 | Ast Research Inc. | Circuit for synchronizing an asynchronous input signal to a high frequency clock |
US5014270A (en) * | 1989-05-03 | 1991-05-07 | Sat (Societe Anonyme De Telecommunications) | Device for synchronizing a pseudo-binary signal with a regenerated clock signal having phase jumps |
EP0433120A1 (en) * | 1989-11-16 | 1991-06-19 | Fujitsu Limited | PLL synthesizer circuit |
EP0447344A2 (en) * | 1990-03-12 | 1991-09-18 | International Business Machines Corporation | Receiver synchronizing device in a serial data communication system |
US5126587A (en) * | 1990-03-26 | 1992-06-30 | Siemens Aktiengesellschaft | Synchronization circuit configuration |
US5189379A (en) * | 1989-11-16 | 1993-02-23 | Fujitsu Limited | Pulse width detecting circuit and PLL synthesizer circuit using the same |
US5225723A (en) * | 1990-05-24 | 1993-07-06 | Apple Computer, Inc. | Circuitry for the timing data output enable pulses |
US5920213A (en) * | 1997-03-28 | 1999-07-06 | Cypress Semiconductor Corp. | Pulse discriminating clock synchronizer for logic derived clock signals for a programmable device |
US6055285A (en) * | 1997-11-17 | 2000-04-25 | Qlogic Corporation | Synchronization circuit for transferring pointer between two asynchronous circuits |
US6084447A (en) * | 1997-03-28 | 2000-07-04 | Cypress Semiconductor Corp. | Pulse discriminating clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device |
US6163550A (en) * | 1997-11-17 | 2000-12-19 | Qlogic Corporation | State dependent synchronization circuit which synchronizes leading and trailing edges of asynchronous input pulses |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0618365B2 (en) * | 1988-01-21 | 1994-03-09 | 日本電気株式会社 | Timing method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3471790A (en) * | 1965-04-23 | 1969-10-07 | Philips Corp | Device for synchronizing pulses |
US3820030A (en) * | 1973-09-05 | 1974-06-25 | Gte Information Syst Inc | Pulse sampling and synchronization circuit |
US4222009A (en) * | 1978-11-02 | 1980-09-09 | Sperry Corporation | Phase lock loop preconditioning circuit |
-
1981
- 1981-01-13 JP JP1981003104U patent/JPS6347105Y2/ja not_active Expired
-
1982
- 1982-01-12 US US06/338,995 patent/US4408333A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3471790A (en) * | 1965-04-23 | 1969-10-07 | Philips Corp | Device for synchronizing pulses |
US3820030A (en) * | 1973-09-05 | 1974-06-25 | Gte Information Syst Inc | Pulse sampling and synchronization circuit |
US4222009A (en) * | 1978-11-02 | 1980-09-09 | Sperry Corporation | Phase lock loop preconditioning circuit |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4514719A (en) * | 1981-10-15 | 1985-04-30 | Matsushita Electric Works, Ltd. | Data transmission system utilizing power line of 3-phase alternating current |
US4580243A (en) * | 1983-09-14 | 1986-04-01 | Gte Automatic Electric Incorporated | Circuit for duplex synchronization of asynchronous signals |
US4669080A (en) * | 1984-05-11 | 1987-05-26 | Aveneau Andre A | Synchronizing circuit in a plesiochronous digital signal multiplexer |
US4656649A (en) * | 1984-12-18 | 1987-04-07 | Nec Corporation | Clock frequency divider circuit |
US4631484A (en) * | 1984-12-21 | 1986-12-23 | Allied Corporation | Multimode pulse generator |
US4633487A (en) * | 1985-01-17 | 1986-12-30 | Itt Corporation | Automatic phasing apparatus for synchronizing digital data and timing signals |
US4758737A (en) * | 1985-02-13 | 1988-07-19 | Sharp Kabushiki Kaisha | Clock generator circuit |
US4774422A (en) * | 1987-05-01 | 1988-09-27 | Digital Equipment Corporation | High speed low pin count bus interface |
US4829515A (en) * | 1987-05-01 | 1989-05-09 | Digital Equipment Corporation | High performance low pin count bus interface |
US4928290A (en) * | 1988-11-07 | 1990-05-22 | Ncr Corporation | Circuit for stable synchronization of asynchronous data |
US4973860A (en) * | 1989-05-02 | 1990-11-27 | Ast Research Inc. | Circuit for synchronizing an asynchronous input signal to a high frequency clock |
US5014270A (en) * | 1989-05-03 | 1991-05-07 | Sat (Societe Anonyme De Telecommunications) | Device for synchronizing a pseudo-binary signal with a regenerated clock signal having phase jumps |
EP0433120A1 (en) * | 1989-11-16 | 1991-06-19 | Fujitsu Limited | PLL synthesizer circuit |
US5189379A (en) * | 1989-11-16 | 1993-02-23 | Fujitsu Limited | Pulse width detecting circuit and PLL synthesizer circuit using the same |
EP0447344A2 (en) * | 1990-03-12 | 1991-09-18 | International Business Machines Corporation | Receiver synchronizing device in a serial data communication system |
EP0447344A3 (en) * | 1990-03-12 | 1992-09-16 | International Business Machines Corporation | Receiver synchronizing device in a serial data communication system |
US5126587A (en) * | 1990-03-26 | 1992-06-30 | Siemens Aktiengesellschaft | Synchronization circuit configuration |
US5225723A (en) * | 1990-05-24 | 1993-07-06 | Apple Computer, Inc. | Circuitry for the timing data output enable pulses |
US5920213A (en) * | 1997-03-28 | 1999-07-06 | Cypress Semiconductor Corp. | Pulse discriminating clock synchronizer for logic derived clock signals for a programmable device |
US6084447A (en) * | 1997-03-28 | 2000-07-04 | Cypress Semiconductor Corp. | Pulse discriminating clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device |
US6055285A (en) * | 1997-11-17 | 2000-04-25 | Qlogic Corporation | Synchronization circuit for transferring pointer between two asynchronous circuits |
US6163550A (en) * | 1997-11-17 | 2000-12-19 | Qlogic Corporation | State dependent synchronization circuit which synchronizes leading and trailing edges of asynchronous input pulses |
Also Published As
Publication number | Publication date |
---|---|
JPS57118449U (en) | 1982-07-22 |
JPS6347105Y2 (en) | 1988-12-06 |
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