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US4408333A - Data acquisition circuit - Google Patents

Data acquisition circuit Download PDF

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Publication number
US4408333A
US4408333A US06338995 US33899582A US4408333A US 4408333 A US4408333 A US 4408333A US 06338995 US06338995 US 06338995 US 33899582 A US33899582 A US 33899582A US 4408333 A US4408333 A US 4408333A
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Prior art keywords
pulse
clock
data
input
acquisition
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Expired - Lifetime
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US06338995
Inventor
Yasuhiko Fujii
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Victor Co of Japan Ltd
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Victor Co of Japan Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines

Abstract

A data acquisition circuit is adapted to receive information data, a synchronization pulse and a clock pulse which is transmitted at twice as high as the transmission rate of the information data. The clock and synchronization pulses are processed into a conditioning pulse for a divide-by-two frequency divider so that it conditions the divider to respond to the clock pulse by generating a data acquisition pulse at a frequency corresponding to the transmission rate of the information data in a correct phase relationship therewith.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a data acquisition circuit.

In data processing systems which are interconnected by telecommunication channels, the data is transmitted at a rate lower than the system's normal transmission rate whenever such reduced transmission rate is justified by the use of low cost narrow band transmission channels and/or by the reduction of error rate.

Since the information data is conventionally transmitted with data synchronization and clock pulses in a predetermined phase relationship for data acquisition purposes at the receiving end of the system, the reduction of transmission rate is effected by reducing the transmission rate of the information data to one half of the system's nominal rate while transmitting the clock pulses at the nominal rate. At the receiving end, the clock pulses are frequency divided by a factor of two in a divide-by-two frequency divider to generate data acquisition pulses. However, the data acquisition pulse tends to occur at different timings depending on the operating states of the frequency divider at the time the clock pulse is applied thereto, so that data acquisition is not always correctly phased.

SUMMARY OF THE INVENTION

According to the invention, the data acquisition circuit comprises means responsive to a synchronization pulse and a clock pulse which is received at a rate twice as high as the transmission rate of information data, for generating a conditioning pulse of which the duration is twice as large as the duration of the clock pulse and the leading edge occurs at a time delayed by the duration of the clock pulse, and a divide-by-2 frequency divider responsive to the conditioning pulse and the clock pulse for generating a data acquisition pulse occurring at one half the rate of the clock pulse. Since the time of occurrence and duration of the conditioning pulse are determined by the received clock and synchronization pulses, the operating state of the frequency divider is predeterminable and therefore the data acquisition pulse occurs in a predetermined phase relationship with the information data.

Preferably, the conditioning pulse generating means comprises a first bistable device having a first input responsive to the synchronization pulse and a second input terminal responsive to the clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of the clock pulse. A second bistable device is provided having a first input terminal connected to the output of the first bistable device and a second input terminal responsive to the clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of the clock pulse, and coincidence gate means for combining the outputs of the first and second bistable devices to generate the conditioning pulse. In a further preferred embodiment, the divide-by-2 frequency divider comprises a bistable device arranged to respond to the leading edge transition of the clock pulse by switching its bistable condition to a first binary state in the presence of the conditioning pulse and arranged to reverse the bistable condition in response to the leading edge transition of the clock pulses which subsequently occur in the absence of the conditioning pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of the data acquisition circuit of the invention; and

FIGS. 2a and 2i are illustrations of waveforms which are useful for describing the operation of the FIG. 1 embodiment.

DETAILED DESCRIPTION

Referring to FIG. 1, there is shown a preferred embodiment of a data acquisition circuit of the invention which is adapted to receive a clock pulse Pc at terminal 1, a data synchronization pulse Ps at terminal 2 as well as information data Sd. The information data is transmitted at one half the system's normal transmission rate while the clock pulse is transmitted at the nominal rate. The circuit comprises a first D-type flip-flop DFF1 having its clock input CK connected via an inverter INV1 to the terminal 1 to receive square wave clock pulses Pc (FIG. 2b). The data input D of the flip-flop DFF1 is connected to the terminal 2 to receive the synchronization pulse Ps (FIG. 2c). The Q output of the flip-flop DFF1 switches to the logical level of the data input terminal D in response to the trailing edge of the clock pulse Pc due to the inversion of clock pulse by inverter INV1, thereby generating a pulse P1 (FIG. 2d) having the duration of synchronization pulse Ps but delayed with respect to Ps by the duration of clock pulse Pc. The output of the first flip-flop DFF1 is coupled to the data input of a second D-type flip-flop DFF2 having its clock input CK connected to the output of the inverter INV1 to generate a pulse P2 (FIG. 2e) having the duration of synchronization pulse Ps but delayed with respect thereto by the pulse spacing of clock pulse Pc.

The pulses P1 and P2, of which the latter is inverted by inverter INV2, are coupled to an AND gate 3 to generate a positive-going conditioning pulse P3 (FIG. 2f) having the duration equal to the pulse spacing of clock pulse Pc but delayed with respect to Ps by the duration of clock pulse Pc. The conditioning pulse P3 is inverted by an inverter INV3 providing a negative-going pulse P4 (FIG. 2g) to the J input of a J-K flip-flop J-K FF of which the K input is coupled to the ground. This flip-flop is conditioned by the pulse applied to its J input and operates as a frequency divider that divides the frequency of the clock pulses Pc by a factor of 2. The clock input CK of the J-K flip-flop is coupled to the clock input terminal 1. The Q output of the J-K flip-flop thus goes low in the presence of a low level input to the J terminal in response to the leading edge of a clock pulse Pc. In the presence of a high level input to the J terminal that prevails after the trailing edge of pulse P4 the J-K flip-flop reverses its Q output state in response to the leading edge transition of each succeeding clock pulse Pc, thus generating a train of pulses P5 (FIG. 2h) at the Q output of the J-K flip-flop. The pulses P5 are reversed in polarity by an inverter INV4 as shown at P6 in FIG. 2i and fed to an output terminal 4 to serve as data acquisition pulses.

It is seen that the leading edge transition of the data acquisition pulse P6 occurs exactly in phase with the midpoint of information data Sd, FIG. 2a. Therefore, data acquisition can be effected with a high degree of precision not attainable with prior art data acquisition circuits.

Claims (3)

What is claimed is:
1. A data acquisition circuit adapted to receive information data, a synchronization pulse and a clock pulse, the clock pulse at a repetition rate twice as high as the transmission rate of said information data, said circuit comprising:
means responsive to said synchronization pulse and said clock pulse for generating a conditioning pulse of which the duration is twice as large as the duration of said clock pulse and the leading edge occurs at a time delayed from the synchronization pulse by the duration of said clock pulse; and
a divide-by-two frequency divider responsive to said conditioning pulse and said clock pulse for generating a data acquisition pulse occurring at one half the rate of said clock pulse.
2. A data acquisition circuit as claimed in claim 1, wherein said conditioning pulse generating means comprises a first bistable device having a first input responsive to said synchronization pulse and a second input terminal responsive to said clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of said clock pulse, a second bistable device having a first input terminal connected to the output of said first bistable device and a second input terminal responsive to said clock pulse and arranged to switch to the binary state of the first input terminal thereof in response to the trailing edge transition of said clock pulse, and coincidence gate means for combining the outputs of said first and second bistable devices to generate said conditioning pulse.
3. A data acquisition circuit as claimed in claim 1 or 2, wherein said divide-by-two frequency divider comprises a bistable device arranged to response to the leading edge transition of said clock pulse by switching its bistable condition to a first binary state in the presence of said conditioning pulse and arranged to reverse said bistable condition in response to the leading edge transition of said clock pulses which occur in the absence of said conditioning pulse.
US06338995 1981-01-13 1982-01-12 Data acquisition circuit Expired - Lifetime US4408333A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP310481U JPS6347105Y2 (en) 1981-01-13 1981-01-13
JP56-3104[U] 1981-01-13

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US4408333A true US4408333A (en) 1983-10-04

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US06338995 Expired - Lifetime US4408333A (en) 1981-01-13 1982-01-12 Data acquisition circuit

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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514719A (en) * 1981-10-15 1985-04-30 Matsushita Electric Works, Ltd. Data transmission system utilizing power line of 3-phase alternating current
US4580243A (en) * 1983-09-14 1986-04-01 Gte Automatic Electric Incorporated Circuit for duplex synchronization of asynchronous signals
US4631484A (en) * 1984-12-21 1986-12-23 Allied Corporation Multimode pulse generator
US4633487A (en) * 1985-01-17 1986-12-30 Itt Corporation Automatic phasing apparatus for synchronizing digital data and timing signals
US4656649A (en) * 1984-12-18 1987-04-07 Nec Corporation Clock frequency divider circuit
US4669080A (en) * 1984-05-11 1987-05-26 Aveneau Andre A Synchronizing circuit in a plesiochronous digital signal multiplexer
US4758737A (en) * 1985-02-13 1988-07-19 Sharp Kabushiki Kaisha Clock generator circuit
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
US4928290A (en) * 1988-11-07 1990-05-22 Ncr Corporation Circuit for stable synchronization of asynchronous data
US4973860A (en) * 1989-05-02 1990-11-27 Ast Research Inc. Circuit for synchronizing an asynchronous input signal to a high frequency clock
US5014270A (en) * 1989-05-03 1991-05-07 Sat (Societe Anonyme De Telecommunications) Device for synchronizing a pseudo-binary signal with a regenerated clock signal having phase jumps
EP0433120A1 (en) * 1989-11-16 1991-06-19 Fujitsu Limited PLL synthesizer circuit
EP0447344A2 (en) * 1990-03-12 1991-09-18 International Business Machines Corporation Receiver synchronizing device in a serial data communication system
US5126587A (en) * 1990-03-26 1992-06-30 Siemens Aktiengesellschaft Synchronization circuit configuration
US5189379A (en) * 1989-11-16 1993-02-23 Fujitsu Limited Pulse width detecting circuit and PLL synthesizer circuit using the same
US5225723A (en) * 1990-05-24 1993-07-06 Apple Computer, Inc. Circuitry for the timing data output enable pulses
US5920213A (en) * 1997-03-28 1999-07-06 Cypress Semiconductor Corp. Pulse discriminating clock synchronizer for logic derived clock signals for a programmable device
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6084447A (en) * 1997-03-28 2000-07-04 Cypress Semiconductor Corp. Pulse discriminating clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device
US6163550A (en) * 1997-11-17 2000-12-19 Qlogic Corporation State dependent synchronization circuit which synchronizes leading and trailing edges of asynchronous input pulses

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618365B2 (en) * 1988-01-21 1994-03-09 日本電気株式会社 Timing scheme

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3471790A (en) * 1965-04-23 1969-10-07 Philips Corp Device for synchronizing pulses
US3820030A (en) * 1973-09-05 1974-06-25 Gte Information Syst Inc Pulse sampling and synchronization circuit
US4222009A (en) * 1978-11-02 1980-09-09 Sperry Corporation Phase lock loop preconditioning circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3471790A (en) * 1965-04-23 1969-10-07 Philips Corp Device for synchronizing pulses
US3820030A (en) * 1973-09-05 1974-06-25 Gte Information Syst Inc Pulse sampling and synchronization circuit
US4222009A (en) * 1978-11-02 1980-09-09 Sperry Corporation Phase lock loop preconditioning circuit

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514719A (en) * 1981-10-15 1985-04-30 Matsushita Electric Works, Ltd. Data transmission system utilizing power line of 3-phase alternating current
US4580243A (en) * 1983-09-14 1986-04-01 Gte Automatic Electric Incorporated Circuit for duplex synchronization of asynchronous signals
US4669080A (en) * 1984-05-11 1987-05-26 Aveneau Andre A Synchronizing circuit in a plesiochronous digital signal multiplexer
US4656649A (en) * 1984-12-18 1987-04-07 Nec Corporation Clock frequency divider circuit
US4631484A (en) * 1984-12-21 1986-12-23 Allied Corporation Multimode pulse generator
US4633487A (en) * 1985-01-17 1986-12-30 Itt Corporation Automatic phasing apparatus for synchronizing digital data and timing signals
US4758737A (en) * 1985-02-13 1988-07-19 Sharp Kabushiki Kaisha Clock generator circuit
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
US4928290A (en) * 1988-11-07 1990-05-22 Ncr Corporation Circuit for stable synchronization of asynchronous data
US4973860A (en) * 1989-05-02 1990-11-27 Ast Research Inc. Circuit for synchronizing an asynchronous input signal to a high frequency clock
US5014270A (en) * 1989-05-03 1991-05-07 Sat (Societe Anonyme De Telecommunications) Device for synchronizing a pseudo-binary signal with a regenerated clock signal having phase jumps
EP0433120A1 (en) * 1989-11-16 1991-06-19 Fujitsu Limited PLL synthesizer circuit
US5189379A (en) * 1989-11-16 1993-02-23 Fujitsu Limited Pulse width detecting circuit and PLL synthesizer circuit using the same
EP0447344A2 (en) * 1990-03-12 1991-09-18 International Business Machines Corporation Receiver synchronizing device in a serial data communication system
EP0447344A3 (en) * 1990-03-12 1992-09-16 International Business Machines Corporation Receiver synchronizing device in a serial data communication system
US5126587A (en) * 1990-03-26 1992-06-30 Siemens Aktiengesellschaft Synchronization circuit configuration
US5225723A (en) * 1990-05-24 1993-07-06 Apple Computer, Inc. Circuitry for the timing data output enable pulses
US5920213A (en) * 1997-03-28 1999-07-06 Cypress Semiconductor Corp. Pulse discriminating clock synchronizer for logic derived clock signals for a programmable device
US6084447A (en) * 1997-03-28 2000-07-04 Cypress Semiconductor Corp. Pulse discriminating clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6163550A (en) * 1997-11-17 2000-12-19 Qlogic Corporation State dependent synchronization circuit which synchronizes leading and trailing edges of asynchronous input pulses

Also Published As

Publication number Publication date Type
JPS6347105Y2 (en) 1988-12-06 grant
JPS57118449U (en) 1982-07-22 application

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Owner name: VICTOR COMPANY OF JAPAN, LIMITED; 3-12, MORIYA-CHO

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