CN106059570A - System and method for combining and counting multiple irrelevant pulses - Google Patents
System and method for combining and counting multiple irrelevant pulses Download PDFInfo
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- CN106059570A CN106059570A CN201610556562.3A CN201610556562A CN106059570A CN 106059570 A CN106059570 A CN 106059570A CN 201610556562 A CN201610556562 A CN 201610556562A CN 106059570 A CN106059570 A CN 106059570A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
Abstract
The present invention discloses a system and a method for combining and counting multiple irrelevant pulses. The system includes n cascaded two-path irrelevant pulse combined circuits and a counter, wherein n is an integer and is greater than or equal to 2. Each two-path irrelevant pulse combined circuit is used for combining input two-path irrelevant pulses in a time-sharing manner. According to a cascading manner, a first pulse and a second pulse are input into the first two-path irrelevant pulse combined circuit, and a time-sharing combined pulse Uo1 is output; a time-sharing combined pulse Uo(I 1) output by a (i-1)th two-path irrelevant pulse combined circuit and a (i+1)th pulse are input into an ith two-path irrelevant pulse combined circuit, and a time-sharing combined pulse Uoi is output, wherein i is equal to 1, 2, and the like, n; and a time-sharing combined pulse Uon output by an nth two-path irrelevant pulse combined circuit is input into a counter clock end. The system has a simple circuit, low cost, and high reliability, and solves a problem of combining and counting of multiple irrelevant pulses.
Description
Technical field
The invention belongs to electronic technology field, relate to the application of Digital Electronic Technique and Analog Electronics Technique, particularly to
A kind of irrelevant pulse of multichannel merges number system and method.
Background technology
In product quantity statistics and demographics, it is frequently present of the problem that multichannel data merges.Existing method is first
Pulse to the output of each road sensor counts, more each circuit-switched data is passed through communication interface circuit with wired or wireless side
Formula is sent to an adder, central processing unit or computer and carries out summation statistics.Counting electricity is all used on each road of this method
Road, telecommunication circuit, display device so that systematic comparison is complicated.In the demographics in the most multi-door room, due to each
Enumeration data may be negative, needs to consider sign bit so that circuit is more complicated, and cost is high, and cost performance is low, and maintenance difficulties is big.
Obviously, the pulse of each road sensor output is mutually incoherent in time.The invention aims to provide
The irrelevant pulse of a kind of multichannel merges the ball bearing made method of counting, it is to avoid reuses counting circuit in number system, lead to
Letter circuit, display device etc., thus cost performance is greatly improved, significantly reduce maintenance difficulties.
Summary of the invention
Solved by the invention technical problem is that, for the defect of above-mentioned prior art, the present invention provides a kind of multichannel not
Coherent pulse merges number system and method, and circuit is simple, with low cost, and reliability is high, solves multichannel well irrelevant
The merging enumeration problem of pulse.
Technical scheme provided by the present invention is:
A kind of irrelevant pulse of multichannel merges number system, including n cascade two-way irrelevant pulse consolidation circuit with
One enumerator；N is integer, and n >=2；
Each two-way irrelevant pulse consolidation circuit merges for the two-way irrelevant pulse timesharing realizing input；
Cascade system is:
1st tunnel pulse and the 2nd tunnel pulse input the 1st two-way irrelevant pulse consolidation circuit, and output timesharing merges pulse
Uo1；
The timesharing of the i-th-1 two-way irrelevant pulse consolidation circuit output merges pulse Uo(i-1)Input with the pulse of i+1 road
I-th two-way irrelevant pulse consolidation circuit, output timesharing merges pulse Uoi；I=1,2 ..., n；
The timesharing of the n-th two-way irrelevant pulse consolidation circuit output merges pulse UonInput counter clock end.
Each two-way irrelevant pulse consolidation circuit all includes that time delay starting point auto-adjusting circuit, pulse sequence are more electric
Road, monostable flipflop, RC peaker, voltage comparator and pulse-combining circuit；
The irrelevant pulse of two-way that irrelevant for i-th two-way pulse consolidation circuit inputs is designated as Ua and Ub respectively；Ua and
Ub is sent to pulse sequence comparison circuit, time delay starting point auto-adjusting circuit and pulse-combining circuit simultaneously；Pulse sequence is more electric
Output signal U d on road and output signal U c of time delay starting point auto-adjusting circuit connect monostable flipflop respectively two are defeated
Enter end；Output signal U e of monostable flipflop is connected to the input of RC peaker, the output letter of described RC peaker
Number Uf is connected to the input of voltage comparator, and output signal U g of described voltage comparator is connected to described pulse combined electricity
Road, the output signal of described pulse-combining circuit is timesharing and merges pulse Uoi。
Described Ua and Ub is two incoherent positive burst pulses or negative burst pulse.
When Ua and Ub is two incoherent positive burst pulses, two-way irrelevant pulse consolidation circuit structure is:
Described time delay starting point auto-adjusting circuit includes nor gate U2A and diode D3；Two inputs of nor gate U2A
Connect Ua and Ub respectively；The outfan of nor gate U2A connects diode D3 negative electrode；
Described pulse sequence comparison circuit includes NAND gate U3A；Two inputs of NAND gate U3A connect respectively Ua and
Ub；
Described monostable flipflop includes LM555CM chip U1, resistance R1, electric capacity C1 and electric capacity C2；The discharge end of U1 and
Threshold value end [DIS end and THR end] is all connected with the anode of diode D3, and the triggering end [TRI end] of U1 connects the output of NAND gate U3A
End；Resistance R1 one end connects discharge end and the threshold value end of U1, and the other end connects power vd D；Electric capacity C1 one end connects the electric discharge of U1
End and threshold value end, the other end connects power supply ground；Electric capacity C2 one end connects the control power end [CON end] of U1, and the other end connects electricity
Seedbed；
Described RC peaker includes electric capacity C3, resistance R2, resistance R3 and diode D4；The one termination U1's of electric capacity C3 is defeated
Going out end, the other end is designated as junction point S, junction point S and meets power vd D through resistance R2；One end of resistance R3 and the negative electrode of diode D4
The other end of contact S the most in succession, resistance R3 and the anode of diode D4 all connect power supply ground；
Described voltage comparator includes LM393D chip U4A, resistance R4, resistance R5, electric capacity C4 and resistance R6；U4A is just
Meet power vd D to input through resistance R4, connect power supply ground through resistance R5；Electric capacity C4 is in parallel with resistance R5；The reverse input end of U4A
Contact S in succession；The outfan of U4A meets power vd D through resistance R6；
Described pulse-combining circuit includes diode D1, diode D2, diode D5 and resistance R7；
The anode of diode D1, diode D2 and diode D5 connects the outfan of Ua, Ub and U4A respectively；Resistance R7 one end
Connecing power supply ground, the other end is connected with the negative electrode of D1, D2 and D5, is output Uoi。
When Ua and Ub is two incoherent negative burst pulses, two-way irrelevant pulse consolidation circuit structure is:
Described time delay starting point auto-adjusting circuit includes and door U2A and diode D3；Two inputs difference with door U2A
Connect Ua and Ub；Diode D3 negative electrode it is connected with the outfan of door U2A；
Described pulse sequence comparison circuit includes or door U3A；Or two inputs of door U3A connect Ua and Ub respectively；
Described monostable flipflop includes LM555CM chip U1, resistance R1, electric capacity C1 and electric capacity C2；The discharge end of U1 and
Threshold value end is all connected with the anode of diode D3, and the end that triggers of U1 connects or the outfan of door U3A；Resistance R1 one end connects putting of U1
Electricity end and threshold value end, the other end connects power vd D；Electric capacity C1 one end connects discharge end and the threshold value end of U1, and the other end connects electricity
Seedbed；Electric capacity C2 one end connects the control power end of U1, and the other end connects power supply ground；
Described RC peaker includes electric capacity C3, resistance R2, resistance R3 and diode D4；The one termination U1's of electric capacity C3 is defeated
Going out end, the other end is designated as junction point S, junction point S and meets power vd D through resistance R2；One end of resistance R3 and the negative electrode of diode D4
The other end of contact S the most in succession, resistance R3 and the anode of diode D4 all connect power supply ground；
Described voltage comparator includes LM393D chip U4A, resistance R4, resistance R5, electric capacity C4 and resistance R6；U4A's is anti-
Meet power vd D to input through resistance R4, connect power supply ground through resistance R5；Electric capacity C4 is in parallel with resistance R4；The positive input of U4A
Contact S in succession；The outfan of U4A meets power vd D through resistance R6；
Described pulse-combining circuit includes diode D1, diode D2, diode D5 and resistance R7；
The negative electrode of diode D1, diode D2 and diode D5 connects the outfan of Ua, Ub and U4A respectively；Resistance R7 one end
Meeting power vd D, the other end is connected with the anode of D1, D2 and D5, is output Uoi。
A kind of irrelevant pulse of multichannel merges method of counting, and n two-way irrelevant pulse consolidation circuit cascade is realized n+1
The timesharing of the irrelevant pulse in road merges；Each two-way irrelevant pulse consolidation circuit is for realizing the irrelevant arteries and veins of two-way of input
Rush timesharing to merge；
The timesharing of the n-th two-way irrelevant pulse consolidation circuit output of cascade is merged pulse and is sent to the clock of enumerator
End, it is achieved the merging counting of the irrelevant pulse in n+1 road；
Described cascade system is:
1st tunnel pulse and the 2nd tunnel pulse input the 1st two-way irrelevant pulse consolidation circuit, and output timesharing merges pulse
Uo1；
The timesharing of the i-th-1 two-way irrelevant pulse consolidation circuit output merges pulse Uo(i-1)Input with the pulse of i+1 road
I-th two-way irrelevant pulse consolidation circuit, output timesharing merges pulse Uoi；I=1,2 ..., n.
The method of the two-way irrelevant pulse timesharing merging that i-th two-way irrelevant pulse consolidation circuit realizes input is:
The irrelevant pulse of two-way that irrelevant for i-th two-way pulse consolidation circuit inputs is designated as Ua and Ub respectively；Ua and
Ub is sent to pulse sequence comparison circuit, time delay starting point auto-adjusting circuit and pulse-combining circuit simultaneously；Pulse sequence is more electric
Output signal U d on road and output signal U c of time delay starting point auto-adjusting circuit connect two of monostable flipflop respectively and touch
Send out input；Output signal U e of monostable flipflop is connected to the input of RC peaker, described RC peaker defeated
Going out signal Uf and be connected to the input of voltage comparator, output signal U g of described voltage comparator is connected to described pulse combined
Circuit, the output signal of described pulse-combining circuit is timesharing and merges pulse Uoi。
Pulse Ua, Ub of the output of two-way sensor are the burst pulses that dutycycle is the least, are mutually incoherent in time.Cause
This merge counting need to consider Ua, Ub stagger the most completely, the completely overlapped or various situations such as partly overlap.To this end, will
Two-way irrelevant pulse Ua, Ub are sent to pulse sequence comparison circuit, time delay starting point auto-adjusting circuit and pulse combined electricity simultaneously
Road.Described pulse sequence comparison circuit output Ud and time delay starting point auto-adjusting circuit output Uc is all connected to monostable trigger
Device, described monostable flipflop output Ue is connected to RC peaker, and described RC peaker output Uf is connected to voltage ratio relatively
Device, described voltage comparator output Ug is connected to described pulse-combining circuit, described pulse-combining circuit output UoiIt is merging
Count pulse, the clock end being sent to enumerator achieves that merging counting.
When two-way irrelevant pulse Ua, Ub stagger the most completely, described pulse sequence comparison circuit no pulse is defeated
Going out, described monostable flipflop and voltage comparator do not overturn, and only Ua, Ub is directly sent to export after pulse-combining circuit merges
Two pulses.
When two-way irrelevant pulse Ua, Ub are the most completely overlapped or partly overlap, then pulse sequence comparison circuit
Export a pulse to sequentially pass through after monostable flipflop, RC peaker and voltage comparator carry out time delay shaping and be sent to pulse
Combinational circuit, the pulse merged with Ua, Ub is combined, thus also two pulses of output.
In order to ensure sequentially passing through the pulse after monostable flipflop, RC peaker and voltage comparator time delay shaping not
Can be the most overlapping with Ua, Ub, use time delay starting point auto-adjusting circuit just to start Time delay after Ua, Ub being detected,
Voltage comparator output Ug with Ua, Ub are staggered the most completely.
Beneficial effect:
The middle small scale integrated circuits such as present invention application logic gates, monostable flipflop, voltage comparator realize many
The irrelevant pulse in road merges counting, and circuit is simple, with low cost, and reliability is high, solves the irrelevant pulse of multichannel well
Merge enumeration problem.
The method of the invention solves prior art and repeats to use counting circuit, telecommunication circuit in multichannel data is added up
The defect that system complex, cost are high, maintenance difficulties is big is caused so that the closely merging of the irrelevant pulse of multichannel with display device
Counting circuit becomes simple and reliable, with low cost.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of two-way irrelevant pulse consolidation circuit.
Fig. 2 is the working waveform figure of two-way irrelevant pulse consolidation circuit.
Fig. 3 is the overall structure block diagram of the embodiment of the present invention.
Fig. 4 is the circuit diagram of the incoherent positive burst pulse consolidation circuit of two-way.
Fig. 5 is the circuit diagram of the incoherent negative burst pulse consolidation circuit of two-way.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in more detail.
The invention discloses a kind of irrelevant pulse of multichannel and merge number system and method, number system includes n cascade
Two-way irrelevant pulse consolidation circuit and an enumerator；N is integer, and n >=2；The irrelevant pulse of each two-way merges
Circuit merges for the two-way irrelevant pulse timesharing realizing input；
Cascade system is:
1st tunnel pulse and the 2nd tunnel pulse input the 1st two-way irrelevant pulse consolidation circuit, and output timesharing merges pulse
Uo1；
The timesharing of the i-th-1 two-way irrelevant pulse consolidation circuit output merges pulse Uo(i-1)Input with the pulse of i+1 road
I-th two-way irrelevant pulse consolidation circuit, output timesharing merges pulse Uoi；I=1,2 ..., n；
The timesharing of the n-th two-way irrelevant pulse consolidation circuit output merges pulse UonInput counter clock end.
As it is shown in figure 1, be the structured flowchart of two-way irrelevant pulse consolidation circuit, by time delay starting point auto-adjusting circuit 1,
Monostable flipflop 2, pulse-combining circuit 3, pulse sequence comparison circuit 4, RC peaker 5 and voltage comparator 6 form.Two
Road irrelevant pulse Ua, Ub are sent to pulse sequence comparison circuit 4, time delay starting point auto-adjusting circuit 1 and pulse combined electricity simultaneously
Road 3 input, pulse sequence comparison circuit 4 exports Ud and time delay starting point auto-adjusting circuit 1 exports Uc and is all connected to monostable
The triggering input of trigger 2, monostable flipflop 2 exports Ue and is connected to RC peaker 5 input, and RC peaker 5 is defeated
Going out Uf and be connected to voltage comparator 6 input, voltage comparator 6 exports Ug and is connected to pulse-combining circuit 3 input, pulse group
Close circuit 3 then Ua, Ub and Ug tri-road pulse signal be merged into one road pulse signal Uo1 output, the pulse number of Uo1 is
The summation of Ua, Ub pulse number.The clock end that Uo1 is sent to enumerator achieves that the merging counting of Ua, Ub.
Two-way irrelevant pulse Ua, Ub can be positive burst pulses, it is also possible to be negative burst pulse.
As in figure 2 it is shown, Ua, Ub are positive burst pulse, the most mutually incoherent, i.e. Ua, Ub in time may be the most wrong
Open, it is also possible to completely overlapped or partly overlap.When Ua, Ub stagger the most completely, pulse sequence comparison circuit 4 exports Ud
Be constantly in high level, i.e. no pulse output, monostable flipflop 2 is in stable state and does not overturns, and output Ue is low level, RC differential
Circuit 5 exports Uf and does not overturns without differentiated pulse, voltage comparator 6, output Ug be constantly in low level and without positive pulse, only
Ua, Ub are directly sent to pulse-combining circuit 3 input, export Uo1 and contain two pulses, by it after pulse-combining circuit 3 merges
It is sent to counter clock end can realize correctly counting.
When Ua, Ub are the most completely overlapped or partly overlap, then pulse sequence comparison circuit 4 exports Ud at Ua and Ub
Overlap during upset for low level, make monostable flipflop 2 enter temporary stable state, output Ue becomes high level, RC peaker 5
Output Uf occurs that forward differentiated pulse, voltage comparator 6 do not overturn, and output Ug is constantly in low level.But, at Ua and Ub
For between high period, it is low level that time delay starting point auto-adjusting circuit 1 exports Uc, makes the timing capacitor of monostable flipflop 2 also
Not starting to charge up, only after Ua and Ub high level pulse, Uc becomes high level, makes the timing capacitor of monostable flipflop 2
Starting to charge up, after certain time τ, monostable flipflop 2 returns to stable state, and output Ue is become low level, RC differential from high level
Circuit 5 exports Uf and negative sense differentiated pulse occurs, makes voltage comparator 6 occur upset to make output Ug a positive burst pulse occur,
Being sent to an input of pulse-combining circuit 3, the pulse merged with Ua, Ub is combined, so that Uo1 occurs
Two pulses, are sent to counter clock end and can realize correctly counting.
Special instruction, time delay starting point auto-adjusting circuit 1 exports Uc for controlling the timing capacitor in monostable flipflop 2
Charging starting point.As seen from Figure 2, the overlapping time of Ua with Ub is different, and it is low that time delay starting point auto-adjusting circuit 1 exports Uc
The time of level is different, then the charging starting point of the timing capacitor in monostable flipflop 2 is different so that at monostable flipflop 2
Time t in temporary stable stateWDifference, it is different that output Ue reverts to the low level time, so that RC peaker 5 exports Uf and occurs
The time of negative sense differentiated pulse is different, causes voltage comparator 6 to export Ug and the time of positive burst pulse occurs always at Ua, Ub height electricity
After flat pulse, it is ensured that Ug will not be overlapping with Ua, Ub in any case.
In sum, no matter irrelevant positive pulse Ua of two-way, Ub stagger or completely overlapped or part the most completely
Overlap, the pulse number of output Uo1 is always Ua, Ub pulse number sum.The clock end that Uo1 is sent to enumerator achieves that
The merging counting of Ua, Ub.
Fig. 3 is the overall structure block diagram of the embodiment of the present invention.By irrelevant to the 3rd tunnel irrelevant pulse Uc and the 1st two-way
The output Uo1 of pulse consolidation circuit [(1) # two-way irrelevant pulse consolidation circuit] is simultaneously entered the 2nd the irrelevant pulse of two-way
Consolidation circuit [(2) # two-way irrelevant pulse consolidation circuit] merges output Uo2 with regard to the irrelevant pulse in Ke Jiang tri-tunnel；By the 4th tunnel not
Coherent pulse Ud and the output Uo2 of the 2nd two-way irrelevant pulse consolidation circuit [(2) # two-way irrelevant pulse consolidation circuit]
It is simultaneously entered the 3rd two-way irrelevant pulse consolidation circuit [(3) # two-way irrelevant pulse consolidation circuit] with regard to Ke Jiang tetra-tunnel not phase
Dry pulse merges output Uo3；By that analogy, the (n+1)th tunnel irrelevant pulse Un+1 and the irrelevant pulse of (n-1) individual two-way are closed
And the output Uo (n-1) of circuit [(n-1) # two-way irrelevant pulse consolidation circuit] is simultaneously entered the n-th irrelevant pulse of two-way
Consolidation circuit [(n) # two-way irrelevant pulse consolidation circuit] merges output Uon with regard to the irrelevant pulse in Ke Jiang n+1 road；Uon is sent
Clock end toward enumerator achieves that the merging counting of the irrelevant pulse in n+1 road.
Fig. 4 is the circuit diagram of the incoherent positive burst pulse consolidation circuit of two-way.Ua, Ub are two the narrowest incoherent arteries and veins
Punching；Two inputs of nor gate U2A connect Ua, Ub, and it is automatic that the outfan of U2A connects diode D3 negative electrode composition time delay starting point
Regulation circuit 1, D3 anode is connected to discharge end and the threshold value end [DIS end and THR end] of LM555CM chip U1；NAND gate U3A structure
Becoming pulse sequence comparison circuit 4, two inputs of U3A connect Ua, Ub, and the outfan of U3A is connected to the triggering end [TRI of U1
End]；U1, resistance R1, electric capacity C1 and C2 constitute monostable flipflop 2, and U1 outfan connects one end of electric capacity C3；Electric capacity C3, electricity
Resistance R2, resistance R3, diode D4 constitute RC peaker 5；LM393D chip U4A, resistance R4, resistance R5, electric capacity C4, resistance R6
Constitute voltage comparator 6；Diode D1, diode D2, diode D5, resistance R7 connect the diode OR gate circuit of composition and constitute
Pulse-combining circuit 3, the negative electrode of D1, D2, D5 is output U with the connection end of R7o1。
When Ua, Ub stagger the most completely, NAND gate U3A output Ud is constantly in high level, i.e. no pulse output,
U1 is in stable state and does not overturns, and U1 output Ue is low level, junction point output Uf=Vcc/2 (without differentiated pulse) of C3 Yu R3, U4A
"-" terminal voltage higher than "+" terminal voltage, U4A output Ug is constantly in low level and without positive pulse, only Ua, Ub are respectively through D1, D2
Arrive outfan Uo1 (containing two pulses), be sent to counter clock end and can realize correctly counting.
When Ua, Ub are the most completely overlapped or partly overlap, then NAND gate U3A output Ud is at the overlap period of Ua and Ub
Between upset for low level, make U1 enter temporary stable state, U1 output Ue becomes high level, C3 Yu R2, the junction point output Uf appearance of R3
Forward differentiated pulse, the "-" end of U4A higher than "+" end, U4A does not overturns, U4A output Ug be constantly in low level.But,
Ua and Ub is between high period, U2A output low level, and D3 turns on, and makes timing capacitor C1 short circuit external for U1 not start to fill
Electricity；Only after Ua and Ub high level, U2A outfan becomes high level, and D3 ends, and timing capacitor C1 making U1 external starts
Charging, after certain time τ, U1 returns to stable state, and U1 outfan Ue is become low level, C3 Yu R2, the junction point of R3 from high level
There is negative sense differentiated pulse in output Uf, make the "-" end of U4A less than "+" end and overturning, make U4A outfan Ug occur one
Positive burst pulse, arrives outfan Uo1 through D5, and Ua, Ub also obtains a pulse through D1, D2, R7 or computing, therefore make
There are two pulses in Uo1, is sent to counter clock end and can realize correctly counting.
As it is shown in figure 5, be the circuit diagram of the incoherent negative burst pulse consolidation circuit of two-way.When Ua, Ub be two irrelevant
Negative burst pulse time, then can use and door constitute time delay starting point auto-adjusting circuit 1, use or door constitute pulse sequence more electric
Road 4, uses diode AND gate circuit to constitute pulse-combining circuit 3, can realize the merging output of the irrelevant pulse of two-way equally.
Above in conjunction with accompanying drawing, embodiments of the present invention are explained in detail, but the present invention is not limited to above-mentioned enforcement
Mode, in the ken that those of ordinary skill in the art are possessed, it is also possible on the premise of without departing from present inventive concept
Various changes can be made.
Claims (7)
1. the irrelevant pulse of multichannel merges number system, it is characterised in that include that n the irrelevant pulse of the two-way cascaded is closed
And circuit and an enumerator；N is integer, and n >=2；Each two-way irrelevant pulse consolidation circuit is for realizing input
Two-way irrelevant pulse timesharing merges；
Cascade system is:
1st tunnel pulse and the 2nd tunnel pulse input the 1st two-way irrelevant pulse consolidation circuit, and output timesharing merges pulse Uo1；
The timesharing of the i-th-1 two-way irrelevant pulse consolidation circuit output merges pulse Uo(i-1)I-th is inputted with the pulse of i+1 road
Individual two-way irrelevant pulse consolidation circuit, output timesharing merges pulse Uoi；I=1,2 ..., n；
The timesharing of the n-th two-way irrelevant pulse consolidation circuit output merges pulse UonInput counter clock end.
The irrelevant pulse of multichannel the most according to claim 1 merges number system, it is characterised in that each two-way not phase
Dry pulse consolidation circuit all includes time delay starting point auto-adjusting circuit, pulse sequence comparison circuit, monostable flipflop, RC differential
Circuit, voltage comparator and pulse-combining circuit；
The irrelevant pulse of two-way that irrelevant for i-th two-way pulse consolidation circuit inputs is designated as Ua and Ub respectively；
Two inputs of described pulse sequence comparison circuit, time delay starting point auto-adjusting circuit and pulse-combining circuit are respectively
It is connected with Ua and Ub；Output signal U d of pulse sequence comparison circuit and output signal U c of time delay starting point auto-adjusting circuit are divided
Do not connect two inputs of monostable flipflop；Output signal U e of monostable flipflop is connected to the input of RC peaker
End；Output signal U f of described RC peaker connects the input of voltage comparator；The output signal of described voltage comparator
Ug is connected to the 3rd input of described pulse-combining circuit；The output signal of described pulse-combining circuit is timesharing and merges arteries and veins
Rush Uoi。
The irrelevant pulse of multichannel the most according to claim 2 merges number system, it is characterised in that when Ua and Ub is two
During incoherent positive burst pulse, the structure of two-way irrelevant pulse consolidation circuit is:
Described time delay starting point auto-adjusting circuit includes nor gate U2A and diode D3；Two inputs of nor gate U2A are respectively
Connect Ua and Ub；The outfan of nor gate U2A connects diode D3 negative electrode；
Described pulse sequence comparison circuit includes NAND gate U3A；Two inputs of NAND gate U3A connect Ua and Ub respectively；
Described monostable flipflop includes LM555CM chip U1, resistance R1, electric capacity C1 and electric capacity C2；The discharge end of U1 and threshold value
End is all connected with the anode of diode D3, and the end that triggers of U1 connects the outfan of NAND gate U3A；Resistance R1 one end connects the electric discharge of U1
End and threshold value end, the other end connects power vd D；Electric capacity C1 one end connects discharge end and the threshold value end of U1, and the other end connects power supply
Ground；Electric capacity C2 one end connects the control power end of U1, and the other end connects power supply ground；
Described RC peaker includes electric capacity C3, resistance R2, resistance R3 and diode D4；The output of the one termination U1 of electric capacity C3
End, the other end is designated as junction point S, junction point S and meets power vd D through resistance R2；One end of resistance R3 and the negative electrode of diode D4 are equal
The other end of contact S in succession, resistance R3 and the anode of diode D4 all connect power supply ground；
Described voltage comparator includes LM393D chip U4A, resistance R4, resistance R5, electric capacity C4 and resistance R6；The forward of U4A is defeated
Enter end and meet power vd D through resistance R4, connect power supply ground through resistance R5；Electric capacity C4 is in parallel with resistance R5；The reverse input end of U4A is in succession
Contact S；The outfan of U4A meets power vd D through resistance R6；
Described pulse-combining circuit includes diode D1, diode D2, diode D5 and resistance R7；
The anode of diode D1, diode D2 and diode D5 connects the outfan of Ua, Ub and U4A respectively；Resistance R7 mono-terminates electricity
Seedbed, the other end is connected with the negative electrode of D1, D2 and D5, is output Uoi。
The irrelevant pulse of multichannel the most according to claim 2 merges number system, it is characterised in that when described Ua and Ub is
During two incoherent negative burst pulses, the structure of two-way irrelevant pulse consolidation circuit is:
Described time delay starting point auto-adjusting circuit includes and door U2A and diode D3；It is connected respectively with two inputs of door U2A
Ua and Ub；Diode D3 negative electrode it is connected with the outfan of door U2A；
Described pulse sequence comparison circuit includes or door U3A；Or two inputs of door U3A connect Ua and Ub respectively；
Described monostable flipflop includes LM555CM chip U1, resistance R1, electric capacity C1 and electric capacity C2；The discharge end of U1 and threshold value
End is all connected with the anode of diode D3, and the end that triggers of U1 connects or the outfan of door U3A；Resistance R1 one end connects the discharge end of U1
With threshold value end, the other end connects power vd D；Electric capacity C1 one end connects discharge end and the threshold value end of U1, and the other end connects power supply ground；
Electric capacity C2 one end connects the control power end of U1, and the other end connects power supply ground；
Described RC peaker includes electric capacity C3, resistance R2, resistance R3 and diode D4；The output of the one termination U1 of electric capacity C3
End, the other end is designated as junction point S, junction point S and meets power vd D through resistance R2；One end of resistance R3 and the negative electrode of diode D4 are equal
The other end of contact S in succession, resistance R3 and the anode of diode D4 all connect power supply ground；
Described voltage comparator includes LM393D chip U4A, resistance R4, resistance R5, electric capacity C4 and resistance R6；U4A's is the most defeated
Enter end and meet power vd D through resistance R4, connect power supply ground through resistance R5；Electric capacity C4 is in parallel with resistance R4；The positive input of U4A is in succession
Contact S；The outfan of U4A meets power vd D through resistance R6；
Described pulse-combining circuit includes diode D1, diode D2, diode D5 and resistance R7；
The negative electrode of diode D1, diode D2 and diode D5 connects the outfan of Ua, Ub and U4A respectively；Resistance R7 mono-terminates electricity
Source VDD, the other end is connected with the anode of D1, D2 and D5, is output Uoi。
5. the irrelevant pulse of multichannel merges method of counting, it is characterised in that by n two-way irrelevant pulse consolidation circuit level
Connection realizes the timesharing of the irrelevant pulse in n+1 road and merges；N is integer, and n >=2；Each two-way irrelevant pulse consolidation circuit is used
Merge in the two-way irrelevant pulse timesharing realizing input；
The timesharing of the n-th two-way irrelevant pulse consolidation circuit output of cascade is merged pulse and is sent to the clock end of enumerator,
Realize the merging counting of the irrelevant pulse in n+1 road；
Described cascade system is:
1st tunnel pulse and the 2nd tunnel pulse input the 1st two-way irrelevant pulse consolidation circuit, and output timesharing merges pulse Uo1；
The timesharing of the i-th-1 two-way irrelevant pulse consolidation circuit output merges pulse Uo(i-1)I-th is inputted with the pulse of i+1 road
Individual two-way irrelevant pulse consolidation circuit, output timesharing merges pulse Uoi；I=1,2 ..., n.
The irrelevant pulse of multichannel the most according to claim 5 merges method of counting, it is characterised in that i-th two-way not phase
The method of the two-way irrelevant pulse timesharing merging that dry pulse consolidation circuit realizes input is:
The irrelevant pulse of two-way that irrelevant for i-th two-way pulse consolidation circuit inputs is designated as Ua and Ub respectively；Ua and Ub is same
Time be sent to pulse sequence comparison circuit, time delay starting point auto-adjusting circuit and pulse-combining circuit；Pulse sequence comparison circuit
Two triggerings that output signal U c of output signal U d and time delay starting point auto-adjusting circuit connects monostable flipflop respectively are defeated
Enter end；Output signal U e of monostable flipflop is connected to the input of RC peaker, the output letter of described RC peaker
Number Uf is connected to the input of voltage comparator, and output signal U g of described voltage comparator is connected to described pulse combined electricity
Road, the output signal of described pulse-combining circuit is timesharing and merges pulse Uoi。
The irrelevant pulse of multichannel the most according to claim 6 merges method of counting, it is characterised in that
When two-way irrelevant pulse Ua and Ub staggers the most completely, described pulse sequence comparison circuit no pulse exports,
The output level of described monostable flipflop and voltage comparator does not overturns, and only Ua and Ub is directly sent to pulse combined electricity
Road exports two pulses after merging；
When two-way irrelevant pulse Ua, Ub are the most completely overlapped or partly overlap, described pulse sequence comparison circuit is defeated
Go out a pulse, and sequentially pass through after monostable flipflop, RC peaker and voltage comparator carry out time delay shaping and be sent to arteries and veins
Rushing combinational circuit, the pulse merged with by Ua and Ub is combined, thus also two pulses of output.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4300100A (en) * | 1978-07-28 | 1981-11-10 | Societa Italiana Telecomunicazioni Siemens S.P.A. | Circuit arrangement for correlating several isofrequentially stepped counting chains |
| US4759043A (en) * | 1987-04-02 | 1988-07-19 | Raytheon Company | CMOS binary counter |
| CN101030306A (en) * | 2007-03-31 | 2007-09-05 | 湘潭大学 | Multifunctional channel-style entrance system |
| CN203966224U (en) * | 2014-07-31 | 2014-11-26 | 湖南科技学院 | A kind of dormitory number checking device |
| CN104299306A (en) * | 2014-10-31 | 2015-01-21 | 湘潭大学 | Device for preventing from miscounting people in room |
| TW201547199A (en) * | 2014-06-04 | 2015-12-16 | Nuvoton Technology Corp | Counter |
| CN105630712A (en) * | 2014-10-28 | 2016-06-01 | 深圳市中兴微电子技术有限公司 | Counter and counting method |
| CN205792487U (en) * | 2016-07-15 | 2016-12-07 | 湘潭大学 | A kind of irrelevant pulse of multichannel merges number system |
-
2016
- 2016-07-15 CN CN201610556562.3A patent/CN106059570B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4300100A (en) * | 1978-07-28 | 1981-11-10 | Societa Italiana Telecomunicazioni Siemens S.P.A. | Circuit arrangement for correlating several isofrequentially stepped counting chains |
| US4759043A (en) * | 1987-04-02 | 1988-07-19 | Raytheon Company | CMOS binary counter |
| CN101030306A (en) * | 2007-03-31 | 2007-09-05 | 湘潭大学 | Multifunctional channel-style entrance system |
| TW201547199A (en) * | 2014-06-04 | 2015-12-16 | Nuvoton Technology Corp | Counter |
| CN203966224U (en) * | 2014-07-31 | 2014-11-26 | 湖南科技学院 | A kind of dormitory number checking device |
| CN105630712A (en) * | 2014-10-28 | 2016-06-01 | 深圳市中兴微电子技术有限公司 | Counter and counting method |
| CN104299306A (en) * | 2014-10-31 | 2015-01-21 | 湘潭大学 | Device for preventing from miscounting people in room |
| CN205792487U (en) * | 2016-07-15 | 2016-12-07 | 湘潭大学 | A kind of irrelevant pulse of multichannel merges number system |
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