CN105845084B - A kind of drive element of the grid and row gated sweep driver and its driving method - Google Patents
A kind of drive element of the grid and row gated sweep driver and its driving method Download PDFInfo
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- CN105845084B CN105845084B CN201610362978.1A CN201610362978A CN105845084B CN 105845084 B CN105845084 B CN 105845084B CN 201610362978 A CN201610362978 A CN 201610362978A CN 105845084 B CN105845084 B CN 105845084B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention discloses a kind of drive element of the grid and row gated sweep drivers and its driving method, drive element of the grid is made of signal acquisition module, boost module, inverter modules, negative pressure module, internal output module and scanning output module, pass through negative pressure module, drive element of the grid only needs single negative supply just can work normally, while simplifying circuit structure, reduce circuit area, the clock transition amplitude of oscillation can also be reduced, reduce circuit power consumption, in addition output module uses DC driven mode, dynamic power consumption can be reduced, improves response speed.It is connected after multistage drive element of the grid series connection and with corresponding power supply and time-sequence control module and just constitutes row gated sweep driver, driver only needs 3 driving clocks just can realize that the displacement of grid drive signal exports, and all clocks are the pipeline system driver' s timing of duty ratio 33.3%, sequential is simply independent, avoids the occurrence of race hazard, promotes circuit stability.
Description
Technical field
The present invention relates to the row gated sweep fields of active matrix light-emitting flat-panel monitor, and in particular to a kind of gate driving
Unit and row gated sweep driver and its driving method.
Background technology
Traditional display panel row gate driving circuit needs special driving chip, and chip is crimped on glass by technique
Pixel circuit is driven on glass substrate.In recent years, it with the development of technology, is directly integrated in display panel using thin film transistor (TFT)
Row gate driving circuit replaces the row integrated technology of driving chip to have become the hot topic of current research.Make grid in row integrated technology
Pole driving circuit is integrated in same an array with pixel circuit, caused by signal lead difference in length being avoided by placement-and-routing
Sequential is chaotic, improves signal quality；Substrate area can also be reduced, reduces processing step to reduce cost.In addition, for medium and small
Size display screen, row integrated technology can greatly shorten frame distance, realize narrow frame to meet people's aesthetic requirement.Hang Jicheng
Technology also is able to solve the problems, such as that traditional die may not apply to Flexible Displays well.
Novel oxide thin film transistor device is warm in recent years because its excellent performance, simple manufacturing process become
Door research object, but oxide thin film transistor is N-type device, the characteristic with negative threshold voltage, if using for positive threshold value
The line-scan circuit of voltage characteristic transistor exploitation, then can lead to circuit work(due to oxide thin film transistor cannot be closed thoroughly
Consumption, which increases severely, even can not work normally.In order to thoroughly turn off oxide thin film transistor, most of novel row turntable driving electricity
Two even more than two negative supplies can be used inside road, however more negative supplies can allow circuit structure to become complicated, inside connects
Line increases, circuit area increase, while the requirement to each power supply is also more harsh.In addition, most of line scanners are all to utilize
Exchange clock signal goes to provide output current, and the parasitic capacitance of output transistor can not only consume considerable power consumption, but also
Circuit switching speeds can also be reduced because of charge and discharge.
Invention content
In order to overcome shortcoming and deficiency of the existing technology, primary and foremost purpose of the present invention is to provide a kind of drive element of the grid
And row gated sweep driver.
It is a further object to provide a kind of driving method of drive element of the grid and row gated sweep drivers
Driving method.
The present invention adopts the following technical scheme that：
A kind of drive element of the grid, by signal acquisition module, boost module, inverter modules, negative pressure module, internal output
Module and scanning output module are formed, and the control signal of the drive element of the grid includes the first clock input port IN_EN, second
Clock input port OUT_EN, third clock input port CLR, the first power port VDD, second source mouth VSS, signal acquisition mouth Cin,
First delivery outlet COUT and the second delivery outlet GOUT；
The signal acquisition module is made of first and second transistor, the first transistor M1 drain electrodes and signal acquisition mouth
Cin is connected, and source electrode is connected with the drain electrode of second transistor M2, grid respectively with the grid of second transistor M2 and first when
Clock input port IN_EN is connected；
The boost module is made of the 6th transistor M6 and the first storage capacitance C1, the grid of the 6th transistor M6 and
The other end of one storage capacitance C1 and the source electrode of second transistor M2 are connected, as signal memory node Q, the 6th transistor M6's
Drain electrode is connected with second clock input port OUT_EN, and the source electrode of the 6th transistor M6 is connect with one end of the first storage capacitance C1；
The inverter modules are made of third transistor M3 and the 9th transistor M9, third transistor M3 drain electrodes and first
Power port VDD is connected, and the grid of third transistor M3 is connected with third clock input port CLR, the source electrode of third transistor M3 with
The grid of 9th transistor M9 is connected, the output node QB as inverter modules；The drain electrode of 9th transistor M9 is deposited with signal
Storage node Q is connected, and the source electrode of the 9th transistor M9 is connected with second source mouth VSS.
Negative pressure module is deposited by the 4th transistor M4, the 5th transistor M5, the 7th transistor M7, the 8th transistor M8 and second
Storing up electricity is held C2 and is formed；The drain electrode of the 4th transistor M4 and one end of the second storage capacitance C2 with phase inverter output node QB
Connection, the source electrode of the 4th transistor M4 is connected with the drain electrode of the 5th transistor M5, the grid of the 4th transistor M4 and
The grid of 5th transistor M5, the grid of the 7th transistor M7 are connected with signal acquisition mouth Cin；The source electrode of 5th transistor M5
It is connected with second source mouth VSS；The drain electrode of 7th transistor M7 is connected with the first power port VDD, the source electrode of the 7th transistor M7
The other end with the drain electrode of the 8th transistor M8 and the second storage capacitance C2 is connected respectively；The grid and second of 8th transistor M8
Clock input port OUT_EN is connected, and the source electrode of the 8th transistor M8 is connected with second source mouth VSS
Internal output module is made of the tenth transistor M10 and the 11st transistor M11, the tenth transistor M10's
Drain electrode is connected with the first power port VDD, and the grid of the tenth transistor M10 is connected with signal memory node Q, the tenth transistor
The source electrode of M10 is connected with the drain electrode of the 11st transistor M11 with the first delivery outlet COUT；The grid of 11st transistor M11
It is connected with phase inverter output node QB, the source electrode of the 11st transistor M11 is connected with second source mouth VSS
Scanning output module is made of the tenth two-transistor M12 and the 13rd transistor M13, the tenth two-transistor
The drain electrode of M12 is connected with the first power port VDD, and the grid of the tenth two-transistor M12 is connected with signal memory node Q, and the 12nd
The source electrode of transistor M12 is connected with the drain electrode of the 13rd transistor M13 with the second delivery outlet GOUT；13rd transistor M13
Grid be connected with output node QB, the source electrode of the 13rd transistor M13 is connected with second source mouth VDD.
The transistor of drive element of the grid is N-type TFT.
A kind of row gated sweep driver, including power supply and time-sequence control module and row gate driving array, wherein power supply
Output signal with time-sequence control module is high voltage VD, low-voltage VS, the first clock CK1, second clock CK2, third clock
CK3, triggering clock VI；
The row gate driving array is made of the row gate driving group of N grades of series connection, and each row gate driving group is by first
Drive element of the grid, second grid driving unit and third drive element of the grid are formed, and first, second and third grid drives
The control signal of moving cell includes the first clock input port IN_EN, second clock input port OUT_EN, third clock input port
CLR, the first power port VDD, second source mouth VSS, signal acquisition mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT.
In row gate driving array, the signal acquisition mouth of the first grid driving unit in first order row gate driving group
Cin is connected with power supply with the triggering clock VI of time-sequence control module；
The signal acquisition mouth Cin and K-1 grades of row gate drivings of first grid driving unit in K grades of row gate driving groups
The first delivery outlet COUT of third drive element of the grid is connected in group, the signal acquisition mouth Cin of second grid driving unit and
First delivery outlet COUT of one drive element of the grid is connected, the signal acquisition mouth Cin and second grid of third drive element of the grid
First delivery outlet COUT of driving unit is connected；
The first clock input port IN_EN, second clock per the first grid driving unit of level-one row gate driving group is defeated
Entrance OUT_EN, third clock input port CLR respectively with power supply and the first clock CK1, the second clock of time-sequence control module
CK2, third clock CK3 are connected；
The first clock input port IN_EN, second clock input port OUT_EN and the third clock of second grid driving unit
Input port CLR is connected respectively with power supply with the second clock CK2, third clock CK3, the first clock CK1 of time-sequence control module；
The first clock input port IN_EN, second clock input port OUT_EN and the third clock of third drive element of the grid
Input port CLR is connected respectively with power supply with the third clock CK3, the first clock CK1, second clock CK2 of time-sequence control module.
The high level of described first to third clock signal is equal with high voltage VD, tells first third clock signal
Low level is equal with low-voltage VS.
A kind of driving method of drive element of the grid, the first clock input port IN_EN, second clock input port OUT_EN with
And the clock-pulse width that third clock input port CLR is inputted is identical, duty ratio 33.3%, and level pulse from first when
Clock input port IN_EN successively to second clock input port OUT_EN, third clock input port CLR shifting flows assembly line when
Sequence；
Driving method specifically includes signal acquisition memory phase, signal output stage and reset phase；
Signal acquisition memory phase：First clock mouth IN_EN high input voltages, by the first transistor M1, second transistor
M2 is opened, signal acquisition mouth Cin input high level signals, and is input to the grid of acquisition signal storage point Q, the 6th transistor M6
And first in storage capacitance C1, the tenth transistor M10, the tenth two-transistor M12 are opened, while input high level signal is by
Four transistor M4, the 5th transistor M5 are opened, and reversed output node QB is pulled low to low-voltage state, the 9th transistor M9, the
11 transistor M11 and the 13rd transistor M13 are turned off, the first delivery outlet COUT, the second delivery outlet GOUT output positive voltage,
But less than input high level VD.In addition, the 7th transistor M7 is also turned on, electric current is flowed into from the first power port VDD, passes through the 7th
It flows out to be formed back through second source mouth VSS after transistor M7, the second storage capacitance C2, the 4th transistor M4, the 5th transistor M5
Road, the second storage capacitance C2 are electrically charged, and node N is high level at this time, and output node QB is low level；Second clock mouth OUT_EN
And third clock mouth CLR inputs low-voltage.Then, the first clock signal IN_EN becomes low-voltage, by the first transistor M1,
Second transistor M2 is turned off, and signal acquisition mouth Cin input low-voltages turn off the 4th transistor M4 and the 5th transistor M5 and the 7th
Transistor M7, signal acquisition are completed, this stage continues 1/3 clock period time；
Signal exports the stage：Second clock mouth OUT_EN high input voltages, due to the boot strap of the first capacitance C1, signal
To the high level of about twice VD, the tenth transistor M10 and the tenth two-transistor M12 are abundant for the level saltus step of memory node Q
It opens, the drive signal that the first delivery outlet COUT, the second delivery outlet GOUT output levels are about VD；Meanwhile the 8th transistor M8
It is opened, at this time the current potential of node N and the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 source potentials
For low level VS；Third clock input port CLR and signal acquisition mouth Cin input low level signals simultaneously, third to the 5th crystal
Pipe is closed, and reversed output point QB is in quick condition relative to any power port, and is imitated since the second storage capacitance C2 is stored
Should, the gate-source voltage difference of the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 are negative, above-mentioned crystal
Pipe is thoroughly closed, and avoids interference output signals, this stage continues 1/3 clock period time；
Reset phase：Third clock mouth CLR input high level signals, third transistor M3 are opened, reversed output node
QB becomes high level, and the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 are opened, acquisition signal storage
Point Q becomes low level, and the tenth transistor M10, the tenth two-transistor M12 are turned off, the first delivery outlet COUT and the second delivery outlet
GOUT exports low-voltage, and circuit resetting finishes, this stage continues 1/3 clock period time.
A kind of driving method of row gated sweep driver, the first clock CK1, second clock CK2, third clock CK3
Pulse width and cycle phase are same, duty ratio 33.3%, and for level pulse from the first clock CK1, successively to second clock
The assembly line sequential of CK2, third clock CK3 cyclic shifts；
When clock VI generates the level pulse identical with the first clock CK1 upon activation, row gated sweep driver enters just
In stage beginning, after 1/3 clock cycle T, first order drive element of the grid generates gate drive signal, subsequent gate driving lists at different levels
Member generates gate drive signal step by step by clock driving, when afterbody drive element of the grid generates the same of gate drive signal
When, triggering clock VI also generates the level pulse identical with the gate drive signal, and row gated sweep driver enters repetition rank
Section, after 1/3 clock cycle T, first order drive element of the grid generates gate drive signal, row gated sweep driving process for the second time
Terminate.
Beneficial effects of the present invention：
(1) row driver circuits invented are by that by built-in negative pressure module, can not only drop much lower power rows
The circuit layout difficulty of driver saves circuit area, moreover it is possible to reduce the clock voltage amplitude of oscillation, improve circuit efficiency.
(2) output module is scanned using DC control, avoids conventional AC control mode because of output transistor parasitic capacitance
Caused by dynamic power consumption, meanwhile, take full advantage of after the coupling bootstrapping of circuit internal capacitance the high voltage that generates to drive big ruler
Very little TFT reduces delay effect, is conducive to high frequency and shows.
(3) internal novel invertor module is utilized, the DC loop that low-voltage is flowed to from high voltage is avoided the occurrence of, drops significantly
The low power consumption of driver.
(4) driving method using 33.3% duty ratio timing control signal acquisition module, boost module, inverter modules,
Negative pressure module and internal output module, can avoid inside from race hazard situation occur, increase the stability and reliability of circuit,
High frequency is advantageously implemented to show.
Description of the drawings
Fig. 1 is the circuit diagram of the drive element of the grid in the embodiment of the present invention；
Fig. 2 is the structure diagram of the row gated sweep driver in the embodiment of the present invention；
Fig. 3 is driving unit connection diagram in the row gate driving group in implementation column of the present invention；
Fig. 4 is the driver' s timing oscillogram of Fig. 1 drive element of the grid in the embodiment of the present invention；
Fig. 5 is Fig. 2 rows gated sweep driver driver' s timing oscillogram in the embodiment of the present invention.
Specific embodiment
With reference to embodiment and attached drawing, the present invention is described in further detail, but embodiments of the present invention are not
It is limited to this.
Embodiment
As shown in Figure 1, a kind of drive element of the grid, by signal acquisition module 11, boost module 12, inverter modules 13,
Negative pressure module 14, internal output module 15 and scanning output module 16 are formed, and the control signal of the drive element of the grid includes
First clock input port IN_EN, second clock input port OUT_EN, third clock input port CLR, the first power port VDD, second
Power port VSS, signal acquisition mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT；
The signal acquisition module 11 is made of first and second transistor, the first transistor M1 drain electrodes and signal acquisition mouth
Cin is connected, and source electrode is connected with the drain electrode of second transistor M2, grid respectively with the grid of second transistor M2 and first when
Clock input port IN_EN is connected；
The boost module 12 is made of the 6th transistor M6 and the first storage capacitance C1, the grid of the 6th transistor M6 with
The other end of first storage capacitance C1 and the source electrode of second transistor M2 are connected, as signal memory node Q, the 6th transistor M6
Drain electrode be connected with second clock input port OUT_EN, one end of the source electrode of the 6th transistor M6 and the first storage capacitance C1 connects
It connects；
The inverter modules 13 are made of third transistor M3 and the 9th transistor M9, third transistor M3 drain electrodes and the
One power port VDD is connected, and the grid of third transistor M3 is connected with third clock input port CLR, the source electrode of third transistor M3
It is connected with the grid of the 9th transistor M9, the output node QB as inverter modules；9th transistor M9 drain electrodes are deposited with signal
Storage node Q is connected, and the source electrode of the 9th transistor M9 is connected with second source mouth VSS.
Negative pressure module 14 is by the 4th transistor M4, the 5th transistor M5, the 7th transistor M7, the 8th transistor M8 and second
Storage capacitance C2 is formed；The drain electrode of the 4th transistor M4 and one end of the second storage capacitance C2 with phase inverter output node
QB connections, the source electrode of the 4th transistor M4 are connected with the drain electrode of the 5th transistor M5, the grid of the 4th transistor M4
It is connected with the 5th transistor M5 grids, the 7th transistor M7 grids with signal acquisition mouth Cin；The source electrode of 5th transistor M5 with
Second source mouth VSS is connected；The drain electrode of 7th transistor M7 is connected with the first power port VDD, the source electrode point of the 7th transistor M7
The other end not with the drain electrode of the 8th transistor M8 and the second storage capacitance C2 is connected；The grid of 8th transistor M8 and when second
Clock input port OUT_EN is connected, and the source electrode of the 8th transistor M8 is connected with second source mouth VSS
Internal output module 15 is made of the tenth transistor M10 and the 11st transistor M11, the tenth transistor M10
Drain electrode be connected with the first power port VDD, the grid of the tenth transistor M10 is connected with acquisition signal memory node Q, the tenth
The source electrode of transistor M10 is connected with the drain electrode of the 11st transistor M11 with the first delivery outlet COUT；11st transistor M11
Grid be connected with phase inverter output node QB, the source electrode of the 11st transistor M11 is connected with second source mouth VSS
Scanning output module 16 is made of the tenth two-transistor M12 and the 13rd transistor M13, the tenth two-transistor
The drain electrode of M12 is connected with the first power port VDD, and the grid of the tenth two-transistor M12 is connected with acquisition signal memory node Q, the
The source electrode of ten two-transistor M12 is connected with the drain electrode of the 13rd transistor M13 with the second delivery outlet GOUT；13rd transistor
The grid of M13 is connected with phase inverter output node QB, and the source electrode of the 13rd transistor M13 is connected with second source mouth VDD.
All transistors of drive element of the grid are N-type TFT.
As shown in Fig. 2, a kind of row gated sweep driver, including power supply and time-sequence control module 20 and row gate driving battle array
When row 30, wherein power supply and the output signal of time-sequence control module 20 are high voltage VD, low-voltage VS, the first clock CK1, second
Clock CK2, third clock CK3, triggering clock VI；
The row gate driving array 30 is made of the row gate driving group of N grades of series connection, and each row gate driving group is by the
One drive element of the grid 31, second grid driving unit 32 and third drive element of the grid 33 are formed, and described first, second and
When the control signal of three drive element of the grid includes the first clock input port IN_EN, second clock input port OUT_EN, third
Clock input port CLR, the first power port VDD, second source mouth VSS, signal acquisition mouth Cin, the first delivery outlet COUT and second are defeated
Export GOUT.
First, second and third drive element of the grid is structure shown in FIG. 1.
Fig. 3 is connection figure inside all row gate driving groups, and specific connection mode is：
The signal acquisition mouth Cin of first grid driving unit in first order row gate driving group and power supply and timing control
The triggering clock VI of module is connected；
The signal acquisition mouth Cin and K-1 grades of row gate drivings of first grid driving unit in K grades of row gate driving groups
The first delivery outlet COUT of third drive element of the grid is connected in group, and the K is the integer more than or equal to 2；
The first delivery outlet COUT phases of the signal acquisition mouth Cin of second grid driving unit and first grid driving unit
Even, the signal acquisition mouth Cin of third drive element of the grid is connected with the first delivery outlet COUT of second grid driving unit；
The first clock input port IN_EN, second clock per the first grid driving unit of level-one row gate driving group is defeated
Entrance OUT_EN, third clock input port CLR respectively with power supply and the first clock CK1, the second clock of time-sequence control module
CK2, third clock CK3 are connected；
The first clock input port IN_EN, second clock input port OUT_EN and the third clock of second grid driving unit
Input port CLR is connected respectively with power supply with the second clock CK2, third clock CK3, the first clock CK1 of time-sequence control module；
The first clock input port IN_EN, second clock input port OUT_EN and the third clock of third drive element of the grid
Input port CLR is connected respectively with power supply with the third clock CK3, the first clock CK1, second clock CK2 of time-sequence control module.`
Second delivery outlet GOUT of first grid driving unit is lead GOUT1；The second of second grid driving unit is defeated
Outlet GOUT is lead GOUT2；Second delivery outlet GOUT of third drive element of the grid is lead GOUT3.
Described first to third clock signal high level it is equal with high voltage VD, described first to third clock signal
Low level is equal with low-voltage VS.
As shown in figure 4, a kind of driving method of drive element of the grid, the first clock input port IN_EN, second clock input
The clock-pulse width that mouth OUT_EN and third clock input port CLR is inputted is identical, duty ratio 33.3%, and level arteries and veins
It rushes from the first clock input port IN_EN successively to second clock input port OUT_EN, third clock input port CLR shifting flows
Assembly line sequential.
Including signal acquisition memory phase, signal output stage and reset phase；
Signal acquisition memory phase：First clock mouth IN_EN high input voltages, by the first transistor M1, second transistor
M2 is opened, signal acquisition mouth Cin input high level signals, and is input to the grid of acquisition signal storage point Q, the 6th transistor M6
And first in storage capacitance C1, the tenth transistor M10, the tenth two-transistor M12 are opened, while input high level signal is by
Four transistor M4, the 5th transistor M5 are opened, and reversed output node QB is pulled low to low-voltage state, the 9th transistor M9, the
11 transistor M11 and the 13rd transistor M13 are turned off, the first delivery outlet COUT, the second delivery outlet GOUT output positive voltage,
But less than input high level VD.In addition, the 7th transistor M7 is also turned on, electric current is flowed into from the first power port VDD, passes through the 7th
It flows out to be formed back through second source mouth VSS after transistor M7, the second storage capacitance C2, the 4th transistor M4, the 5th transistor M5
Road, the second storage capacitance C2 are electrically charged, and node N is high level at this time, and output node QB is low level；Second clock mouth OUT_EN
And third clock mouth CLR inputs low-voltage.Then, the first clock signal IN_EN becomes low-voltage, by the first transistor M1,
Second transistor M2 is turned off, and signal acquisition mouth Cin input low-voltages turn off the 4th transistor M4 and the 5th transistor M5 and the 7th
Transistor M7, signal acquisition are completed.This stage continues 1/3 clock period time；
Signal exports the stage：Second clock mouth OUT_EN high input voltages, due to the boot strap of the first capacitance C1, signal
To the high level of about twice VD, the tenth transistor M10 and the tenth two-transistor M12 are abundant for the level saltus step of memory node Q
It opens, the drive signal that the first delivery outlet COUT, the second delivery outlet GOUT output levels are about VD；Meanwhile the 8th transistor M8
It is opened, at this time the current potential of node N and the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 source potentials
For low level VS；Third clock input port CLR and signal acquisition mouth Cin input low level signals simultaneously, third to the 5th crystal
Pipe is closed, and reversed output point QB is in quick condition relative to any power port, and is imitated since the second storage capacitance C2 is stored
Should, the gate-source voltage difference of the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 are negative, above-mentioned crystal
Pipe is thoroughly closed, and avoids interference output signals.This stage continues 1/3 clock period time；
Reset phase：Third clock mouth CLR input high level signals, third transistor M3 are opened, reversed output node
QB becomes high level, and the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 are opened, acquisition signal storage
Point Q becomes low level, and the tenth transistor M10, the tenth two-transistor M12 are turned off, the first delivery outlet COUT and the second delivery outlet
GOUT exports low-voltage, and circuit resetting finishes.This stage continues 1/3 clock period time.
As described in Figure 5, a kind of driving method of row gated sweep driver, which is characterized in that the first clock CK1, second
Clock CK2, the pulse width of third clock CK3 and cycle phase are same, duty ratio 33.3%, and are level pulse from the first clock
CK1, to second clock CK2, the assembly line sequential of third clock CK3 cyclic shifts；
When clock VI generates the level pulse identical with the first clock CK1 upon activation, row gated sweep driver enters just
In stage beginning, after 1/3 clock cycle T, first order drive element of the grid generates gate drive signal, subsequent gate driving lists at different levels
Member generates gate drive signal step by step by clock driving.Particularly, when afterbody drive element of the grid generates gate driving letter
Number while, triggering clock VI also generates the level pulse identical with the gate drive signal, and row gated sweep driver enters
Duplication stages, after 1/3 clock cycle T, first order drive element of the grid generates gate drive signal for the second time, at this point, one complete
Whole row gated sweep driving process terminates.
By negative pressure module, drive element of the grid only needs single negative supply just can work normally, and simplifies circuit structure, reduces
While circuit area, moreover it is possible to reduce the clock transition amplitude of oscillation, reduce circuit power consumption, output module uses DC driven side in addition
Formula can reduce dynamic power consumption, improve response speed.After the series connection of multistage drive element of the grid and with corresponding power supply and sequential control
Molding block, which is connected, just constitutes row gated sweep driver, and driver only needs 3 driving clocks just can realize grid drive signal
Displacement output, and all clocks are the pipeline system driver' s timing of duty ratio 33.3%, and sequential is simply independent, avoids the occurrence of
Race hazard promotes circuit stability.Meanwhile after all taking full advantage of circuit internal bootstrap to row gate charges and discharge process
High voltage drive large scale TFT, improve reaction speed, be conducive to high frequency and show.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (7)
1. a kind of drive element of the grid, which is characterized in that by signal acquisition module, boost module, inverter modules, negative pressure mould
Block, internal output module and scanning output module are formed, and the control signal of the drive element of the grid is inputted including the first clock
Mouth IN_EN, second clock input port OUT_EN, third clock input port CLR, the first power port VDD, second source mouth VSS, letter
Number acquisition port Cin, the first delivery outlet COUT and the second delivery outlet GOUT；
The signal acquisition module is made of first and second transistor, drain electrode and the signal acquisition mouth Cin phases of the first transistor
Even, source electrode is connected with the drain electrode of second transistor, grid respectively with the grid of second transistor and the first clock input port
IN_EN is connected；
The boost module is made of the 6th transistor and the first storage capacitance, the grid and the first storage capacitance of the 6th transistor
The other end and the source electrode of second transistor be connected, as signal memory node Q, the drain electrode of the 6th transistor and second clock are defeated
Entrance OUT_EN is connected, and the source electrode of the 6th transistor is connect with one end of the first storage capacitance；
The inverter modules are made of third transistor and the 9th transistor, the drain electrode of third transistor and the first power port
VDD is connected, and the grid of third transistor is connected with third clock input port CLR, the source electrode of third transistor and the 9th transistor
Grid be connected, as inverter modules output node QB；The drain electrode of 9th transistor is connected with signal memory node Q, and the 9th
The source electrode of transistor is connected with second source mouth VSS；
Negative pressure module is made of the 4th transistor, the 5th transistor, the 7th transistor, the 8th transistor and the second storage capacitance；
The drain electrode of 4th transistor and one end of the second storage capacitance are connect with inverter modules output node QB, and the described 4th
The source electrode of transistor is connected with the drain electrode of the 5th transistor, the grid of the 4th transistor and the grid of the 5th transistor,
The grid of seven transistors is connected with signal acquisition mouth Cin；The source electrode of 5th transistor is connected with second source mouth VSS；7th
The drain electrode of transistor is connected with the first power port VDD, the source electrode drain electrode and second with the 8th transistor respectively of the 7th transistor
The other end of storage capacitance is connected；The grid of 8th transistor is connected with second clock input port OUT_EN, the 8th transistor
Source electrode is connected with second source mouth VSS；
Internal output module is made of the tenth transistor and the 11st transistor, drain electrode and the first power supply of the tenth transistor
Mouth VDD is connected, and the grid of the tenth transistor is connected with signal memory node Q, the source electrode of the tenth transistor and the 11st crystalline substance
The drain electrode of body pipe is connected with the first delivery outlet COUT；The grid of 11st transistor and inverter modules output node QB phases
Even, the source electrode of the 11st transistor is connected with second source mouth VSS；
Scanning output module is made of the tenth two-transistor and the 13rd transistor, the drain electrode and first of the tenth two-transistor
Power port VDD is connected, and the grid of the tenth two-transistor is connected with signal memory node Q, the source electrode and the tenth of the tenth two-transistor
The drain electrode of three transistors is connected with the second delivery outlet GOUT；The grid of 13rd transistor and inverter modules output node QB
It is connected, the source electrode of the 13rd transistor is connected with second source mouth VDD.
2. drive element of the grid according to claim 1, which is characterized in that the transistor of drive element of the grid is N-type
Thin film transistor (TFT).
3. the row gated sweep driver being made of claim 1-2 any one of them drive element of the grid, which is characterized in that
Including power supply and time-sequence control module and row gate driving array, the wherein output signal of power supply and time-sequence control module is high electricity
Press VD, low-voltage VS, the first clock CK1, second clock CK2, third clock CK3, triggering clock VI；
The row gate driving array is made of the row gate driving group of N grades of series connection, and each row gate driving group is by first grid
Driving unit, second grid driving unit and third drive element of the grid are formed, the first, second and third gate driving list
Member control signal include the first clock input port IN_EN, second clock input port OUT_EN, third clock input port CLR,
First power port VDD, second source mouth VSS, signal acquisition mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT.
4. row gated sweep driver according to claim 3, which is characterized in that
In row gate driving array, the signal acquisition mouth Cin of the first grid driving unit in first order row gate driving group with
Power supply is connected with the triggering clock VI of time-sequence control module；
In K grades of row gate driving groups in the signal acquisition mouth Cin and K-1 grades of row gate driving groups of first grid driving unit
First delivery outlet COUT of third drive element of the grid is connected, the signal acquisition mouth Cin and the first grid of second grid driving unit
First delivery outlet COUT of pole driving unit is connected, and signal acquisition mouth Cin and the second grid of third drive element of the grid drive
First delivery outlet COUT of unit is connected；
Per the first clock input port IN_EN of the first grid driving unit of level-one row gate driving group, second clock input port
OUT_EN, third clock input port CLR respectively with the first clock CK1 of power supply and time-sequence control module, second clock CK2,
Three clock CK3 are connected；
The first clock input port IN_EN, second clock input port OUT_EN and third the clock input of second grid driving unit
Mouth CLR is connected respectively with power supply with the second clock CK2, third clock CK3, the first clock CK1 of time-sequence control module；
First clock input port IN _ EN, second clock input port OUT_EN and third the clock input of third drive element of the grid
Mouth CLR is connected respectively with power supply with the third clock CK3, the first clock CK1, second clock CK2 of time-sequence control module.
5. row gated sweep driver according to claim 3, which is characterized in that first, second and third clock
The high level of signal is equal with high voltage VD, and the low level of first, second and third clock signal is equal with low-voltage VS.
6. according to the driving method of any one of the claim 1-2 drive element of the grid, which is characterized in that the first clock inputs
The clock-pulse width that mouth IN_EN, second clock input port OUT_EN and third clock input port CLR are inputted is identical, accounts for
Sky than for 33.3%, and level pulse from the first clock input port IN_EN successively to second clock input port OUT_EN, third when
The assembly line sequential of clock input port CLR shifting flows；
Driving method specifically includes signal acquisition memory phase, signal output stage and reset phase；
Signal acquisition memory phase：First clock mouth IN_EN high input voltages are opened the first transistor, second transistor, letter
Number acquisition port Cin input high level signals, and be input to acquisition signal memory node Q, the grid of the 6th transistor and first deposit
During storing up electricity is held, the tenth transistor, the tenth two-transistor are opened, while input high level signal is by the 4th transistor, the 5th brilliant
Body pipe is opened, and inverter modules output node QB is pulled low to low-voltage state, the 9th transistor, the 11st transistor and the
13 transistors are turned off, the first delivery outlet COUT, the second delivery outlet GOUT output positive voltage, but are less than input high level VD,
In addition, the 7th transistor is also turned on, electric current is flowed into from the first power port VDD, by the 7th transistor, the second storage capacitance,
It flows out and is formed into a loop through second source mouth VSS after 4th transistor, the 5th transistor, the second storage capacitance is electrically charged, this time
Point N is high level, and inverter modules output node QB is low level；Second clock mouth OUT_EN and third clock mouth CLR are defeated
Enter low-voltage；Then, the first clock signal IN_EN becomes low-voltage, the first transistor, second transistor is turned off, signal is adopted
Collect mouth Cin input low-voltages and turn off the 4th transistor and the 5th transistor and the 7th transistor, signal acquisition is completed, this stage holds
Continuous 1/3 clock period time；
Signal exports the stage：Second clock mouth OUT_EN high input voltages, due to the boot strap of the first capacitance, signal storage section
The high level of most twice VD of level saltus step of point Q, the tenth transistor and the tenth two-transistor are fully opened, the first delivery outlet
COUT, the drive signal that the second delivery outlet GOUT output levels are VD；Meanwhile the 8th transistor be opened, the electricity of node N at this time
Position and the 9th transistor, the 11st transistor and the 13rd source transistor electrode potential are low level VS；Third clock input simultaneously
Mouth CLR and signal acquisition mouth Cin input low level signals, third to the 5th transistor are closed, inverter modules output node QB
Quick condition is in relative to any power port, and due to the second storage capacitance storage effect, the 9th transistor, the 11st crystalline substance
The gate-source voltage difference of body pipe and the 13rd transistor is negative, and above-mentioned transistor is thoroughly closed, and avoids interference output signals,
This stage continues 1/3 clock period time；
Reset phase：Third clock mouth CLR input high level signals, third transistor are opened, inverter modules output node
QB becomes high level, and the 9th transistor, the 11st transistor and the 13rd transistor are opened, and acquisition signal memory node Q becomes
For low level, the tenth transistor, the tenth two-transistor are turned off, and the first delivery outlet COUT and the second delivery outlet GOUT export low
Voltage, circuit resetting finish, this stage continues 1/3 clock period time.
7. according to the driving method of any one of the claim 3-5 row gated sweep drivers, which is characterized in that the first clock
CK1, second clock CK2, the pulse width of third clock CK3 and cycle phase are same, duty ratio 33.3%, and for level pulse from
First clock CK1, successively to second clock CK2, the assembly line sequential of third clock CK3 cyclic shifts；
When clock VI generates the level pulse identical with the first clock CK1 upon activation, row gated sweep driver enters initialization
In the stage, after 1/3 clock cycle T, first order drive element of the grid generates gate drive signal, subsequent drive element of the grid at different levels by
Clock driving generates gate drive signal step by step, while afterbody drive element of the grid generates gate drive signal, touches
Hair clock VI also generates the level pulse identical with the gate drive signal, and row gated sweep driver enters duplication stages, and 1/3
After clock cycle T, first order drive element of the grid generates gate drive signal for the second time, and row gated sweep driving process terminates.
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| CN201610362978.1A CN105845084B (en) | 2016-05-25 | 2016-05-25 | A kind of drive element of the grid and row gated sweep driver and its driving method |
| PCT/CN2016/109469 WO2017202005A1 (en) | 2016-05-25 | 2016-12-12 | Gate driving unit, row gate scanning driver and driving method thereof |
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| CN107134246B (en) * | 2017-05-18 | 2023-09-26 | 华南理工大学 | Gate driving unit, row gate scanning driver and driving method thereof |
| TWI728783B (en) * | 2020-04-21 | 2021-05-21 | 友達光電股份有限公司 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915052A (en) * | 2013-01-05 | 2014-07-09 | 北京京东方光电科技有限公司 | Grid driving circuit and method and display device |
| CN104505036A (en) * | 2014-12-19 | 2015-04-08 | 深圳市华星光电技术有限公司 | Gate driver circuit |
| CN104517653A (en) * | 2013-10-08 | 2015-04-15 | 友达光电股份有限公司 | Shifting register and multistage shifting register circuit comprising same |
| CN105096803A (en) * | 2015-08-26 | 2015-11-25 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit, and display apparatus |
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| CN104732913B (en) * | 2013-12-19 | 2018-12-14 | 昆山国显光电有限公司 | The screen body structure and its voltage conversion circuit of AMOLED |
| CN103943058B (en) * | 2014-04-28 | 2017-04-05 | 华南理工大学 | A kind of row gated sweep device and its driving method |
| CN104064153B (en) * | 2014-05-19 | 2016-08-31 | 京东方科技集团股份有限公司 | Shift register cell, shift register, gate driver circuit and display device |
| CN104240766A (en) * | 2014-09-26 | 2014-12-24 | 合肥京东方光电科技有限公司 | Shifting register unit and gate driving device |
| CN104809973B (en) * | 2015-04-09 | 2017-10-31 | 北京大学深圳研究生院 | A kind of shift register and its unit for being suitable for negative threshold voltage |
| CN105845084B (en) * | 2016-05-25 | 2018-06-22 | 华南理工大学 | A kind of drive element of the grid and row gated sweep driver and its driving method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915052A (en) * | 2013-01-05 | 2014-07-09 | 北京京东方光电科技有限公司 | Grid driving circuit and method and display device |
| CN104517653A (en) * | 2013-10-08 | 2015-04-15 | 友达光电股份有限公司 | Shifting register and multistage shifting register circuit comprising same |
| CN104505036A (en) * | 2014-12-19 | 2015-04-08 | 深圳市华星光电技术有限公司 | Gate driver circuit |
| CN105096803A (en) * | 2015-08-26 | 2015-11-25 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit, and display apparatus |
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