CN105990098A - Method for forming polycrystalline silicon thin film and thin film transistor comprising polycrystalline silicon thin film - Google Patents
Method for forming polycrystalline silicon thin film and thin film transistor comprising polycrystalline silicon thin film Download PDFInfo
- Publication number
- CN105990098A CN105990098A CN201510084015.5A CN201510084015A CN105990098A CN 105990098 A CN105990098 A CN 105990098A CN 201510084015 A CN201510084015 A CN 201510084015A CN 105990098 A CN105990098 A CN 105990098A
- Authority
- CN
- China
- Prior art keywords
- cushion
- layer
- thin film
- polysilicon membrane
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present invention provides a method for forming a polycrystalline silicon thin film and a thin film transistor comprising the polycrystalline silicon thin film. The method includes the following steps that: 1) a first buffer layer is generated on a substrate; 2) a second buffer layer is generated on the first buffer layer; 3) a third buffer layer is generated on the second buffer layer; 4) an amorphous silicon layer is generated on the third buffer layer; 5) a fourth buffer layer is generated on the amorphous silicon layer; and 6) the amorphous silicon layer is crystallized. With the method of the invention adopted, the problem of large raised spots on the surface of a formed polycrystalline silicon thin film in the prior art can be solved, so that the uniformity of the surface of the polycrystalline silicon thin film can be improved, and the electrical properties of an MOS transistor can be ensured. The method of the invention is advantages in simplicity in structure setting.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of method forming polysilicon membrane
And comprise the thin film transistor (TFT) of polysilicon membrane.
Background technology
In the industry of organic plates face, polysilicon membrane is widely deployed and manufactures.Apply most,
No more than being used for producing TFT thin film transistor (TFT).Generally, polysilicon is to be formed by recrystallized amorphous silicon.Tool
Saying, non-crystalline silicon, based on its crystallization temperature, is i.e. higher or lower than 500 DEG C, its typical side of crystallization body
Method is the crystallizing process under low temperature and high temperature crystallization method.The crystallizing process under low temperature includes: excimer laser annealing method；
High temperature crystallization method includes: solid-phase crystallization method, Rapid Annealing Method etc..Compare two kinds of method for crystallising, be excited
Quasi-molecule laser annealing method has can provide bigger field-effect mobility and advantage more low in calories,
The cost of high temperature crystallization method then relative moderate.
At present, high-quality polysilicon membrane commonly used quasi-molecule laser annealing method carries out non-crystalline silicon knot
Crystalline substance, sees figures.1.and.2 shown, and the concrete basic process of this method for crystallising is: utilize CVD chemistry
Vapour deposition principle, first generates the SiO of thick layer2Layer is as cushion more raw on this cushion
Become last layer amorphous silicon membrane, afterwards with excimer laser irradiation amorphous thin Film layers and anneal,
Amorphous silicon thin-film materials can absorb the laser energy of PRK, and then crystallization formation polysilicon is thin
Film.But often there is bigger protuberance spot on the surface forming polysilicon membrane, polysilicon membrane surface equal
Even property cannot ensure, thus affects the electrical property of metal-oxide-semiconductor.
For example, patent publication No. is: the Chinese invention patent of CN 1770472 A, discloses a kind of shape
Become the method for polysilicon film.The method specifically includes: the first heat leads film and thermal conductivity less than the first heat
The second heat leading film leads film, to form lower film；Formation is covered in the second heat and leads the non-of film
Polycrystal silicon film；Crystallizing amorphous silicon thin film.The purpose of this patent is, forms bigger crystallite dimension many
Polycrystal silicon film.
It would therefore be desirable to a kind of reduce film surface protuberance spot the method forming polysilicon, with
It is effectively improved polysilicon membrane surface uniformity.
Content of the invention
For overcoming the defect existing for prior art, existing offer one changes thin film-forming method and then forms polysilicon
The method of film and the thin film transistor (TFT) comprising this polysilicon membrane, to solve to be formed the table of polysilicon membrane
Often there is the problem of bigger protuberance spot in face, thus improves the uniformity on polysilicon membrane surface, goes forward side by side
One step ensures the electrical property of metal-oxide-semiconductor.
For achieving the above object, the present invention discloses and a kind of change thin film-forming method and then form polysilicon membrane
Method, comprises the following steps:
1) on substrate, the first cushion is generated；
2) on the first cushion, the second cushion is generated；
3) on the second cushion, three buffer layer is generated；
4) on three buffer layer, amorphous silicon layer is generated；
5) on amorphous silicon layer, the 4th cushion is generated；
6) amor phous silicon layer, makes amorphous silicon layer and the 4th cushion form polysilicon membrane.
Having the beneficial effects that of the inventive method: change existing tradition crystallization of amorphous silicon on one layer of cushion
Film forming configuration settings, adds careless cushion at fine and close buffering interlayer so that each cause buffering interlayer
Close property produces notable difference, to be effectively improved the uniformity on polysilicon membrane surface.
The further improvements in methods that the present invention forms polysilicon are,
First cushion, three buffer layer and the 4th cushion are all extinction coefficient and are less than 10-4Dioxy
SiClx layer；Second cushion is extinction coefficient 10-2～10-4Silicon dioxide layer.
The further improvements in methods that the present invention forms polysilicon are,
The thickness of the first cushion, the second cushion and three buffer layer is 50nm～100nm；
The thickness of the 4th cushion is 10nm～15nm；The thickness of amorphous silicon layer is 40nm～50nm.
The further improvements in methods that the present invention forms polysilicon are,
Step 1) to step 5) all utilize chemical gaseous phase deposition principle to generate corresponding layer.
The further improvements in methods that the present invention forms polysilicon are,
In step 4) after step 5) before, also include being carried out amorphous silicon layer.
The further improvements in methods that the present invention forms polysilicon are,
Step 6) pass through excimer laser irradiation with amor phous silicon layer.
For above-mentioned purpose is better achieved, invention additionally discloses a kind of film crystal including polysilicon membrane
Pipe, the structure of this thin film transistor (TFT) specifically includes:
Substrate；
First cushion, is arranged on substrate；
Second cushion, is arranged on the first cushion；
Three buffer layer, is arranged on the second cushion；
Polysilicon membrane, is arranged on three buffer layer；
Gate insulator, is arranged on partial polysilicon film；
Grid, is arranged on gate insulator；
Insulating barrier, is arranged on polysilicon membrane and grid, and insulating barrier has two openings, exposes respectively and is positioned at
The polysilicon membrane of grid both sides；And
First electrode and the second electrode, lay respectively on two openings of insulating barrier, and respectively with grid both sides
Polysilicon membrane connects.
Further improvement is that of thin film transistor (TFT) of the present invention,
First cushion and three buffer layer are all extinction coefficient and are less than 10-4Silicon dioxide layer；Second buffering
Layer is extinction coefficient 10-2～10-4Silicon dioxide layer.
Further improvement is that of thin film transistor (TFT) of the present invention,
The thickness of the first cushion, the second cushion and three buffer layer is 50nm～100nm；Polysilicon is thin
The thickness of film is 40nm～50nm.
Advantages of the present invention: configuration settings is simple, and beneficial effect is notable.
Brief description
Fig. 1 is the existing configuration settings schematic diagram generally forming polysilicon；
Fig. 2 is the structural representation after existing universal polysilicon is formed；
Fig. 3 is the logic diagram that the present invention forms polysilicon membrane method；
Fig. 4 is that the present invention forms the first enforcement view in polysilicon membrane method；
Fig. 5 is the second enforcement view based on Fig. 4；
Fig. 6 is the 3rd enforcement view based on Fig. 5；
Fig. 7 is the 4th enforcement view based on Fig. 6；
Fig. 8 is the structural representation of the thin film transistor (TFT) that the present invention comprises polysilicon membrane.
Detailed description of the invention
For the benefit of the understanding to the structure of the present invention, illustrates below in conjunction with drawings and Examples.
With reference to shown in Fig. 3, first the present invention discloses a kind of method changing thin film-forming method formation polysilicon,
To solve to form the problem that often there is bigger protuberance spot on the surface of polysilicon membrane.
Including following key step:
Step S10, generates the first cushion 1 on the substrate 100；
Step S20, generates the second cushion 2 on the first cushion 1；
Step S30, generates three buffer layer 3 on the second cushion 2；
Step S40, generates amorphous silicon layer 4 on three buffer layer 3；
Step S50, generates the 4th cushion 5 on amorphous silicon layer 4；
Step S60, amor phous silicon layer, form polysilicon membrane 6.
It is described in detail below for each step above-mentioned.
Such as Fig. 4, step S10, generate the first cushion 1 on the substrate 100.At the present embodiment
In, utilize chemical vapor deposition method, generate the silica material of a densification on the substrate 100
First cushion 1, the thickness of this silicon dioxide layer 1 is 80nm, and extinction coefficient is less than 10-4。
Such as Fig. 5, step S20, the first cushion 1 generates the second cushion 2.In this reality
Execute in example, utilize chemical vapor deposition method, between the first cushion 1 of silica material has
Generate the second cushion 2 of one layer of careless silica material, the thickness of this second cushion 2 every ground
Degree is 80nm, extinction coefficient 10-2～10-4。
Such as Fig. 6, step S30, the second cushion 2 generates three buffer layer 3.In this reality
Execute in example, utilize chemical vapor deposition method, the second cushion 2 generates one layer of fine and close dioxy
The three buffer layer 3 of SiClx material, the thickness of this three buffer layer 3 is 80nm, and extinction coefficient is less than
10-4。
Such as Fig. 6, step S40, three buffer layer 3 generates amorphous silicon layer 4.In this enforcement
In example, utilize chemical vapor deposition method, three buffer layer 3 generates one layer of amorphous silicon layer 4.
The thickness of this amorphous silicon layer 4 is 45nm.
Such as Fig. 6, first the amorphous silicon layer 4 in step S40 can be carried out before step S50
Clean.
Such as Fig. 6, step S50, amorphous silicon layer 4 generates the 4th cushion 5.In this enforcement
In example, utilize chemical vapor deposition method, amorphous silicon layer 4 generates one layer of fine and close silica
4th cushion 5 of material.The thickness of this 4th cushion 5 is 10nm, and extinction coefficient is less than 10-4。
In conjunction with Fig. 7 and Fig. 8, step S60, amor phous silicon layer.In the present embodiment, enter
Row excimer laser irradiation, with amor phous silicon layer 4 so that amorphous silicon layer 4 and the 4th cushion 5
In conjunction with so formed polysilicon membrane 6.
After polysilicon membrane 6 to be formed, can stack successively further on partial polysilicon film 6
Gate insulator 7 and grid 8, and insulating barrier 9 is set on this grid 8 and polysilicon membrane 6, should
Insulating barrier 9 has two openings and exposes the polysilicon membrane 6 being positioned at grid 8 both sides respectively.Again by first
Electrode 11 and the second electrode 12 are deposited on two openings of insulating barrier 9, and respectively with grid 8 liang
The polysilicon membrane 6 of side connects.
With reference to shown in Fig. 8, the invention also discloses a kind of film crystal comprising above-mentioned polysilicon membrane
Pipe, comprising: substrate 100；The first fine and close cushion 1, is arranged on substrate 100；Loose second is delayed
Rush layer 2, be arranged on the first cushion 1；Fine and close three buffer layer 3, is arranged at the second cushion 2
On；Polysilicon membrane 6, is arranged on three buffer layer 3；Gate insulator 7, is arranged at partial polysilicon
On film 6；Grid 8, is arranged on gate insulator 7；Insulating barrier 9, is arranged at polysilicon membrane 6 and grid
On 8, this insulating barrier 9 has two openings, exposes the polysilicon membrane 6 being positioned at grid 8 both sides respectively；And,
First electrode 11 and the second electrode, lay respectively on two openings of insulating barrier 9, and respectively with grid 8 both sides
Polysilicon membrane 6 connect.
Specifically, the first cushion 1 and three buffer layer 3 are all extinction coefficient and are less than 10-4Silica
Layer；And the second cushion 2 is extinction coefficient 10-2～10-4Silicon dioxide layer.First cushion the 1st, second
The thickness of cushion 2 and three buffer layer 3 is 50nm～100nm；And the thickness of polysilicon membrane 6 is 40nm
～50nm.
In conjunction with Fig. 7, more preferably, the second cushion 2 is laid on the first cushion 1, and polysilicon
Film 6 is to be formed by above-mentioned amorphous silicon layer 4 and the 4th cushion 5 crystallization, then at polysilicon membrane 6
On be provided with gate insulator 7 and grid 8.
The structure of thin film transistor (TFT) of the present invention also can be implemented to make by the method for above-mentioned formation polysilicon membrane.
The present invention forms polysilicon membrane method and has a following actual effect:
1) arranged by the cushion of different extinction coefficients, reduce protuberance spot, to improve formation
The uniformity on polysilicon membrane surface；
2) after polysilicon membrane uniformity improves, and then the product yield of thin film transistor (TFT) is increased；
Being described in detail the present invention above in association with accompanying drawing embodiment, those skilled in the art can
Make many variations example according to the above description to the present invention.Thus, some details in embodiment should not be constituted
Limitation of the invention, the present invention by the scope that defines using appended claims as protection domain.
Claims (9)
1. the method forming polysilicon membrane, it is characterised in that comprise the following steps:
1) on substrate, the first cushion is generated；
2) on described first cushion, the second cushion is generated；
3) on described second cushion, three buffer layer is generated；
4) on described three buffer layer, amorphous silicon layer is generated；
5) on described amorphous silicon layer, the 4th cushion is generated；
6) amorphous silicon layer described in crystallization, makes described amorphous silicon layer and described 4th cushion form polysilicon thin
Film.
2. the method for formation polysilicon membrane according to claim 1, it is characterised in that；
Described first cushion, described three buffer layer and described 4th cushion are all extinction coefficient and are less than
10-4Silicon dioxide layer；
Described second cushion is extinction coefficient 10-2～10-4Silicon dioxide layer.
3. the method for formation polysilicon membrane according to claim 2, it is characterised in that:
The thickness of described first cushion, described second cushion and described three buffer layer be 50nm～
100nm；The thickness of described 4th cushion is 10nm～15nm；The thickness of described amorphous silicon layer be 40nm～
50nm。
4. the method for formation polysilicon membrane according to claim 1, it is characterised in that:
Described step 1) to step 5) all utilize chemical gaseous phase deposition principle to generate corresponding layer.
5. the method for formation polysilicon membrane according to claim 1, it is characterised in that:
In described step 4) after step 5) before, also include being carried out described amorphous silicon layer.
6. the method for formation polysilicon according to claim 1, it is characterised in that:
Described step 6) pass through excimer laser irradiation with amorphous silicon layer described in crystallization.
7. the thin film transistor (TFT) including polysilicon membrane, it is characterised in that include:
Substrate；
First cushion, is arranged on described substrate；
Second cushion, is arranged on described first cushion；
Three buffer layer, is arranged on described second cushion；
Polysilicon membrane, is arranged on described three buffer layer；
Gate insulator, is arranged on the described polysilicon membrane of part；
Grid, is arranged on described gate insulator；
Insulating barrier, is arranged on described polysilicon membrane and described grid, and described insulating barrier has two openings, point
Do not expose the described polysilicon membrane being positioned at described grid both sides；And
First electrode and the second electrode, lay respectively on two openings of described insulating barrier, and respectively with described grid
The described polysilicon membrane of both sides, pole connects.
8. thin film transistor (TFT) according to claim 7, it is characterised in that
Described first cushion and described three buffer layer are all extinction coefficient and are less than 10-4Silicon dioxide layer；
Described second cushion is extinction coefficient 10-2～10-4Silicon dioxide layer.
9. thin film transistor (TFT) according to claim 8, it is characterised in that
The thickness of described first cushion, described second cushion and described three buffer layer be 50nm～
100nm；The thickness of described polysilicon membrane is 40nm～50nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510084015.5A CN105990098B (en) | 2015-02-16 | 2015-02-16 | Form the method for polysilicon membrane and the thin film transistor (TFT) comprising polysilicon membrane |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510084015.5A CN105990098B (en) | 2015-02-16 | 2015-02-16 | Form the method for polysilicon membrane and the thin film transistor (TFT) comprising polysilicon membrane |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990098A true CN105990098A (en) | 2016-10-05 |
| CN105990098B CN105990098B (en) | 2019-09-13 |
Family
ID=57037655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510084015.5A Active CN105990098B (en) | 2015-02-16 | 2015-02-16 | Form the method for polysilicon membrane and the thin film transistor (TFT) comprising polysilicon membrane |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990098B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107422513A (en) * | 2017-07-28 | 2017-12-01 | 京东方科技集团股份有限公司 | Display base plate and its manufacture method and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN103199111A (en) * | 2012-01-10 | 2013-07-10 | 三星显示有限公司 | Semiconductor device and method of manufacturing the same |
| CN103283006A (en) * | 2011-11-07 | 2013-09-04 | 松下电器产业株式会社 | Method for manufacturing thin film transistor device, thin film transistor device, and display device |
| CN104037127A (en) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | Preparation method for polycrystalline silicon layer and display substrate, and display substrate |
-
2015
- 2015-02-16 CN CN201510084015.5A patent/CN105990098B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN103283006A (en) * | 2011-11-07 | 2013-09-04 | 松下电器产业株式会社 | Method for manufacturing thin film transistor device, thin film transistor device, and display device |
| CN103199111A (en) * | 2012-01-10 | 2013-07-10 | 三星显示有限公司 | Semiconductor device and method of manufacturing the same |
| CN104037127A (en) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | Preparation method for polycrystalline silicon layer and display substrate, and display substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107422513A (en) * | 2017-07-28 | 2017-12-01 | 京东方科技集团股份有限公司 | Display base plate and its manufacture method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990098B (en) | 2019-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100490074C (en) | Method for producing polycrystal silicon thin film and method for producing transistor using the same | |
| JP5015473B2 (en) | Thin film transistor array and manufacturing method thereof | |
| TWI224868B (en) | Method of forming poly-silicon thin film transistor | |
| US9299808B2 (en) | Manufacturing method of low temperature polysilicon, low temperature polysilicon film and thin film transistor | |
| CN105070724A (en) | TFT substrate manufacturing method and TFT substrate | |
| WO2014139291A1 (en) | Manufacturing method of polycrystalline silicon layer, and polycrystalline silicon thin film transistor and manufacturing method thereof | |
| JP2006024881A (en) | Thin film transistor and its manufacturing method | |
| JP2009295996A (en) | Thin-film transistor | |
| WO2016206239A1 (en) | Low-temperature poly-silicon thin film transistor and preparation method therefor | |
| JP2010145984A (en) | Organic electroluminescent display device and method of manufacturing the same | |
| JP2011181842A (en) | Method of manufacturing semiconductor device | |
| JP5309387B2 (en) | Semiconductor layer and semiconductor device and display device using the semiconductor layer | |
| TW201528524A (en) | Thin film transistor, method of manufacturing thereof, and application thereof | |
| CN106784412B (en) | Flexible organic light emitting diode display and preparation method thereof | |
| CN1842919A (en) | Thin-film transistor and production method therefor | |
| CN109638174B (en) | OLED display panel and manufacturing method thereof | |
| WO2019085096A1 (en) | Method for manufacturing flexible oled display panel, and flexible oled display panel | |
| WO2014153841A1 (en) | Manufacturing method of low-temperature polysilicon thin film and manufacturing method of thin-film transistor | |
| WO2007116917A1 (en) | Production method for 3-d semiconductor device | |
| US20070077735A1 (en) | Element of low temperature poly-silicon thin film and method of making poly-silicon thin film by direct deposition at low temperature and inductively-coupled plasma chemical vapor deposition equipment therefor | |
| CN105990098A (en) | Method for forming polycrystalline silicon thin film and thin film transistor comprising polycrystalline silicon thin film | |
| JP2007067399A (en) | Method of forming single-crystal silicon layer, and method of manufacturing thin-film transistor using the same | |
| Sugawara et al. | Crystallization of double-layered silicon thin films by solid green laser annealing for high-performance thin-film transistors | |
| JP2006013425A (en) | Thin film transistor and its manufacturing method | |
| JP5652926B2 (en) | Method for forming gate insulating film and method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 201506, No. nine, No. 1568, Jinshan Industrial Zone, Shanghai, Jinshan District Patentee after: Shanghai Hehui optoelectronic Co., Ltd Address before: 201508, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee before: EverDisplay Optronics (Shanghai) Ltd. |
|
| CP03 | Change of name, title or address |