CN105990098B - Form the method for polysilicon membrane and the thin film transistor (TFT) comprising polysilicon membrane - Google Patents
Form the method for polysilicon membrane and the thin film transistor (TFT) comprising polysilicon membrane Download PDFInfo
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- CN105990098B CN105990098B CN201510084015.5A CN201510084015A CN105990098B CN 105990098 B CN105990098 B CN 105990098B CN 201510084015 A CN201510084015 A CN 201510084015A CN 105990098 B CN105990098 B CN 105990098B
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Abstract
The present invention provides a kind of method for forming polysilicon membrane and include the thin film transistor (TFT) of polysilicon membrane, wherein method includes following key step: 1) first buffer layer is generated on substrate；2) second buffer layer is generated in first buffer layer；3) third buffer layer is generated in second buffer layer；4) amorphous silicon layer is generated on third buffer layer；5) the 4th buffer layer is generated on amorphous silicon layer；6) amor phous silicon layer.The present invention solves the problems, such as that form the surface of polysilicon membrane often has biggish protuberance spot, to improve the uniformity on polysilicon membrane surface, and is further ensured that the electrical property of metal-oxide-semiconductor.Advantages of the present invention: configuration settings are simple, and beneficial effect is significant.
Description
Technical field
The invention belongs to field of semiconductor manufacture, more particularly to a kind of method for forming polysilicon membrane and include polycrystalline
The thin film transistor (TFT) of silicon thin film.
Background technique
In organic plate face industry, polysilicon membrane is widely deployed and manufactures.Using most, no more than for giving birth to
Produce TFT thin film transistor (TFT).In general, polysilicon is formed by recrystallized amorphous silicon.Specifically, amorphous silicon is based on its crystallization temperature,
It is higher or lower than 500 DEG C, typical method for crystallising is the crystallizing process under low temperature and high temperature crystallization method.The crystallizing process under low temperature include: by
Excimers laser annealing method；High temperature crystallization method includes: solid-phase crystallization method, Rapid Annealing Method etc..Two kinds of method for crystallising are compared, by
Excimers laser annealing method has the advantages that can provide biggish field-effect mobility and more low in calories, and high temperature crystallization method
Cost then relative moderate.
Currently, the polysilicon membrane of high quality, which generallys use quasi-molecule laser annealing method, carries out recrystallized amorphous silicon, referring to Fig.1
With shown in Fig. 2, the specific basic process of this method for crystallising are as follows: utilize CVD chemical vapor deposition principle, first generate a thickness
SiO2Layer is used as buffer layer, then upper one layer of amorphous silicon membrane is generated on this buffer layer, later with excimer laser irradiation amorphous
Silicon membrane layer is simultaneously annealed, and amorphous silicon thin-film materials can absorb the laser energy of excimer laser, and then crystallize and form polycrystalline
Silicon thin film.But often there is biggish protuberance spot on the surface for forming polysilicon membrane, and the uniformity on polysilicon membrane surface cannot
Guarantee, to influence the electrical property of metal-oxide-semiconductor.
For example, patent publication No. are as follows: the Chinese invention patent of 1770472 A of CN discloses and a kind of forms polysilicon film
Method.The method specifically includes: the first thermal conductivity film and thermal conductivity are lower than the second thermal conductivity film of the first thermal conductivity film, to be formed
Lower film；Form the amorphous silicon membrane for being covered in the second thermal conductivity film；Crystallizing amorphous silicon thin film.The purpose of this patent is,
Form the polysilicon membrane compared with big crystal grain size.
It would therefore be desirable to which a kind of method for reducing film surface protuberance spot and forming polysilicon, more to be effectively improved
Polycrystal silicon film surface uniformity.
Summary of the invention
To overcome the defects of present in the prior art, a kind of change thin film-forming method is now provided and then forms polysilicon membrane
Method and thin film transistor (TFT) comprising the polysilicon membrane often have biggish protuberance spot with the surface for solving to form polysilicon membrane
The problem of point, to improve the uniformity on polysilicon membrane surface, and it is further ensured that the electrical property of metal-oxide-semiconductor.
To achieve the above object, the present invention discloses a kind of method that change thin film-forming method forms polysilicon membrane in turn, packet
Include following steps:
1) first buffer layer is generated on substrate；
2) second buffer layer is generated in first buffer layer；
3) third buffer layer is generated in second buffer layer；
4) amorphous silicon layer is generated on third buffer layer；
5) the 4th buffer layer is generated on amorphous silicon layer；
6) amor phous silicon layer makes amorphous silicon layer and the 4th buffer layer form polysilicon membrane.
The beneficial effect of the method for the present invention is: changing the film forming knot of existing tradition crystallization of amorphous silicon on one layer of buffer layer
Structure setting adds careless buffer layer in fine and close buffering interlayer, so that respectively the compactness of buffering interlayer generates notable difference, with
It is effectively improved the uniformity on polysilicon membrane surface.
The present invention formed polysilicon further improvements in methods be,
First buffer layer, third buffer layer and the 4th buffer layer are all extinction coefficient less than 10-4Silicon dioxide layer；Second
Buffer layer is extinction coefficient 10-2~10-4Silicon dioxide layer.
The present invention formed polysilicon further improvements in methods be,
First buffer layer, second buffer layer and third buffer layer with a thickness of 50nm~100nm；
4th buffer layer with a thickness of 10nm~15nm；Amorphous silicon layer with a thickness of 40nm~50nm.
The present invention formed polysilicon further improvements in methods be,
Step 1) generates corresponding layer using chemical vapor deposition principle to step 5).
The present invention formed polysilicon further improvements in methods be,
It further include being cleaned to amorphous silicon layer before step 5) after step 4).
The present invention formed polysilicon further improvements in methods be,
Step 6) is by excimer laser irradiation with amor phous silicon layer.
For above-mentioned purpose is better achieved, invention additionally discloses it is a kind of include polysilicon membrane thin film transistor (TFT), should
The structure of thin film transistor (TFT) specifically includes:
Substrate；
First buffer layer is set on substrate；
Second buffer layer is set in first buffer layer；
Third buffer layer, is set in second buffer layer；
Polysilicon membrane is set on third buffer layer；
Gate insulating layer is set on partial polysilicon film；
Grid is set on gate insulating layer；
Insulating layer is set on polysilicon membrane and grid, and insulating layer has two openings, is exposed respectively positioned at grid two
The polysilicon membrane of side；And
First electrode and second electrode are located in two openings of insulating layer, and the polysilicon with grid two sides respectively
Film connection.
Thin film transistor (TFT) of the present invention further improvement lies in that,
First buffer layer and third buffer layer are all extinction coefficient less than 10-4Silicon dioxide layer；Second buffer layer is to disappear
Backscatter extinction logarithmic ratio 10-2~10-4Silicon dioxide layer.
Thin film transistor (TFT) of the present invention further improvement lies in that,
First buffer layer, second buffer layer and third buffer layer with a thickness of 50nm~100nm；The thickness of polysilicon membrane
For 40nm~50nm.
Advantages of the present invention: configuration settings are simple, and beneficial effect is significant.
Detailed description of the invention
Fig. 1 is the existing configuration settings schematic diagram for generally forming polysilicon；
Fig. 2 is the structural schematic diagram after existing universal polysilicon is formed；
Fig. 3 is the logic diagram that the present invention forms polysilicon membrane method；
Fig. 4 is that the present invention forms the first implementation status diagram in polysilicon membrane method；
Fig. 5 is the second implementation status diagram based on Fig. 4；
Fig. 6 is that the third based on Fig. 5 implements status diagram；
Fig. 7 is the 4th implementation status diagram based on Fig. 6；
Fig. 8 is the structural schematic diagram of thin film transistor (TFT) of the present invention comprising polysilicon membrane.
Specific embodiment
To facilitate the understanding of the structure of the invention, it is illustrated with reference to the accompanying drawings and embodiments.
Referring to shown in Fig. 3, the present invention discloses a kind of method that change thin film-forming method forms polysilicon first, to solve shape
Often there is the problem of biggish protuberance spot at the surface of polysilicon membrane.
Including following key step:
Step S10 generates first buffer layer 1 on the substrate 100；
Step S20 generates second buffer layer 2 in first buffer layer 1；
Step S30 generates third buffer layer 3 in second buffer layer 2；
Step S40 generates amorphous silicon layer 4 on third buffer layer 3；
Step S50 generates the 4th buffer layer 5 on amorphous silicon layer 4；
Step S60, amor phous silicon layer form polysilicon membrane 6.
It is described in detail below for above-mentioned each step.
Such as Fig. 4, step S10 is executed, generates first buffer layer 1 on the substrate 100.In the present embodiment, chemical gas is utilized
Phase depositing operation generates the first buffer layer 1 of a fine and close silica material, the thickness of this silicon dioxide layer 1 on the substrate 100
Degree is 80nm, and extinction coefficient is less than 10-4。
Such as Fig. 5, step S20 is executed, second buffer layer 2 is generated in first buffer layer 1.In the present embodiment, change is utilized
Gas-phase deposition is learned, generates one layer of careless silica material with interval in the first buffer layer 1 of silica material
The second buffer layer 2 of matter, this second buffer layer 2 with a thickness of 80nm, extinction coefficient 10-2~10-4。
Such as Fig. 6, step S30 is executed, third buffer layer 3 is generated in second buffer layer 2.In the present embodiment, change is utilized
Gas-phase deposition is learned, the third buffer layer 3 of one layer of fine and close silica material, this third are generated in second buffer layer 2
Buffer layer 3 with a thickness of 80nm, extinction coefficient is less than 10-4。
Such as Fig. 6, step S40 is executed, amorphous silicon layer 4 is generated on third buffer layer 3.In the present embodiment, chemistry is utilized
Gas-phase deposition generates one layer of amorphous silicon layer 4 on third buffer layer 3.This amorphous silicon layer 4 with a thickness of 45nm.
Such as Fig. 6, first the amorphous silicon layer 4 in step S40 can be cleaned before executing step S50.
Such as Fig. 6, step S50 is executed, the 4th buffer layer 5 is generated on amorphous silicon layer 4.In the present embodiment, chemistry is utilized
Gas-phase deposition generates the 4th buffer layer 5 of one layer of fine and close silica material on amorphous silicon layer 4.This 4th buffering
Layer 5 with a thickness of 10nm, extinction coefficient is less than 10-4。
In conjunction with Fig. 7 and Fig. 8, step S60, amor phous silicon layer are executed.In the present embodiment, excimer laser photograph is carried out
It penetrates, with amor phous silicon layer 4, so that amorphous silicon layer 4 is combined with the 4th buffer layer 5 and then forms polysilicon membrane 6.
After polysilicon membrane 6 to be formed, gate insulating layer 7 further can be successively stacked on partial polysilicon film 6
And grid 8, and insulating layer 9 is set on the grid 8 and polysilicon membrane 6, which has two to be open and expose to the open air respectively
It is located at the polysilicon membrane 6 of 8 two sides of grid out.First electrode 11 and second electrode 12 are deposited on insulating layer 9 again
In two openings, and it is connect respectively with the polysilicon membrane 6 of 8 two sides of grid.
Referring to shown in Fig. 8, the invention also discloses a kind of thin film transistor (TFT)s comprising above-mentioned polysilicon membrane, comprising: base
Plate 100；Fine and close first buffer layer 1, is set on substrate 100；Loose second buffer layer 2, is set to first buffer layer 1
On；Fine and close third buffer layer 3, is set in second buffer layer 2；Polysilicon membrane 6 is set on third buffer layer 3；Grid
Insulating layer 7 is set on partial polysilicon film 6；Grid 8 is set on gate insulating layer 7；Insulating layer 9, is set to polycrystalline
On silicon thin film 6 and grid 8, which has two openings, exposes the polysilicon membrane 6 positioned at 8 two sides of grid respectively；With
And first electrode 11 and second electrode, it is located in two openings of insulating layer 9, and thin with the polysilicon of 8 two sides of grid respectively
Film 6 connects.
Specifically, first buffer layer 1 and third buffer layer 3 are all extinction coefficient less than 10-4Silicon dioxide layer；And second
Buffer layer 2 is extinction coefficient 10-2~10-4Silicon dioxide layer.First buffer layer 1, second buffer layer 2 and third buffer layer 3
With a thickness of 50nm~100nm；And polysilicon membrane 6 with a thickness of 40nm~50nm.
In conjunction with Fig. 7, more preferably, second buffer layer 2 is laid in first buffer layer 1, and polysilicon membrane 6 is by upper
The amorphous silicon layer 4 stated is formed with 5 crystallization of the 4th buffer layer, and gate insulating layer 7 and grid are provided on polysilicon membrane 6
8。
The structure of thin film transistor (TFT) of the present invention also can be implemented to make by the method for above-mentioned formation polysilicon membrane.
The present invention, which forms polysilicon membrane method, has following actual effect:
1) it is arranged by the buffer layer of different extinction coefficients, reduces protuberance spot, improves the polysilicon membrane table formed
The uniformity in face；
2) after polysilicon membrane uniformity improves, and then increase the product yield of thin film transistor (TFT)；
The present invention has been described in detail with reference to the accompanying drawings, those skilled in the art can be according to upper
It states and bright many variations example is made to the present invention.Thus, certain details in embodiment should not constitute limitation of the invention, this
Invention will be using the range that the appended claims define as protection scope.
Claims (7)
1. a kind of method for forming polysilicon membrane, which comprises the following steps:
1) first buffer layer is generated on substrate；
2) second buffer layer is generated with interval in the first buffer layer；
3) third buffer layer is generated in the second buffer layer；
4) amorphous silicon layer is generated on the third buffer layer；
5) the 4th buffer layer is generated on the amorphous silicon layer；
6) amorphous silicon layer described in crystallization makes the amorphous silicon layer and the 4th buffer layer form polysilicon membrane；
Wherein, the first buffer layer, the third buffer layer and the 4th buffer layer are all extinction coefficient less than 10-4Two
Silicon oxide layer；The second buffer layer is extinction coefficient 10-2~10-4Silicon dioxide layer.
2. the method according to claim 1 for forming polysilicon membrane, it is characterised in that:
The first buffer layer, the second buffer layer and the third buffer layer with a thickness of 50nm~100nm；Described 4th
Buffer layer with a thickness of 10nm~15nm；The amorphous silicon layer with a thickness of 40nm~50nm.
3. the method according to claim 1 for forming polysilicon membrane, it is characterised in that:
The step 1) generates corresponding layer using chemical vapor deposition principle to step 5).
4. the method according to claim 1 for forming polysilicon membrane, it is characterised in that:
It further include being cleaned to the amorphous silicon layer before step 5) after the step 4).
5. the method according to claim 1 for forming polysilicon, it is characterised in that:
The step 6) is by excimer laser irradiation with amorphous silicon layer described in crystallization.
6. a kind of includes the thin film transistor (TFT) of polysilicon membrane characterized by comprising
Substrate；
First buffer layer is set on the substrate；
Second buffer layer is set to interval in the first buffer layer；
Third buffer layer is set in the second buffer layer；
Polysilicon membrane is set on the third buffer layer；
Gate insulating layer is set on the polysilicon membrane of part；
Grid is set on the gate insulating layer；
Insulating layer is set on the polysilicon membrane and the grid, and the insulating layer has two openings, exposes position respectively
The polysilicon membrane in the grid two sides；And
First electrode and second electrode are located in two openings of the insulating layer, and the institute with the grid two sides respectively
State polysilicon membrane connection；
Wherein, further includes:
Amorphous silicon layer is set on the third buffer layer；
4th buffer layer is set on the amorphous silicon layer, and the 4th buffer layer and the amorphous silicon layer crystallization form described
Polysilicon membrane；
The first buffer layer, the third buffer layer and the 4th buffer layer are all extinction coefficient less than 10-4Titanium dioxide
Silicon layer；The second buffer layer is extinction coefficient 10-2~10-4Silicon dioxide layer.
7. thin film transistor (TFT) according to claim 6, which is characterized in that
The first buffer layer, the second buffer layer and the third buffer layer with a thickness of 50nm~100nm；The polycrystalline
Silicon thin film with a thickness of 40nm~50nm.
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| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN103199111A (en) * | 2012-01-10 | 2013-07-10 | 三星显示有限公司 | Semiconductor device and method of manufacturing the same |
| CN103283006A (en) * | 2011-11-07 | 2013-09-04 | 松下电器产业株式会社 | Method for manufacturing thin film transistor device, thin film transistor device, and display device |
| CN104037127A (en) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | Preparation method for polycrystalline silicon layer and display substrate, and display substrate |
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|---|---|---|---|---|
| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN103283006A (en) * | 2011-11-07 | 2013-09-04 | 松下电器产业株式会社 | Method for manufacturing thin film transistor device, thin film transistor device, and display device |
| CN103199111A (en) * | 2012-01-10 | 2013-07-10 | 三星显示有限公司 | Semiconductor device and method of manufacturing the same |
| CN104037127A (en) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | Preparation method for polycrystalline silicon layer and display substrate, and display substrate |
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