JP5652926B2 - Method for forming gate insulating film and method for manufacturing semiconductor device - Google Patents

Method for forming gate insulating film and method for manufacturing semiconductor device Download PDF

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JP5652926B2
JP5652926B2 JP2013507625A JP2013507625A JP5652926B2 JP 5652926 B2 JP5652926 B2 JP 5652926B2 JP 2013507625 A JP2013507625 A JP 2013507625A JP 2013507625 A JP2013507625 A JP 2013507625A JP 5652926 B2 JP5652926 B2 JP 5652926B2
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行則 森田
行則 森田
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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Description

本発明は、ゲート絶縁膜の形成方法及びこのゲート絶縁膜の形成方法を用いた半導体装置の製造方法に関するものである。   The present invention relates to a method for forming a gate insulating film and a method for manufacturing a semiconductor device using the method for forming a gate insulating film.

近年の集積回路では、ＭＯＳトランジスタのゲート絶縁膜として、ＳｉＯ２に代わり、高誘電率（high-k）の材料よりなるゲート絶縁膜が使用されるようになった。これは、スケーリング則に従い電気的な等価酸化膜厚は薄膜化しつつ、絶縁膜の誘電率を増大させることで、実際の膜厚を増加させ、直接トンネル電流を抑制する手法である。最初の世代のhigh-k材料としては、ＨｆＯ２（酸化ハフニウム、ハフニア；誘電率約１３〜２０）が用いられた。In recent integrated circuits, a gate insulating film made of a material having a high dielectric constant (high-k) is used instead of SiO 2 as a gate insulating film of a MOS transistor. This is a technique for directly suppressing the tunnel current by increasing the actual film thickness by increasing the dielectric constant of the insulating film while reducing the electrical equivalent oxide film thickness according to the scaling law. HfO 2 (hafnium oxide, hafnia; dielectric constant about 13-20) was used as the first generation high-k material.

トランジスタ加工の微細化の進行に伴い、約０．５ｎｍ以下という極薄の等価酸化膜厚が必要とされる世代の技術において、ゲートスタック全体での等価酸化膜厚を薄膜化する手法はいくつか提案されている。   There are several methods to reduce the equivalent oxide thickness of the entire gate stack in the generation technology that requires an extremely thin equivalent oxide thickness of about 0.5 nm or less as transistor processing becomes finer. Proposed.

ひとつは、ある種の金属をドープしたＴｉＮ、ＴａＮ等の合金をゲート電極とし、熱処理時にＨｆＯ２とＳｉとの界面に存在するＳｉＯ２層を、ドープした金属による酸素欠陥注入効果により還元分解し、ＨｆＯ２を直接Ｓｉ上に形成することで、低誘電率の界面ＳｉＯ２層による等価酸化膜厚の増加を抑制する手法である（非特許文献１、２参照）。しかし、この手法では、約０．５ｎｍ以下の等価酸化膜厚を得るためには、低誘電率の界面ＳｉＯ２層を完全に除去したとしても、誘電率１３〜２０程度のhigh-k絶縁膜を直接トンネル電流が流れる領域まで薄膜化する必要が生じるため、この手法は充分なものではない。The first is to use an alloy such as TiN or TaN doped with a certain metal as a gate electrode, and to reduce and decompose the SiO 2 layer present at the interface between HfO 2 and Si during heat treatment by the oxygen defect injection effect of the doped metal. In this method, HfO 2 is formed directly on Si to suppress an increase in equivalent oxide thickness due to the low dielectric constant interface SiO 2 layer (see Non-Patent Documents 1 and 2). However, in this method, in order to obtain an equivalent oxide thickness of about 0.5 nm or less, even if the interface SiO 2 layer having a low dielectric constant is completely removed, a high-k insulating film having a dielectric constant of about 13 to 20 is used. This method is not sufficient because it is necessary to reduce the film thickness to a region where the tunnel current directly flows.

近年研究が進められているのが、従来のhigh-k材料よりも誘電率の高い絶縁層（higher-k材料、誘電率３０以上）を用いる手法である。higher-kゲート絶縁膜を形成する手法はすでに提案されている（特許文献１参照）。この手法は、例えばＨｆＯ２膜上に保護膜を堆積した上で急速熱処理を行い、ＨｆＯ２膜中で高誘電率の結晶相（立方晶相）を優先的に生成するというものである。しかし、この手法では、ゲート絶縁膜としてのＨｆＯ２と半導体基板としてのＳｉとの界面に、ＨｆＯ２が結晶化する際に放出された酸素によってＳｉＯ２層が形成され、ゲートスタック全体での等価酸化膜厚が増加してしまうという問題が存在し、極薄の等価酸化膜厚の実現は困難である。In recent years, research is progressing on a technique using an insulating layer (higher-k material, dielectric constant 30 or more) having a higher dielectric constant than that of a conventional high-k material. A method of forming a higher-k gate insulating film has already been proposed (see Patent Document 1). This approach, for example, performs a rapid thermal after having deposited a protective film on the HfO 2 film, is the crystalline phase of the high dielectric constant HfO 2 film in (cubic phase) those that preferentially generated. However, in this method, an SiO 2 layer is formed at the interface between HfO 2 as a gate insulating film and Si as a semiconductor substrate by oxygen released when HfO 2 is crystallized, and the equivalent of the entire gate stack is formed. There is a problem that the oxide film thickness increases, and it is difficult to realize an extremely thin equivalent oxide film thickness.

特開２００８−３０６０３６号公報JP 2008-306036 A

K.Choi et al., Tech.Dig VLSISymp., 2009,pg.138.K. Choi et al., Tech.Dig VLSISymp., 2009, pg.138. T.Ando et al., IEDM O9-423〜426T.Ando et al., IEDM O9-423〜426

本発明は、ＨｆＯ２層をゲート絶縁膜とするゲート絶縁膜の形成方法において、界面にＳｉＯ２層が形成されない、極薄の等価酸化膜厚を持ったhigher-kのゲートスタックを実現するゲート絶縁膜の形成方法を、当該ゲート絶縁膜の形成方法を用いた半導体装置の製造方法と共に提供することを目的とする。The present invention relates to a method for forming a gate insulating film using an HfO 2 layer as a gate insulating film, and a gate that realizes a higher-k gate stack having an extremely thin equivalent oxide film thickness without an SiO 2 layer formed at the interface. An object of the present invention is to provide a method for forming an insulating film together with a method for manufacturing a semiconductor device using the method for forming a gate insulating film.

上記の課題を解決する本発明のゲート絶縁膜の形成方法は、シリコン基板上にＨｆＯ２層を原子層成長法により形成する工程と、このＨｆＯ２層上に酸素吸収効果のある酸素制御金属層を形成する工程と、ＨｆＯ２層が結晶化する温度に加熱する熱処理をする工程とを含み、かつ、前記熱処理をする工程より前に、ＨｆＯ２層中に含まれる結晶成長核の量を制御することを特徴とする。 The method for forming a gate insulating film of the present invention that solves the above problems includes a step of forming an HfO 2 layer on a silicon substrate by an atomic layer growth method, and an oxygen control metal layer having an oxygen absorption effect on the HfO 2 layer. forming a, and a step of heat treatment of heating to a temperature of HfO 2 layer is crystallized, and, before the step of the heat treatment, control the amount of crystal growth nuclei contained in the HfO 2 layer in It is characterized by doing.

本発明のゲート絶縁膜の形成方法においては、結晶成長核の量の制御を、形成するＨｆＯ２層の膜厚を低減することにより行うことができる。
また、上記の熱処理は、ＨｆＯ２層を結晶化してＨｆＯ２層の誘電率を増大させるとともに、当該熱処理時にＨｆＯ２層から放出される酸素を前記酸素制御金属層で吸収しかつ、ＨｆＯ２格子からの酸素除去効果を用いてＨｆＯ２／Ｓｉ界面に形成されるＳｉＯ２を除去する熱処理とすることができる。
更に、酸素吸収効果のある酸素制御金属層は、Ｔｉ層、Ｈｆ層及びＺｒ層から選ばれる１種の金属層又はＨｆＮ及びＡｌＮから選ばれる一種の金属窒化物層であることが好ましい。
また、本発明のゲート絶縁膜の形成方法は、熱処理の前に、酸素制御金属層上にゲート電極層を形成する工程を含む構成とすることができる。
また、本発明の半導体装置の製造方法は、上述した本発明のゲート絶縁膜の形成方法によりゲート絶縁膜を形成する工程を含むものである。In the method for forming a gate insulating film of the present invention, the amount of crystal growth nuclei can be controlled by reducing the thickness of the HfO 2 layer to be formed.
Further, the above heat treatment, along with increasing the dielectric constant of the HfO 2 layer by crystallizing the HfO 2 layer, vital absorb oxygen released from the HfO 2 layer during the heat treatment in the oxygen-controlled metal layer, HfO 2 grid It is possible to perform a heat treatment for removing SiO 2 formed at the HfO 2 / Si interface by using the effect of removing oxygen from the surface.
Furthermore, the oxygen control metal layer having an oxygen absorption effect is preferably one kind of metal layer selected from Ti layer, Hf layer and Zr layer or one kind of metal nitride layer selected from HfN and AlN.
In addition, the method for forming a gate insulating film of the present invention can include a step of forming a gate electrode layer on the oxygen control metal layer before the heat treatment.
The method for manufacturing a semiconductor device of the present invention includes a step of forming a gate insulating film by the above-described method for forming a gate insulating film of the present invention.

本発明によれば、ＨｆＯ２層上に酸素吸収効果のある酸素制御金属層を形成し、かつ、急速加熱により結晶化させる熱処理を行うことにより、界面にＳｉＯ２層は形成させることなく、極薄の等価酸化膜厚を持ったhigher-kゲートスタックが実現できる。According to the present invention, an oxygen control metal layer having an oxygen absorption effect is formed on the HfO 2 layer, and a heat treatment for crystallization by rapid heating is performed, so that no SiO 2 layer is formed at the interface, A higher-k gate stack with a thin equivalent oxide thickness can be realized.

図１は、本発明に係るゲート絶縁膜の形成方法を説明する模式的な断面図である。FIG. 1 is a schematic cross-sectional view illustrating a method for forming a gate insulating film according to the present invention. 図２は、成膜時のＨｆＯ２層の厚さと熱処理後の結晶相との関係を説明する時系列的な模式図である。FIG. 2 is a time-series schematic diagram illustrating the relationship between the thickness of the HfO 2 layer during film formation and the crystal phase after heat treatment. 図３は、ＨｆＯ２層の不純物量を説明する模式図である。FIG. 3 is a schematic diagram illustrating the amount of impurities in the HfO 2 layer. 図４は、実施例におけるゲートスタックの模式的な断面図である。FIG. 4 is a schematic cross-sectional view of the gate stack in the embodiment. 図５は、実施例のＣＶ特性を示すグラフである。FIG. 5 is a graph showing the CV characteristics of the example.

本発明に係るゲート絶縁膜の形成方法及び半導体装置の製造方法の実施形態について、図面を参照して詳細に説明する。
図１に示すように、半導体基板としてのシリコン基板１上に、ゲート絶縁膜となるアモルファスＨｆＯ２層２を形成する（図１（ａ））。このアモルファスＨｆＯ２層２は、原子層成長（Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｔｉｏｎ；ＡＬＤ）法により形成する。
ＨｆＯ２層２の形成には、原子層成長法の他に、スパッタリング法もあり、スパッタリング法のほうが原子層成長法よりも成膜されるＨｆＯ２層中の不純物量が少ない。しかし、原子層成長法は、スパッタリング法よりも３００ｍｍといった大径のシリコンウェファの面内均一性に優れ、よって量産に適していて、実際にも一般的に用いられている。したがって、本発明は、実際の量産に適した方法であるために、原子層成長法によりアモルファスＨｆＯ２層２を形成する。Embodiments of a method for forming a gate insulating film and a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, an amorphous HfO 2 layer 2 serving as a gate insulating film is formed on a silicon substrate 1 as a semiconductor substrate (FIG. 1A). The amorphous HfO 2 layer 2 is formed by an atomic layer deposition (ALD) method.
For the formation of the HfO 2 layer 2, there is a sputtering method in addition to the atomic layer growth method, and the amount of impurities in the HfO 2 layer to be formed is smaller in the sputtering method than in the atomic layer growth method. However, the atomic layer growth method is excellent in in-plane uniformity of a silicon wafer having a large diameter of 300 mm as compared with the sputtering method, and is therefore suitable for mass production, and is generally used in practice. Therefore, since the present invention is a method suitable for actual mass production, the amorphous HfO 2 layer 2 is formed by the atomic layer growth method.

次に、このＨｆＯ２層２上に酸素吸収効果のある酸素制御金属層３を形成する（図１（ｂ））。この酸素制御金属層３は、後で行う熱処理時の保護膜としての効果を有するとともに、当該熱処理時にＨｆＯ２層２より生じる酸素を吸収する効果を有している。この酸素制御金属層３は、酸素吸収効果を有する金属層又は当該金属層と同様の酸素吸収効果を有する金属窒化物層からなり、例えば、Ｔｉ層、Ｈｆ層及びＺｒ層から選ばれる１種の金属層又はＨｆＮ及びＡｌＮから選ばれる一種の金属窒化物層であることが好ましい。酸素制御金属層３は、蒸着、イオンプレーティング、スパッタリング等によって形成することができる。酸素制御金属層３の膜厚は１〜１００ｎｍ程度とすることができる。より好ましい膜厚は、１０〜１００ｎｍ程度である。Next, an oxygen control metal layer 3 having an oxygen absorption effect is formed on the HfO 2 layer 2 (FIG. 1B). The oxygen control metal layer 3 has an effect as a protective film at the time of a heat treatment performed later, and also has an effect of absorbing oxygen generated from the HfO 2 layer 2 at the time of the heat treatment. The oxygen control metal layer 3 is composed of a metal layer having an oxygen absorption effect or a metal nitride layer having an oxygen absorption effect similar to that of the metal layer. For example, the oxygen control metal layer 3 is selected from a Ti layer, a Hf layer, and a Zr layer. A metal layer or a kind of metal nitride layer selected from HfN and AlN is preferable. The oxygen control metal layer 3 can be formed by vapor deposition, ion plating, sputtering, or the like. The film thickness of the oxygen control metal layer 3 can be about 1 to 100 nm. A more preferable film thickness is about 10 to 100 nm.

酸素制御金属層３が形成された後、ＨｆＯ２層２が結晶化する温度に加熱する熱処理を行う（図１（ｃ））。この熱処理は、アモルファスＨｆＯ２層２を結晶化させ、アモルファスＨｆＯ２よりも誘電率の高い結晶相よりなるＨｆＯ２層４を優先的に生成させるための急速熱処理である。熱処理は、例えばＮ２（窒素ガス）雰囲気で４００〜１０００℃、好ましくは８００〜９００℃程度で行う。ＨｆＯ２の結晶相には、立方晶（ｃｕｂｉｃ）相、単斜晶（ｍｏｎｏｃｌｉｎｉｃ）相などがあり、なかでも、立方晶相である場合に、高誘電率が得られる。上記熱処理は、ＨｆＯ２層２を結晶化して立方晶相のＨｆＯ２層４を得ることにより、ＨｆＯ２層の誘電率を増大させるための熱処理である。After the oxygen control metal layer 3 is formed, heat treatment is performed to heat to a temperature at which the HfO 2 layer 2 is crystallized (FIG. 1C). This heat treatment is a rapid heat treatment for crystallizing the amorphous HfO 2 layer 2 and preferentially generating the HfO 2 layer 4 having a crystal phase having a dielectric constant higher than that of the amorphous HfO 2 . The heat treatment is performed, for example, in an N 2 (nitrogen gas) atmosphere at 400 to 1000 ° C., preferably about 800 to 900 ° C. The crystal phase of HfO 2 includes a cubic phase, a monoclinic phase, and the like, and in particular, a high dielectric constant is obtained when the phase is a cubic phase. The heat treatment is a heat treatment for increasing the dielectric constant of the HfO 2 layer by crystallizing the HfO 2 layer 2 to obtain the HfO 2 layer 4 having a cubic phase.

また、上記熱処理は、熱処理時にＨｆＯ２層２から放出される酸素を酸素制御金属層３で吸収しかつ、ＨｆＯ２格子からの酸素除去効果を用いてＨｆＯ２／Ｓｉ界面に形成されるＳｉＯ２を除去する熱処理である。より詳しく説明すると、熱処理によりアモルファスＨｆＯ２層２が立方晶相のＨｆＯ２層４に結晶化するとき、結晶格子の組み換えに伴って生じる過剰な酸素がＨｆＯ２層２から放出される。この酸素はＨｆＯ２層２とシリコン基板１との界面においてシリコン基板１を酸化し、ＳｉＯ２の内部層を形成してしまう。ＳｉＯ２はゲート絶縁膜としては立方晶相のＨｆＯ２層４よりも低誘電率であり、ゲートスタック全体での等価酸化膜厚が増加するため、ゲート絶縁膜の高誘電率化には不適である。この点について本発明では、ＨｆＯ２層２上に酸素制御金属層３を形成しているため、ＨｆＯ２層２から放出される酸素を酸素制御金属層３で直接吸収する。このことにより、ＨｆＯ２／Ｓｉ界面におけるＳｉＯ２の形成を抑制する。また、仮にＳｉＯ２の内部層が形成したとしても、酸素制御金属層３が形成されていることによりＨｆＯ２層４のＨｆＯ２格子から酸素を除去し、酸素欠陥（Ｖｏ）をＨｆＯ２層４中に導入することにより、ＨｆＯ２／Ｓｉ界面に形成されたＳｉＯ２を還元分解して除去する。In the above heat treatment, oxygen released from the HfO 2 layer 2 during the heat treatment is absorbed by the oxygen control metal layer 3 and SiO 2 formed at the HfO 2 / Si interface using the effect of removing oxygen from the HfO 2 lattice. It is the heat processing which removes. More specifically, when the amorphous HfO 2 layer 2 is crystallized into the cubic HfO 2 layer 4 by heat treatment, excess oxygen generated by recombination of the crystal lattice is released from the HfO 2 layer 2. This oxygen oxidizes the silicon substrate 1 at the interface between the HfO 2 layer 2 and the silicon substrate 1 and forms an inner layer of SiO 2 . Since SiO 2 has a lower dielectric constant than the cubic HfO 2 layer 4 as a gate insulating film, and the equivalent oxide film thickness of the entire gate stack increases, it is not suitable for increasing the dielectric constant of the gate insulating film. is there. In the present invention this regard, because it forms an oxygen control metal layer 3 on the HfO 2 layer 2, directly absorb the oxygen released from the HfO 2 layer 2 by an oxygen control metal layer 3. Thus, to suppress the formation of SiO2 in the HfO 2 / Si interface. Even if the inner layer of SiO 2 is formed, the oxygen control metal layer 3 is formed, so that oxygen is removed from the HfO 2 lattice of the HfO 2 layer 4 and oxygen defects (Vo) are removed from the HfO 2 layer 4. By introducing it, SiO 2 formed at the HfO 2 / Si interface is reduced and removed by reductive decomposition.

したがって、本発明では、ＨｆＯ２層２上に保護層として酸素制御金属層３を形成してから、結晶化する温度に加熱する熱処理を行ってＨｆＯ２層２を立方晶相に結晶化することにより高誘電率の立方晶相が生成すること、及び、ＨｆＯ２層２とシリコン基板１との間に低誘電率のＳｉＯ２が形成することを抑制してＨｆＯ２層２が直接シリコン基板１と接するようにすることにより、ゲート絶縁膜を高誘電率とすることができる。Therefore, in the present invention, after forming the oxygen control metal layer 3 as a protective layer on the HfO 2 layer 2, a heat treatment is performed to heat to the crystallization temperature to crystallize the HfO 2 layer 2 into a cubic phase. The formation of a high dielectric constant cubic phase and the formation of a low dielectric constant SiO 2 between the HfO 2 layer 2 and the silicon substrate 1 suppress the HfO 2 layer 2 directly from the silicon substrate 1. By making contact with the gate insulating film, the gate insulating film can have a high dielectric constant.

本発明のゲート絶縁膜の形成方法は、熱処理工程より前に、ＨｆＯ２層中に含まれる結晶成長核の量を制御する。発明者の研究によれば、シリコン基板上のＨｆＯ２層２の形成が、スパッタリング法による場合には、上記の熱処理により立方晶相のＨｆＯ２層４を容易に得ることができるが、原子層成長法による場合には、上記の熱処理により立方晶相を容易に得るのが難しかった。その原因について発明者が研究したところ、図２（ａ）に示すように従来の原子層成長法によりＨｆＯ２層１０２を形成した場合には、ＨｆＯ２層１０２中の不純物が、スパッタリング法に比べて多く、このＨｆＯ２層１０２中の不純物を成長核として単斜晶相が立方晶相よりも優先して生成してしまうためであることが判明した。単斜晶相は、立方晶相よりも低誘電率の結晶相であり、単斜晶相が立方晶相に優先して生成しＨｆＯ２層１０２中を占めると、高誘電率のゲート絶縁膜を得るのが困難である。そこで本発明では、熱処理工程より前に、ＨｆＯ２層中に含まれる結晶成長核の量を制御している。これにより、立方晶相を優先的に生成する。In the method for forming a gate insulating film of the present invention, the amount of crystal growth nuclei contained in the HfO 2 layer is controlled before the heat treatment step. According to the inventor's research, when the formation of the HfO 2 layer 2 on the silicon substrate is performed by the sputtering method, the cubic HfO 2 layer 4 can be easily obtained by the above heat treatment. In the case of the growth method, it has been difficult to easily obtain a cubic phase by the heat treatment. The inventors have studied the cause, and as shown in FIG. 2A, when the HfO 2 layer 102 is formed by the conventional atomic layer growth method, impurities in the HfO 2 layer 102 are compared with the sputtering method. It has been found that the monoclinic phase is preferentially generated over the cubic phase using the impurities in the HfO 2 layer 102 as growth nuclei. The monoclinic phase is a crystal phase having a lower dielectric constant than the cubic phase. When the monoclinic phase is generated in preference to the cubic phase and occupies the HfO 2 layer 102, the gate insulating film having a high dielectric constant is obtained. Is difficult to get. Therefore, in the present invention, the amount of crystal growth nuclei contained in the HfO 2 layer is controlled before the heat treatment step. Thereby, a cubic phase is preferentially generated.

熱処理工程より前に行うＨｆＯ２層中に含まれる結晶成長核の量の制御は、より具体的には、ＨｆＯ２層中で結晶成長核となる不純物の量を減少させることである。ＨｆＯ２層中の不純物の量を減少させる具体的な手段の一つは、図２（ｂ）に示すように、シリコン基板１上にＨｆＯ２層を原子層成長法により形成する際に、ＨｆＯ２層２の厚さを薄くすることである。ＨｆＯ２層２は、成膜装置、成膜プロセス等によって定まる成膜条件により、所定の不純物密度を有している。一例として、図３に示すように、原子層成長法によりシリコン基板上に堆積させて形成したＨｆＯ２層２は、厚さ１ｎｍのＨｆＯ２層の単位面積（ｃｍ２）当たりの残留不純物が、およそ１×１０１３個程度である。したがって、従来のように８．７ｎｍ程度の厚さでは、単位面積（ｃｍ２）当たり８．７×１０１３個程度の不純物、換言すれば単斜晶相の結晶成長核が存在することになる。このＨｆＯ２層の厚さを２．４ｎｍにすれば、単位面積（ｃｍ２）当たり２．４×１０１３個程度の不純物、換言すれば単斜晶相の結晶成長核が存在することになり、従来の三分の一以下の結晶成長核数になる。したがって、熱処理後は、ＨｆＯ２層２を誘電率の高い立方晶にすることができる。More specifically, the control of the amount of crystal growth nuclei contained in the HfO 2 layer performed before the heat treatment step is to reduce the amount of impurities serving as crystal growth nuclei in the HfO 2 layer. As a specific means for reducing the amount of impurities in the HfO 2 layer, as shown in FIG. 2B, when forming the HfO 2 layer on the silicon substrate 1 by atomic layer growth, HfO 2 is used. The thickness of the two layers 2 is reduced. The HfO 2 layer 2 has a predetermined impurity density according to film forming conditions determined by a film forming apparatus, a film forming process, and the like. As an example, as shown in FIG. 3, the HfO 2 layer 2 formed by depositing on the silicon substrate by the atomic layer growth method has a residual impurity per unit area (cm 2 ) of the 1 nm thick HfO 2 layer. About 1 × 10 13 pieces. Therefore, when the thickness is about 8.7 nm as in the prior art, there are about 8.7 × 10 13 impurities per unit area (cm 2 ), in other words, monoclinic crystal growth nuclei. . If the thickness of the HfO 2 layer is 2.4 nm, there are about 2.4 × 10 13 impurities per unit area (cm 2 ), in other words, monoclinic crystal growth nuclei. The number of crystal growth nuclei is 1/3 or less of the conventional one. Therefore, after the heat treatment, the HfO 2 layer 2 can be made into a cubic crystal having a high dielectric constant.

本発明により、量産に適した原子層成長法を用いてシリコン基板上に、ＳｉＯ２の内部層を介在させることなく立方晶のＨｆＯ２層が容易に得られ、高誘電率が得られた。According to the present invention, a cubic HfO 2 layer was easily obtained on a silicon substrate by using an atomic layer growth method suitable for mass production without interposing an SiO 2 inner layer, and a high dielectric constant was obtained.

本発明において、ＨｆＯ２層中の不純物の量を減少させる具体的な手段は、ＨｆＯ２層２の厚さを薄くすることに限られない。他の手段には、シリコン基板１上に原子層成長法によりＨｆＯ２層２を形成した後、結晶化のための熱処理の前に、結晶化が生じない温度にＨｆＯ２層２を加熱することが考えられる。結晶化が生じない温度に加熱すれば、ＨｆＯ２層２中の不純物量、結晶成長核量を減少させることができる。In the present invention, specific means for reducing the amount of impurities in the HfO 2 layer in is not limited to reducing the thickness of the HfO 2 layer 2. As another means, after the HfO 2 layer 2 is formed on the silicon substrate 1 by atomic layer growth, the HfO 2 layer 2 is heated to a temperature at which crystallization does not occur before the heat treatment for crystallization. Can be considered. By heating to a temperature at which crystallization does not occur, the amount of impurities and the amount of crystal growth nuclei in the HfO 2 layer 2 can be reduced.

ゲート絶縁膜としてＨｆＯ２層を含む本発明の半導体装置の製造方法は、ＨｆＯ２層４上にゲート電極層５を形成する工程を含む。このゲート電極層５は、ＨｆＯ２層４上に保護層としての酸素吸収効果のある酸素制御金属層３が形成されている場合には、この酸素制御金属層３上に形成してもよいし、また、ＨｆＯ２層４上の酸素制御金属層３を除去して、ＨｆＯ２層４に接して当該ＨｆＯ２層４上に形成してもよい。ゲート電極層５はＴｉＮ電極層やＴａＮ電極層を例示することができる。もっとも、ゲート電極層５の材料は、ＴｉＮやＴａＮに限定されることなく、ＭＯＳトランジスタに用いられる公知の材料を用いることができる。また、ｐＭＯＳトランジスタのゲート電極層５とｎＭＯＳトランジスタのゲート電極層５とで、異なる材料を用いてもよい。ゲート電極層５の形成は、上述したＨｆＯ２層の結晶化のための熱処理の前に行えばよい。The manufacturing method of the semiconductor device of the present invention including the HfO 2 layer as the gate insulating film includes a step of forming the gate electrode layer 5 on the HfO 2 layer 4. The gate electrode layer 5 may be formed on the oxygen control metal layer 3 when the oxygen control metal layer 3 having an oxygen absorption effect as a protective layer is formed on the HfO 2 layer 4. , also by removing the oxygen control metal layer 3 on the HfO 2 layer 4 may be formed on the HfO 2 layer 4 in contact with the HfO 2 layer 4. Examples of the gate electrode layer 5 include a TiN electrode layer and a TaN electrode layer. However, the material of the gate electrode layer 5 is not limited to TiN or TaN, and any known material used for MOS transistors can be used. Different materials may be used for the gate electrode layer 5 of the pMOS transistor and the gate electrode layer 5 of the nMOS transistor. The formation of the gate electrode layer 5 may be performed before the heat treatment for crystallization of the HfO 2 layer described above.

（実施例１）
トランジスタの製造に当たり、図４（ａ）に本発明の一実施例のゲートスタックの模式的な断面図を示すように、シリコン基板１１上にＨｆＯ２層を原子層成長法により厚さ２．４ｎｍで形成した。次いでＨｆＯ２層上に酸素制御金属層としてＴｉ層を厚さ６ｎｍで形成した。次いでＴｉ層上にゲート電極層としてＴｉＮ層を厚さ１０ｎｍで形成した。
ＴｉＮ層を形成後、熱処理を９００℃に急速加熱して行った。
熱処理後のＨｆＯ２層をＸＲＤ装置により分析したところ、ＨｆＯ２層は立方晶相となっていた。また、ＨｆＯ２層とシリコン基板との界面にＳｉＯ２の内部層は存在していなかった。
熱処理後のＨｆＯ２層の比誘電率は４０、トランジスタ向けゲートスタックとしての等価酸化膜厚は０．２５ｎｍであった。Example 1
In manufacturing the transistor, as shown in a schematic cross-sectional view of the gate stack of one embodiment of the present invention in FIG. 4A, an HfO 2 layer is 2.4 nm thick on the silicon substrate 11 by atomic layer growth. Formed with. Next, a Ti layer having a thickness of 6 nm was formed as an oxygen control metal layer on the HfO 2 layer. Next, a TiN layer having a thickness of 10 nm was formed as a gate electrode layer on the Ti layer.
After forming the TiN layer, heat treatment was performed by rapidly heating to 900 ° C.
When the HfO 2 layer after the heat treatment was analyzed with an XRD apparatus, the HfO 2 layer was in a cubic phase. Further, no SiO 2 inner layer was present at the interface between the HfO 2 layer and the silicon substrate.
The relative dielectric constant of the HfO 2 layer after heat treatment was 40, and the equivalent oxide thickness as a gate stack for transistors was 0.25 nm.

（実施例２）
図４（ｂ）に本発明の別の実施例のゲートスタックの模式的な断面図を示すように、実施例１のＴｉ層の代わりに酸素制御金属層としてＨｆ層を厚さ６ｎｍで形成した以外は実施例１と同様にして、ゲートスタックを形成した。
熱処理後のＨｆＯ２層をＸＲＤ装置により分析したところ、ＨｆＯ２層は立方晶相となっていた。また、ＨｆＯ２層とシリコン基板との界面にＳｉＯ２の内部層は存在していなかった。
熱処理後のＨｆＯ２層の比誘電率は４０、トランジスタ向けゲートスタックとしての等価酸化膜厚は０．２５ｎｍであった。(Example 2)
As shown in the schematic cross-sectional view of the gate stack of another embodiment of the present invention in FIG. 4B, an Hf layer having a thickness of 6 nm was formed as an oxygen control metal layer instead of the Ti layer of the first embodiment. A gate stack was formed in the same manner as in Example 1 except for the above.
When the HfO 2 layer after the heat treatment was analyzed with an XRD apparatus, the HfO 2 layer was in a cubic phase. Further, no SiO 2 inner layer was present at the interface between the HfO 2 layer and the silicon substrate.
The relative dielectric constant of the HfO 2 layer after heat treatment was 40, and the equivalent oxide thickness as a gate stack for transistors was 0.25 nm.

図５に、実施例１及び実施例２で形成したゲートスタックのＣＶ特性の測定結果を示す。図５（ａ）に示す実施例１及び図５（ｂ）に示す実施例２のＣＶ特性は、良好であった。   FIG. 5 shows the measurement results of the CV characteristics of the gate stacks formed in Example 1 and Example 2. The CV characteristics of Example 1 shown in FIG. 5A and Example 2 shown in FIG. 5B were good.

１ シリコン基板
２ ＨｆＯ２層
３ 酸素制御金属層
４ ＨｆＯ２層
５ ゲート電極層DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 HfO 2 layer 3 Oxygen control metal layer 4 HfO 2 layer 5 Gate electrode layer

Claims (6)

シリコン基板上にＨｆＯ２層を原子層成長法により形成する工程と、
このＨｆＯ２層上に酸素吸収効果のある酸素制御金属層を形成する工程と、
ＨｆＯ２層が結晶化する温度に加熱する熱処理をする工程と
を含み、かつ、
前記熱処理をする工程より前に、ＨｆＯ２層中に含まれる結晶成長核の量を制御することを特徴とするゲート絶縁膜の形成方法。 Forming an HfO 2 layer on a silicon substrate by atomic layer deposition;
Forming an oxygen control metal layer having an oxygen absorption effect on the HfO 2 layer;
And a heat treatment for heating to a temperature at which the HfO 2 layer crystallizes, and
Wherein before the step of heat treatment, a method of forming the gate insulating film, characterized by controlling the amount of crystal growth nuclei contained in HfO 2 layer in. 前記結晶成長核の量の制御を、形成するＨｆＯ２層の膜厚を低減することにより行う請求項１記載のゲート絶縁膜の形成方法。 2. The method of forming a gate insulating film according to claim 1, wherein the amount of the crystal growth nuclei is controlled by reducing the film thickness of the HfO 2 layer to be formed. 前記熱処理は、ＨｆＯ２層を結晶化してＨｆＯ２層の誘電率を増大させるとともに、当該熱処理時にＨｆＯ２層から放出される酸素を前記酸素制御金属層で吸収しかつ、ＨｆＯ２格子からの酸素除去効果を用いてＨｆＯ２／Ｓｉ界面に形成されるＳｉＯ２を除去するものである請求項１記載のゲート絶縁膜の形成方法。 The heat treatment, along with increasing the dielectric constant of the HfO 2 layer by crystallizing the HfO 2 layer, oxygen of oxygen released from the HfO 2 layer during the heat treatment from absorbing vital, HfO 2 lattice by the oxygen control metal layer 2. The method for forming a gate insulating film according to claim 1, wherein SiO 2 formed at the HfO 2 / Si interface is removed by using a removing effect. 前記酸素吸収効果のある酸素制御金属層は、Ｔｉ層、Ｈｆ層及びＺｒ層から選ばれる１種の金属層又はＨｆＮ及びＡｌＮから選ばれる一種の金属窒化物層である請求項１記載のゲート絶縁膜の形成方法。   2. The gate insulation according to claim 1, wherein the oxygen-controlling metal layer having an oxygen absorption effect is one kind of metal layer selected from a Ti layer, an Hf layer, and a Zr layer, or one kind of metal nitride layer selected from HfN and AlN. Method for forming a film. 前記熱処理の前に、酸素制御金属層上にゲート電極層を形成する工程を含むことを特徴とする請求項１記載のゲート絶縁膜の形成方法。   2. The method of forming a gate insulating film according to claim 1, further comprising a step of forming a gate electrode layer on the oxygen control metal layer before the heat treatment. 請求項１に記載のゲート絶縁膜の形成方法によりゲート絶縁膜を形成する工程を含む半導体装置の製造方法。   A method for manufacturing a semiconductor device, comprising: forming a gate insulating film by the method for forming a gate insulating film according to claim 1.
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