CN105977301A - 一种体内栅型mos - Google Patents
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Abstract
本发明属于功率半导体技术领域，特别涉及一种体内栅型MOS。传统功率MOS器件的栅极和沟道位于器件表面或接近表面，源极区域也通常位于器件表面，而该发明定义一种新型沟道导通方式，将栅极和源极区域、漏极区域完全置于器件体内，并通过槽栅金属外接电极，极大地降低了器件的栅漏电容Cgd、栅源电容Cgs，由于正向导通时，导通电流直接通过槽栅金属，该结构的导通电阻和传统MOS相比更低。反向耐压时，器件的耐压机理和PIN二极管类似，低掺杂外延层可以承受较高的耐压。
Description
技术领域
本发明属于功率半导体技术领域，特别涉及一种体内栅型MOS。
背景技术
传统的功率VDMOS器件通常可以分为平面栅型VDMOS和槽栅型VDMOS器件。而这两种类型的MOS器件的源极区域和漏极区域都位于器件结构的正面或者背面，在器件开关状态时，栅漏电容Cgd、栅源电容Cgs会由于外加电压的变化而变化，从而漏极电压的振荡会引起感应额栅电位变化，影响器件在高频工作条件下的开关性能。
目前国际上，很多新结构都让平面栅型MOS和槽栅型MOS的电容有所改善，例如TI公司在2010年推出的NexFET结合了横向器件LDMOS和纵向器件DMOS的优点：LDMOS特有的低Qgd特性，可以实现极低的FOM值，而垂直电流可提供高电流密度。NexFET结构的源极金属可以发挥场板(field-plate)效应，降低沟道区域的峰值电场。利用LDD区、场板及下方深P区域的电荷平衡，可以提高LDD区域掺杂浓度。这有助于将器件漏源通态电阻Rdson降至最低。但NexFET结构元胞尺寸较大，芯片面积相比较大，而且制造工艺复杂，成本高昂。
发明内容
本发明提出一种新型体内栅型MOS，该发明将源漏之间的导电沟道移至器件体内，源漏区域也均位于器件体内，并通过槽栅金属电极接外加电位，极大减小了正向导通电阻。器件反向偏置时的低掺杂P型外延承受耐压，由于电场接近于理想PIN结的电场，该结构的反向耐压提高。
本发明的技术方案如下：
一种体内栅型MOS，包括从下至上依次层叠设置的漏极电极11、N型重掺杂单晶硅衬底12、低掺杂P型外延层5、高掺杂P+源区2和源极金属电极1；所述掺杂P型外延层5中具有条形源区6和条形漏区9，所述条形源区6和条形漏区9位于同一水平面，且条形源区6和条形漏区9之间通过多晶硅栅7连接，所述多晶硅栅7通过栅氧化层8与低掺杂P型外延层5隔离；所述条形源区6通过贯穿高掺杂P+源区2的第一深槽金属3与源极金属电极1连接，所述第一深槽金属3通过第一氧化层4与低掺杂P型外延层5和高掺杂P+源区2隔离；所述条形漏区9通过贯穿N型重掺杂单晶硅衬底12的第二深槽金属10与漏极电极11连接，所述第二深槽金属10通过第二氧化层13与低掺杂P型外延层5和N型重掺杂单晶硅衬底12隔离；所述多晶硅栅7通过第三深槽金属14连接外加栅电位，所述第三深槽金属14通过第三氧化层15与低掺杂P型外延层5和高掺杂P+源区2隔离。
进一步的，所述多晶硅栅7的结深小于条形源区6和条形漏区9的结深。
进一步的，所述低掺杂P型外延层5与N型重掺杂单晶硅衬底12之间具有高掺杂P区。
进一步的，所述低掺杂P型外延层5的掺杂浓度低于N+衬底12的掺杂浓度至少两个数量级。
进一步的，所述第一深槽金属3和第二深槽金属10呈条形分布结构或分散结构。
进一步的，所述第三深槽金属14仅位于结构的边缘处。
本发明的有益效果为，本发明通过将源漏区域置于器件体内，不仅降低了器件漏源通态电阻Rdson，还极大地降低了栅漏电容Cgd、栅源电容Cgs。利用类PIN结构反向耐压，电场完全横向，提高了器件的击穿电压，解决了传统功率MOS小的导通电阻和高耐压的矛盾。
附图说明
图1是本发明所提供的一种新型体内栅型MOS的结构示意图；
图2是本发明所提供的一种新型体内栅型MOS的三维结构示意图；
图3是本发明所提供的一种新型体内栅型MOS沿着图2所示剖面的结构示意图；
图4是本发明所提供的一种新型体内栅型MOS正向导通时的电流线路径图；
图5是本发明所提供的一种新型体内栅型MOS的扩展结构示意图，以及浓度示意图；
图6是本发明高能离子注入工艺流程中形成条形源漏区域后的结构示意图；
图7是本发明刻蚀工艺流程中形成用于栅极生长的深槽区域后的结构示意图；
图8是本发明生长完栅氧化层和栅电极后的结构示意图；
图9是本发明深槽内外延工艺流程后的结构示意图；
图10是本发明刻蚀工艺流程中形成用于外接源漏极深槽的结构示意图；
图11是本发明填充源漏极金属电极后的结构示意图；
图12是本发明表面注入P+离子后的结构示意图；
图13是本发明背部减薄以及表面金属化之后的结构示意图；
具体实施方式
下面结合附图详细描述本发明的技术方案
如图1所示，本发明的一种体内栅型MOS，包括从下至上依次层叠设置的漏极电极11、N型重掺杂单晶硅衬底12、低掺杂P型外延层5、高掺杂P+源区2和源极金属电极1；所述掺杂P型外延层5中具有条形源区6和条形漏区9，所述条形源区6和条形漏区9位于同一水平面，且条形源区6和条形漏区9之间通过多晶硅栅7连接，所述多晶硅栅7通过栅氧化层8与低掺杂P型外延层5隔离；所述条形源区6通过贯穿高掺杂P+源区2的第一深槽金属3与源极金属电极1连接，所述第一深槽金属3通过第一氧化层4与低掺杂P型外延层5和高掺杂P+源区2隔离；所述条形漏区9通过贯穿N型重掺杂单晶硅衬底12的第二深槽金属10与漏极电极11连接，所述第二深槽金属10通过第二氧化层13与低掺杂P型外延层5和N型重掺杂单晶硅衬底12隔离；所述多晶硅栅7通过第三深槽金属14连接外加栅电位，所述第三深槽金属14通过第三氧化层15与低掺杂P型外延层5和高掺杂P+源区2隔离。
本发明的工作原理为：
(1)器件的正向导通：
本发明所提供的一种新型体内栅型MOS，其正向导通时的电极连接方式为：源极电极1接低电位，漏极电极11接高电位，栅极14外加栅电压。
体内源极区域6通过深槽金属3接源极电位，体内漏极区域9通过深槽金属10接漏极电位。当源极区域6相对于漏极区域9加零电压，栅极6也未加电压时，体内漏极区域9和体内源极区域6之间没有导电通道，器件未开启。
当漏极11相对于源极1加正电压，栅极6外加正电压时，低掺杂P型外延层5与栅氧化层7相接触的表面区域形成耗尽层。当提高加在栅极7上的正电压时，低掺杂P型外延层5与栅氧化层7相接触的表面区域形成反型层16，为载流子电子提供一条流动通道，如图4所示，有电流在漏极深槽金属10、体内漏极区域9、反型层沟道16、体内源极区域6、源极深槽金属3通道流过，器件开启。由于导通电流流过的为金属和低阻的源漏区，主要的导通电阻为沟道电阻，与传统的MOS相比导通电阻大大减低。
(2)器件的反向阻断：
本发明所提供的一种新型体内栅型MOS，其正向导通时的电极连接方式为：漏极电极11接高电位，源极电极1与栅极电极14短接，且接零电位。
当栅极7外加零偏压时，电子的导电通路已经不存在。继续增加反向电压时，低掺杂P型外延层5将承受大部分耐压，类似于普通的PIN结，电场曲线的斜率在类本征层中较低，耗尽层将向靠近漏极电极11一侧扩展以承受反向电压。另一种延伸结构是在低掺杂外延层的底部有一部分高掺杂外延17，具体结构和浓度示意图如图5所示，该结构类似与穿通型IGBT的底部，与不加高掺杂外延17相比，耐压有所提高。
本发明结构可以用以下方法制备得到，工艺步骤为：
1、单晶硅准备。采用N型重掺杂单晶硅衬底12，晶向为<100>。
2、外延生长。采用气相外延VPE等方法生长一定厚度和低掺杂浓度的P型外延层5。扩展结构中利用多次不同浓度外延技术，制作出P+层17。
3、源漏区域注入。如图6所示，在整个硅片表面淀积一层1um厚的光刻胶，用掩模版光刻出源漏区域的图形然后高能离子注入，形成条形源漏区域。
4、深槽刻蚀。如图7所示，刻蚀出一个深槽结构，用于栅结构生长，其深度应高于源漏区域的底部。连接栅结构的深槽也在这步刻蚀出。
5、制备栅结构。如图8所示，热生长栅氧化层8，淀积多晶硅栅电极后再热生长一层栅氧化层。
6、外延填充深槽。如图9所示，在制备好栅结构后外延填充深槽，其掺杂浓度与第2步外延生长类似。
7、再次深槽刻蚀。如图10所示，分别在硅片的上部和底部刻蚀出深槽，用来对源漏区域加上电位。
8、深槽填充。如图11所示，在生长完侧壁的氧化层后，在沟槽内填充金属。连接栅结构的深槽填充也在这步进行。
9、表面P+层注入。如图12所示。
10、正面金属化源极。在整个器件表面溅射一层金属铝，形成金属区1。
11、背面减薄、金属化，形成漏极电极11，如图13所示。
Claims (6)
1.一种体内栅型MOS，包括从下至上依次层叠设置的漏极电极(11)、N型重掺杂单晶硅衬底(12)、低掺杂P型外延层(5)、高掺杂P+源区(2)和源极金属电极(1)；所述掺杂P型外延层(5)中具有条形源区(6)和条形漏区(9)，所述条形源区(6)和条形漏区(9)位于同一水平面，且条形源区(6)和条形漏区(9)之间通过多晶硅栅(7)连接，所述多晶硅栅(7)通过栅氧化层(8)与低掺杂P型外延层(5)隔离；所述条形源区(6)通过贯穿高掺杂P+源区(2)的第一深槽金属(3)与源极金属电极(1)连接，所述第一深槽金属(3)通过第一氧化层(4)与低掺杂P型外延层(5)和高掺杂P+源区(2)隔离；所述条形漏区(9)通过贯穿N型重掺杂单晶硅衬底(12)的第二深槽金属(10)与漏极电极(11)连接，所述第二深槽金属(10)通过第二氧化层(13)与低掺杂P型外延层(5)和N型重掺杂单晶硅衬底(12)隔离；所述多晶硅栅(7)通过第三深槽金属(14)连接外加栅电位，所述第三深槽金属(14)通过第三氧化层(15)与低掺杂P型外延层(5)和高掺杂P+源区(2)隔离。
2.根据权利要求1所述的一种体内栅型MOS，其特征在于，所述多晶硅栅(7)的结深小于条形源区(6)和条形漏区(9)的结深。
3.根据权利要求2所述的一种体内栅型MOS，其特征在于，所述低掺杂P型外延层(5)与N型重掺杂单晶硅衬底(12)之间具有高掺杂P区。
4.根据权利要求3所述的一种体内栅型MOS，其特征在于，所述低掺杂P型外延层(5)的掺杂浓度低于N+衬底(12)的掺杂浓度至少两个数量级。
5.根据权利要求4所述的一种体内栅型MOS，其特征在于，所述第一深槽金属(3)和第二深槽金属(10)呈条形分布结构或分散结构。
6.根据权利要求5所述的一种体内栅型MOS，其特征在于，所述第三深槽金属(14)仅位于结构的边缘处。
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| CN115207092A (zh) * | 2022-09-09 | 2022-10-18 | 深圳芯能半导体技术有限公司 | 一种高可靠性的沟槽侧壁栅碳化硅mosfet及其制备方法 |
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| US20070045723A1 (en) * | 2005-08-30 | 2007-03-01 | Seung Pyo Park | Semiconductor device having an under stepped gate for preventing gate failure and method of manufacturing the same |
| KR20100048120A (ko) * | 2008-10-30 | 2010-05-11 | 주식회사 하이닉스반도체 | 고집적 반도체 기억 장치 |
| CN104167445A (zh) * | 2014-08-29 | 2014-11-26 | 电子科技大学 | 具有埋栅结构的氮化镓基增强耗尽型异质结场效应晶体管 |
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| JPH098291A (ja) * | 1995-06-20 | 1997-01-10 | Fujitsu Ltd | 半導体装置 |
| US5757047A (en) * | 1995-12-14 | 1998-05-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US20070045723A1 (en) * | 2005-08-30 | 2007-03-01 | Seung Pyo Park | Semiconductor device having an under stepped gate for preventing gate failure and method of manufacturing the same |
| KR20100048120A (ko) * | 2008-10-30 | 2010-05-11 | 주식회사 하이닉스반도체 | 고집적 반도체 기억 장치 |
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| CN115207092A (zh) * | 2022-09-09 | 2022-10-18 | 深圳芯能半导体技术有限公司 | 一种高可靠性的沟槽侧壁栅碳化硅mosfet及其制备方法 |
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