CN105957900A - Metal oxide diode with high voltage withstanding and low conduction voltage drop characteristics - Google Patents
Metal oxide diode with high voltage withstanding and low conduction voltage drop characteristics Download PDFInfo
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- CN105957900A CN105957900A CN201610392836.XA CN201610392836A CN105957900A CN 105957900 A CN105957900 A CN 105957900A CN 201610392836 A CN201610392836 A CN 201610392836A CN 105957900 A CN105957900 A CN 105957900A
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000000407 epitaxy Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 17
- 238000009825 accumulation Methods 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to the semiconductor technology and particularly relates to a metal oxide semiconductor diode with high voltage withstanding and low conduction voltage drop characteristics. The metal oxide semiconductor diode comprises an electron accumulation layer structure and a junction field effect transistor structure and can obtain low conduction voltage drop. At the same time, an N type area 3 with a high doping concentration is employed, and the conduction voltage drop of the diode in positive conduction is reduced further. When a device is reversely blocked, the acceptor impurities contained in a P type area 8 and a P type buried layer 8 and the donor impurity contained in the N type area are mutually depleted, thus the electric field distribution of a drift area is in a rectangular distribution, and the reverse blocking voltage of the device can be raised. Therefore, the new structure of the invention has the advantages of high voltage withstanding and low conduction voltage drop.
Description
Technical field
The present invention relates to semiconductor technology, particularly to a kind of, there is the high resistance to MOS diode forcing down conduction voltage drop characteristic.
Background technology
Diode is one of the most frequently used electronic component, and traditional commutation diode is mainly Schottky rectifier and PN junction commutator.
Wherein, PN junction diode can bear higher reverse BV, and stability is preferable, but its forward conduction voltage drop is relatively big,
Reverse recovery time is longer.Schottky diode is that the metal-semiconductor junction principle utilizing metal and semiconductor contact to be formed makes,
On-state voltage drop is relatively low.Owing to being one pole carrier conduction, Schottky diode does not has the minority carrier of surplus when forward conduction
Accumulation, Reverse recovery is very fast.But the breakdown reverse voltage of Schottky diode is relatively low, reverse leakage current is relatively big, temperature characterisitic
Poor.
In order to improve the performance of diode, domestic and international researchers always strive to combine the excellent of PN junction diode and Schottky diode
Point, it is proposed that PiN diode, Junction Barrier Controlled commutator JBS (JBS:Junction Barrier Schottky Rectifier),
MOS control diode MCD (MCD:MOS Controlled Diode), trench MOS barrier Schottky diode TMBS (TMBS:
Trench MOS Barrier Shcotty Diode) etc. device.Patent " shallow slot MOS diode (CN 102064201A) "
Propose a kind of novel semiconductor diode device, combine electron accumulation layer and junction field tubular construction, it is thus achieved that very
Low conduction voltage drop, substantially increases breakdown voltage and reduces leakage current.But, shallow slot MOS diode and
Schottky diode is equally many subtypes device, and the raising that it is the most pressure exists contradiction with the reduction of forward conduction voltage drop, improves
Device the most pressure, it is necessary to increase the thickness of drift region, reduces the doping content of drift region, and these factors all just can increase
To conduction voltage drop, which has limited the application in mesohigh application of this device.
Summary of the invention
The purpose of the present invention, it is simply that higher in order to solve the forward conduction voltage drop of shallow slot MOS diode in mesohigh field
Problem, make device ensure higher the most pressure while, it is achieved low forward conduction voltage drop.
Technical scheme: a kind of have the high resistance to MOS diode forcing down conduction voltage drop characteristic, including from up to
Under the anode electrode 9, N-doped region 4, N-type region 3, N-type heavy doping monocrystalline substrate 2 and the cathode electrode 1 that are cascading；
The two ends of described anode electrode 9 extend in N-doped region 4 vertically downward, and N-doped region 4 downwardly extends with anode electrode 9
There is between part N-type heavily doped region 5；N-doped region 4 upper surface between the N-type heavily doped region 5 of both sides has planar gate
Structure, described planar gate structure is positioned in anode electrode 1, and described planar gate structure includes gate oxide 10 and is positioned at oxide layer
The polygate electrodes 11 of 10 upper surfaces, oxide layer 10 lower surface and part N-type heavily doped region 5 upper surface；Described sun
The underface of pole electrode 9 downward extension portion has N-type heavily doped region 6；The lower section of described N-type heavily doped region 6 has p-type
District 8 is connected with N-doped region 4 with p type buried layer 7 and p type buried layer 7, and described p type island region 8 extends to and N-type weight vertically downward
The upper surface of doped single crystal silicon substrate 2 connects, and p type buried layer 7 lower surface is connected with the upper surface of N-type region 3；
The doping content of described p type buried layer 7 is more than two orders of magnitude of doping content of N-doped region 4；Mixing of described N-type region 3
Miscellaneous concentration is more than one to two orders of magnitude of doping content of N-doped region 4；Being subject to contained by described p type island region 8 and p type buried layer 7
Main total impurities is equal to the donor impurity total amount contained by N-type region 3.
Further, described silicon dioxide gate oxide 10 is thin gate oxide, and its thickness is 5nm-100nm.
Further, N-doped region 4 extends to the lower section of p type island region 7.
Further, also there is between N-type heavy doping monocrystalline substrate 2 and N-type region 3 N-type epitaxy layer 12, N-type extension
The concentration of layer 12 is different from the doping content of N-type drift region 3.
Further, also there is between N-type heavy doping monocrystalline substrate 2 and p type island region 8 second p type island region 13
The invention have the benefit that a kind of there is the high resistance to MOS diode forcing down conduction voltage drop characteristic, there is electronics
Accumulation layer structure and junction field tubular construction, owing to the gate oxide of electron accumulation layer is the thinnest and the doping of N-doped region 4 is dense
Spending relatively low, diode can obtain relatively low conduction voltage drop；Use the N-type region 3 that doping content is higher simultaneously, make diode exist
Conduction voltage drop during forward conduction reduces further.During device reverse blocking, p type island region 8 is miscellaneous with the acceptor contained by p type buried layer 7
Matter mutually exhausts with the donor impurity contained by N-type region 3, makes the rectangular distribution of Electric Field Distribution of drift region, can improve the anti-of device
To blocking voltage.Therefore, the new construction that the present invention proposes has high pressure and low conduction voltage drop simultaneously.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the metal-oxide-semiconductor diode new construction that embodiment 1 is provided；
Fig. 2 is that the metal-oxide-semiconductor diode new construction that embodiment 1 is provided exhausts line schematic diagram when additional no-voltage；
Fig. 3 be the metal-oxide-semiconductor diode new construction that provided of embodiment 1 when applied voltage arrives cut-in voltage,
Exhaust line and current path schematic diagram；
Fig. 4 is that the metal-oxide-semiconductor diode new construction that embodiment 1 is provided exhausts line signal when additional backward voltage
Figure and drift region longitudinal electric field distribution schematic diagram.
Fig. 5 is to exhaust line schematic diagram during patent " shallow slot MOS diode (CN 102064201A) " additional backward voltage
With drift region longitudinal electric field distribution schematic diagram.
Fig. 6 is the cross-sectional view of the metal-oxide-semiconductor diode new construction that embodiment 2 is provided；
Fig. 7 is the cross-sectional view of the metal-oxide-semiconductor diode new construction that embodiment 3 is provided；
Fig. 8 is the cross-sectional view of the metal-oxide-semiconductor diode new construction that embodiment 4 is provided.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is described in detail.
The diode of the present invention has negative electrode and two, anode to control electrode.
Embodiment 1
As it is shown in figure 1, this example has the high resistance to MOS diode forcing down conduction voltage drop characteristic, including depending on from top to bottom
Anode electrode 9, N-doped region 4, N-type region 3, N-type heavy doping monocrystalline substrate 2 and the cathode electrode 1 that secondary stacking is arranged；Institute
The two ends stating anode electrode 9 extend in N-doped region 4 vertically downward, the portion that N-doped region 4 downwardly extends with anode electrode 9
/ there is N-type heavily doped region 5；N-doped region 4 upper surface between the N-type heavily doped region 5 of both sides has planar gate knot
Structure, described planar gate structure is positioned in anode electrode 1, and described planar gate structure includes gate oxide 10 and is positioned at oxide layer 10
The polygate electrodes 11 of upper surface, oxide layer 10 lower surface and part N-type heavily doped region 5 upper surface；Described anode
The underface of electrode 9 downward extension portion has N-type heavily doped region 6；The lower section of described N-type heavily doped region 6 has p type island region 8
Being connected with N-doped region 4 with p type buried layer 7 and p type buried layer 7, described p type island region 8 extends to and N-type heavy doping vertically downward
The upper surface of monocrystalline substrate 2 connects, and p type buried layer 7 lower surface is connected with the upper surface of N-type region 3.
The operation principle of this example is:
(1) forward conduction of device:
Height provided by the present invention is resistance to forces down conduction voltage drop metal-oxide-semiconductor diode, and electrode during its forward conduction connects
Mode is: anode electrode 9 high potential, and cathode electrode 1 connects electronegative potential.
When anode 9 adds no-voltage relative to negative electrode 1, due to doping content the mixing far above N-doped region 4 of p type buried layer 7
Miscellaneous concentration, the PN junction Built-in potential formed between p type buried layer 7 and N-doped region 4 makes the electricity between two p type buried layers 7
Sub-channel closes owing to the depletion region on both sides is connected, and meanwhile, is positioned at N-doped region 4 surface under gate oxide 10, also
Can be depleted due to grid and the work function difference of quasiconductor and the effect of oxide layer positive charge, in Fig. 2, dotted line is depletion region border.
Electric current is not the most now had to flow through in diode.
When anode 9 adds the least positive voltage relative to negative electrode 1, the depletion region between p type buried layer 7 and N-doped region 4 by
Tapered little, the depletion region below thin gate oxide 10 also reduces simultaneously.When anode 9 continues to strengthen relative to the positive voltage of negative electrode 1
Time to a certain extent, the PN junction depletion region between p type buried layer 7 and N-doped region 4 is separated, and electronics path produces.Meanwhile,
Semiconductor surface under gate oxide forms carrier accumulation layer, and device is opened, and electronics is by leading between p type buried layer 7
Circulation passage, is injected into N-type region 3, as it is shown on figure 3, anode positive voltage now is i.e. to should the cut-in voltage of diode.By
In the body bias effect of MOS structure, this structure has the cut-in voltage lower than conventional diode.When added positive voltage continues to strengthen,
In electron accumulation layer below thin gate oxide 10, electron concentration is higher, and this provides a more smooth path for electronics flowing.
Compared with patent " shallow slot MOS diode (CN 102064201A) ", the doping content of N-type region 3 is mixed than N-
Big one to two orders of magnitude of doping content in miscellaneous district 4, thus device has lower forward conduction voltage drop when forward conduction.
(2) reverse blocking of device:
Height provided by the present invention is resistance to forces down conduction voltage drop metal-oxide-semiconductor diode, and electrode during its reverse blocking connects
Mode is: cathode electrode 1 connects high potential, and anode electrode 9 connects electronegative potential.
During due to zero-bias, the conductive path of electronics is by PN junction depletion region pinch off, when continuing to increase backward voltage, and p type buried layer
7 form reverse biased pn junction, p type island region 8 and N-type region 3 with p type island region 8 with N-type region 3 will be exhausted further, and depletion layer will
From the interface of P-N post to below N-type region 3, extend to bear backward voltage inside p type island region 8, as shown in Figure 4, final N
Type district 3, p type island region 8 are completely depleted.Owing to backward voltage is undertaken by PN junction depletion region, the therefore reverse leakage current of device
Reverse leakage much smaller than Schottky diode.As shown in Figure 4, after N-type region 3, p type island region 8 exhaust, this region is equivalent to only
Carrier concentration is the intrinsic region of zero, and according to Poisson's equation, the longitudinal electric field in this region should be approximate rectangular, and patent " shallow slot gold
Belong to oxide diode (CN 102064201A) " the longitudinal electric field of N-type region 3 be Triangle-Profile (as shown in Figure 5).By
Being the integration of its longitudinal electric field in device pressure voltage, therefore the reverse blocking of embodiment 1 is pressure will be greatly improved.Enter one
Step ground, in the case of identical reverse blocking is pressure, N-type region 3 doping content of embodiment 1 compares patent " shallow slot metal
Oxide diode (CN 102064201A) " can improve, thus the drift zone resistance of embodiment 1 reduces, and reduces forward
Conduction voltage drop, decreases energy loss during forward conduction.
Embodiment 2
As shown in Figure 6, the structure of this example is on the basis of embodiment 1, by thinning for the thickness of N-type region 3, and N-doped region 4
Thickness increase, extend to the lower section of p type island region 7, the operation principle of this example is similar to Example 1, can reduce out further
Open voltage.
Embodiment 3
As it is shown in fig. 7, the structure of this example is on the basis of embodiment 1, N-type heavy doping monocrystalline substrate grows one layer of N
Type epitaxial layer 12, the concentration of N-type epitaxy layer 12 is different from the concentration of N-type drift region 3, and N-type region 3, p type island region 8 are together simultaneously
Time thickness the most thinning.In order to meet different demands, the concentration of N-type epitaxy layer 12 can be adjusted.In order to further
Reduce conduction voltage drop, the doping content of N-type epitaxy layer 12 can be improved；The most pressure in order to improve, N-type extension can be reduced
The doping content of layer 12.
Embodiment 4
As shown in Figure 8, the structure of this example, on the basis of embodiment 1, grown one layer in N-type heavy doping monocrystalline substrate
N-type epitaxy layer 12, has p type island region 13 in the both sides of N-type epitaxy layer 12, decreases N-type region 3, the thickness of p type island region 8 simultaneously.
N-type region 3 is positioned at the top of N-type epitaxy layer 12, and p type island region 8 is positioned at the top of p type island region 13.In described N-type epitaxy layer 12
Total impurities identical with the total impurities of p type island region 13, the total impurities in p type island region 8 and the total impurities phase in N-type region 3
With.The width of described N-type epitaxy layer 12 is more than the width of described N-type region 3.The operation principle of this example is similar to Example 1,
Compared to embodiment 1, wider N-type epitaxy layer 12 has further expanded current flow paths, has reduced forward conduction voltage drop.
As a example by embodiment 1, present configuration can prepare using the following method, and processing step is:
1, monocrystal silicon prepares.Using N-type heavy doping monocrystalline substrate 2, crystal orientation is<100>.
2, epitaxial growth.Use method growth certain thickness and the N-type epitaxy layer of doping content such as vapour phase epitaxy VPE.
3, p type island region 8 etches.The methods such as ion etching are used to etch the groove of certain depth and width in N-type epitaxy layer.
4, p type island region 8 backfills.With gas phase doping or use SiH2Cl2(DCS) carry out anisotropy extension give birth to HCl gas source
The modes such as length form p type island region 8, form N post district 3 between p type island region simultaneously.
5, chemically mechanical polishing.
6, epitaxial growth.The methods such as vapour phase epitaxy are used to grow the N-type epitaxy layer 4 of certain thickness and doping content.
7, p type buried layer 7 injects.Making the figure then high-energy boron ion implanting of P buried regions 7 by lithography, implant angle can be as requested
Change, by adjusting Implantation Energy and DM doping content and junction depth.
8, grid structure is prepared.Thermally grown gate oxide 10, depositing polysilicon gate electrode.
9, photoetching, etching form gate electrode 11.
10, autoregistration arsenic injects preparation N-type heavily doped region 5.
11, shallow slot etching, p-type heavily-doped implant, form p-type heavily doped region 6.
12, front-side metallization anode.Sputter layer of metal aluminum at whole device surface, form metallization anode 9.
13, thinning back side, metallization, forms negative electrode 1.
Claims (5)
1. there is the high resistance to MOS diode forcing down conduction voltage drop characteristic, including be cascading from top to bottom
Anode electrode (9), N-doped region (4), N-type region (3), N-type heavy doping monocrystalline substrate (2) and cathode electrode (1)；
The two ends of described anode electrode (9) extend in N-doped region (4) vertically downward, N-doped region (4) and anode electrode (9)
There is between the part downwardly extended N-type heavily doped region (5)；N-doped region (4) between the N-type heavily doped region (5) of both sides
Upper surface has planar gate structure, and described planar gate structure is positioned in anode electrode (1), and described planar gate structure includes gate oxidation
Layer (10) and be positioned at the polygate electrodes (11) of oxide layer (10) upper surface, oxide layer (10) lower surface and part N-type
Heavily doped region (5) upper surface；The underface of described anode electrode (9) downward extension portion has N-type heavily doped region (6)；
The lower section of described N-type heavily doped region (6) has p type island region (8) and p type buried layer (7) and p type buried layer (7) and adulterates with N-
District (4) is connected, and described p type island region (8) extend to be connected with the upper surface of N-type heavy doping monocrystalline substrate (2) vertically downward,
P type buried layer (7) lower surface is connected with the upper surface of N-type region (3)；
The doping content of described p type buried layer (7) is more than two orders of magnitude of doping content of N-doped region (4)；Described N-type region
(3) doping content is more than one to two orders of magnitude of doping content of N-doped region (4)；Described p type island region (8) and P
Acceptor impurity total amount contained by type buried regions (7) is equal to the donor impurity total amount contained by N-type region (3).
The most according to claim 1 a kind of have the high resistance to MOS diode forcing down conduction voltage drop characteristic, its feature
Being, described oxide layer (10) is thin gate oxide, and its thickness is 5nm-100nm.
The most according to claim 2 a kind of have the high resistance to MOS diode forcing down conduction voltage drop characteristic, its feature
Being, N-doped region (4) extends to the lower section of p type island region (7).
The most according to claim 3 a kind of have the high resistance to MOS diode forcing down conduction voltage drop characteristic, its feature
It is also there is between N-type heavy doping monocrystalline substrate (2) and N-type region (3) N-type epitaxy layer (12), outside N-type
The concentration prolonging layer (12) is different from the doping content of N-type drift region (3).
The most according to claim 4 a kind of have the high resistance to MOS diode forcing down conduction voltage drop characteristic, its feature
It is that also there is between N-type heavy doping monocrystalline substrate (2) and p type island region (8) the second p type island region (13).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610392836.XA CN105957900A (en) | 2016-06-03 | 2016-06-03 | Metal oxide diode with high voltage withstanding and low conduction voltage drop characteristics |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610392836.XA CN105957900A (en) | 2016-06-03 | 2016-06-03 | Metal oxide diode with high voltage withstanding and low conduction voltage drop characteristics |
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| CN105957900A true CN105957900A (en) | 2016-09-21 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130913A (en) * | 2006-11-22 | 2008-06-05 | Rohm Co Ltd | Semiconductor device and manufacturing method |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| US20160005884A1 (en) * | 2012-12-26 | 2016-01-07 | Rohm Co., Ltd. | Semiconductor device |
| CN105590965A (en) * | 2016-03-14 | 2016-05-18 | 电子科技大学 | Plane type metal oxide semiconductor diode with adjustable threshold voltage |
-
2016
- 2016-06-03 CN CN201610392836.XA patent/CN105957900A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130913A (en) * | 2006-11-22 | 2008-06-05 | Rohm Co Ltd | Semiconductor device and manufacturing method |
| US20160005884A1 (en) * | 2012-12-26 | 2016-01-07 | Rohm Co., Ltd. | Semiconductor device |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| CN105590965A (en) * | 2016-03-14 | 2016-05-18 | 电子科技大学 | Plane type metal oxide semiconductor diode with adjustable threshold voltage |
Non-Patent Citations (1)
| Title |
|---|
| YING WANG等: "A superjunction schottky barrier diode with trench metal-oxide-semiconductor structure", 《IEEE ELECTRON DEVICE LETTERS》 * |
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