CN105932986B - D type flip flop - Google Patents
D type flip flop Download PDFInfo
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- CN105932986B CN105932986B CN201610366914.9A CN201610366914A CN105932986B CN 105932986 B CN105932986 B CN 105932986B CN 201610366914 A CN201610366914 A CN 201610366914A CN 105932986 B CN105932986 B CN 105932986B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
Abstract
The present invention provides a kind of d type flip flops, are related to trigger field.The d type flip flop includes at least identical metal-oxide-semiconductor of a pair of conductive type, each metal-oxide-semiconductor includes first substrate or first trap opposite with metal-oxide-semiconductor conduction type, first trap of one of metal-oxide-semiconductor that the first substrate of one of metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type is provided with the second trap identical with metal-oxide-semiconductor conduction type or the identical metal-oxide-semiconductor of each pair of conduction type is provided with the second substrate identical with metal-oxide-semiconductor conduction type, and the second substrate or the second trap are located between two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor.When the sensitive nodes of the d type flip flop are hit, it can inhibit the charge generated when sensitive nodes are bombarded and spread in neighbouring sensitive nodes, overturning while being effectively prevented from multiple sensitive nodes improves the reliability and safety of d type flip flop.
Description
Technical field
The present invention relates to trigger fields, in particular to a kind of d type flip flop.
Background technique
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particles.Integrated circuit by
After the bombardment of these high energy particles and charged particle, electronic impulse can be generated in integrated circuit, may make IC interior section
The original level of point is flipped, this effect is known as single-particle inversion.The linear energy transfer of single-particle bombardment integrated circuit
(Linear Energy Transfer, LET) value is higher, and the electronic impulse of generation is stronger.Collect used in Aeronautics and Astronautics field
All integrated circuit operation can be kept unstable by the threat of single-particle inversion at circuit, or even generate fatal mistake, therefore open
Sending out integrated circuit anti-single particle advanced, overturning reinforcement technique is particularly important.D type flip flop is in sequential logical circuit using most
One of unit, anti-single particle overturning ability directly determines the anti-single particle overturning ability of integrated circuit.To d type flip flop into
Row circuit-level reinforces the anti-single particle overturning that integrated circuit can be effectively improved under lesser chip area, power consumption and cost
Ability.
D type flip flop in the prior art uses DICE structure, using the sensitive nodes being mutually redundant to coming to d type flip flop etc.
Timing unit is reinforced, and when a node is flipped by particle bombardment, redundancy structure can carry out the overturning
It repairs, because of the mistake overturning of the output signal without caused by.But if distance is too small between sensitive nodes pair, single-particle bombardment it is quick
The charge generated after sense node just readily diffuses into its sensitive nodes, so that a pair of of sensitive nodes in DICE structure are sent out simultaneously
Raw overturning, to cause circuit that multiple node upset, DICE structural strengthening failure occurs.
Summary of the invention
In view of this, the embodiment of the present invention is designed to provide a kind of d type flip flop, to improve above-mentioned problem.
A kind of d type flip flop provided in an embodiment of the present invention, including at least identical metal-oxide-semiconductor of a pair of conductive type, Mei Duisuo
Two metal-oxide-semiconductor intervals setting of metal-oxide-semiconductor is stated, the drain electrode of each metal-oxide-semiconductor includes sensitive nodes, each metal-oxide-semiconductor
Include first substrate or first trap opposite with the metal-oxide-semiconductor conduction type, the identical metal-oxide-semiconductor of each pair of conduction type its
In metal-oxide-semiconductor the first substrate or the first trap connect with the first substrate of another metal-oxide-semiconductor or the first trap, each pair of conduction type
First substrate of one of them of the identical metal-oxide-semiconductor metal-oxide-semiconductor is provided with the second trap identical with the metal-oxide-semiconductor conduction type
Or the first trap of one of them metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type is provided with and the metal-oxide-semiconductor conduction type
Identical second substrate, and second substrate or the second trap are located between two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor.
Further, at least one crystal is provided between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type
Pipe.
Further, multiple transistors are provided between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type.
Further, the transistor is metal-oxide-semiconductor or bipolar junction transistor and power transistor npn npn.
Further, the substrate of one of them metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type is provided with blank area
Domain, the white space is located between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type, and the blank area
Domain is located at the left side of second substrate or the second trap.
Further, the spacing distance between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type be 1um~
5um。
Further, the spacing distance between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type is 3um.
Further, the metal-oxide-semiconductor is NMOS tube, and each NMOS tube includes and the NMOS tube conduction type
The first opposite substrate P, second trap are N trap.
Further, the metal-oxide-semiconductor is PMOS tube, and each PMOS tube includes and the PMOS tube conduction type
The first opposite N trap, second substrate are the second substrate P.
Further, the d type flip flop includes the identical metal-oxide-semiconductor of multipair conduction type, and the multipair conduction type is identical
Metal-oxide-semiconductor include multipair PMOS tube and multipair NMOS tube.
Compared with prior art, a kind of d type flip flop of offer of the invention, in the identical metal-oxide-semiconductor of each pair of conduction type
First substrate of one of them metal-oxide-semiconductor is provided with the second trap identical with the metal-oxide-semiconductor conduction type or each pair of conductive-type
First trap of one of them metal-oxide-semiconductor of the identical metal-oxide-semiconductor of type is provided with the second lining identical with the metal-oxide-semiconductor conduction type
Bottom, and the second trap or the second substrate are located between two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor, the conduction type that metal-oxide-semiconductor includes is opposite
The first substrate and opposite the first trap of second trap identical with metal-oxide-semiconductor conduction type or the metal-oxide-semiconductor conduction type that includes
A reverse-biased PN junction, i.e. back biased diode can be formed with second substrate identical with metal-oxide-semiconductor conduction type, works as a pair
When bombardment of the sensitive nodes of one of metal-oxide-semiconductor of metal-oxide-semiconductor by high energy particle, trap formation is made between two metal-oxide-semiconductors
Reverse-biased PN junction can bombardment to sensitive nodes by high energy particle when the electronics that generates or hole play prevention or absorption
Effect, to inhibit the charge generated when bombardment of the sensitive nodes by high energy particle in the diffusion of neighbouring sensitive nodes, from
And overturning while multiple sensitive nodes is efficiently avoided, improve the reliability and safety of d type flip flop.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.Therefore, below to the reality of the invention provided in the accompanying drawings
The detailed description for applying example is not intended to limit the range of claimed invention, but is merely representative of selected implementation of the invention
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
Every other embodiment, shall fall within the protection scope of the present invention.
Fig. 1 is present pre-ferred embodiments d type flip flop circuit layout.
Wherein, the corresponding relationship between appended drawing reference and component names is as follows: NMOS tube 101, PMOS tube 102, the first P lining
Bottom 103, the first N trap 104, the 2nd N trap 105, the second substrate P 106, sensitive nodes 107, white space 108, transistor 109.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particles.Integrated circuit by
After the bombardment of these high energy particles and charged particle, electronic impulse can be generated in integrated circuit, may make IC interior section
The original level of point is flipped, this effect is known as single-particle inversion.The linear energy transfer of single-particle bombardment integrated circuit
(Linear Energy Transfer, LET) value is higher, and the electronic impulse of generation is stronger.Collect used in Aeronautics and Astronautics field
All integrated circuit operation can be kept unstable by the threat of single-particle inversion at circuit, or even generate fatal mistake, therefore open
Sending out integrated circuit anti-single particle advanced, overturning reinforcement technique is particularly important.D type flip flop is in sequential logical circuit using most
One of unit, anti-single particle overturning ability directly determines the anti-single particle overturning ability of integrated circuit.To d type flip flop into
Row circuit-level reinforces the anti-single particle overturning that integrated circuit can be effectively improved under lesser chip area, power consumption and cost
Ability.
D type flip flop in the prior art uses DICE structure, using the sensitive nodes being mutually redundant to coming to d type flip flop etc.
Timing unit is reinforced, and when a node is flipped by particle bombardment, redundancy structure can carry out the overturning
It repairs, because of the mistake overturning of the output signal without caused by.But if distance is too small between sensitive nodes pair, single-particle bombardment it is quick
The charge generated after sense node just readily diffuses into its sensitive nodes, so that a pair of of sensitive nodes in DICE structure are sent out simultaneously
Raw overturning, to cause circuit that multiple node upset, DICE structural strengthening failure occurs.
In view of this, inventor is by long-term observation and the study found that providing a kind of d type flip flop.The d type flip flop includes
At least identical metal-oxide-semiconductor of a pair of conductive type, each metal-oxide-semiconductor include first substrate opposite with metal-oxide-semiconductor conduction type or
First trap, the first substrate or the first trap of one of metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type and another metal-oxide-semiconductor
The first substrate or the connection of the first trap, the first substrate of one of metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type be provided with
First trap of one of metal-oxide-semiconductor of the second trap identical with metal-oxide-semiconductor conduction type or the identical metal-oxide-semiconductor of each pair of conduction type is set
It is equipped with the second substrate identical with metal-oxide-semiconductor conduction type, and the second substrate or the second trap are located at two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor
Between.When the sensitive nodes of the d type flip flop are hit, the electricity generated when bombardment of the sensitive nodes by high energy particle can inhibit
Lotus improves d type flip flop to efficiently avoid overturning while multiple sensitive nodes in the diffusion of neighbouring sensitive nodes
Reliability and safety.
The present invention is described in further detail below through specific implementation examples and in conjunction with the accompanying drawings.
Refering to fig. 1, a kind of d type flip flop provided by the invention, including at least identical metal-oxide-semiconductor of a pair of conductive type, it is each pair of
Two metal-oxide-semiconductor intervals of metal-oxide-semiconductor are arranged, and the drain electrode of each metal-oxide-semiconductor includes sensitive nodes 107, and each metal-oxide-semiconductor includes
First substrate or first trap opposite with metal-oxide-semiconductor conduction type, one of metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type
The first substrate or the first trap connect with the first substrate of another metal-oxide-semiconductor or the first trap, the identical metal-oxide-semiconductor of each pair of conduction type
The first substrate of one of metal-oxide-semiconductor be provided with the second trap identical with metal-oxide-semiconductor conduction type or each pair of conduction type is identical
The first trap of one of metal-oxide-semiconductor of metal-oxide-semiconductor be provided with the second substrate identical with metal-oxide-semiconductor conduction type, and the second substrate
Or second trap be located between two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor, and the first substrate wrapping with the second trap around or the first trap wrapping
Around the second substrate.
In the present embodiment, the logarithm of the identical metal-oxide-semiconductor of conduction type not only can be two pairs, or a pair, three
Pair and four pairs etc., herein with no restrictions.The identical metal-oxide-semiconductor of two pairs of conduction types described in the present embodiment refers to each pair of MOS
The conduction type of two metal-oxide-semiconductors of pipe is identical, and the conduction type being not necessarily referring between each pair of metal-oxide-semiconductor is identical.
In the present embodiment, the one pair of them metal-oxide-semiconductor of the identical metal-oxide-semiconductor of two pairs of conduction types and another pair metal-oxide-semiconductor
Conduction type can be the same or different.For example, two pairs of metal-oxide-semiconductors are NMOS tube or are PMOS tube or one pair of them are
PMOS tube, another pair are NMOS tube, herein with no restrictions.The identical metal-oxide-semiconductor of two pairs of conduction types provided in this embodiment uses
A pair of of PMOS tube and a pair of of NMOS tube illustrate.And the first substrate of each NMOS tube 101 of a pair of of NMOS tube is the first P lining
Bottom 103, the second trap is the 2nd N trap 105 between two NMOS tubes 101 of a pair of of NMOS tube；Each of a pair of of PMOS tube
First trap of PMOS tube 102 is the first N trap 104, and the second substrate is second between two PMOS tube 102 of a pair of of PMOS tube
Substrate P 106.And the first N trap 104 be paperwrapped in around the second substrate P 106, the first substrate P 103 is paperwrapped in the 2nd N trap 105
Around.
In the present embodiment, between two NMOS tubes 101 of a pair of of NMOS tube and two PMOS tube 102 of a pair of of PMOS tube
It is provided at least one transistor 109, and the arrangement of the arrangement mode of each transistor 109 and NMOS tube 101 or PMOS tube 102
Mode is consistent, and at least one described transistor 109 is not involved in the circuit connection between other electronic components of the d type flip flop.
Metal-oxide-semiconductor or bipolar junction transistor 109 and power transistor npn npn 109 can be used in transistor 109.Transistor 109 can be saved in sensitivity
It puts the electronics generated when 107 bombardment by high energy particle or the work of prevention or absorption is played in hole to a certain extent
With.Of course, it is preferably provided between two NMOS tubes 101 of a pair of of NMOS tube and two PMOS tube 102 of a pair of of PMOS tube more
A transistor 109, the electronics or sky that multiple transistors 109 can be generated in bombardment of the sensitive nodes 107 by high energy particle
Cave play the role of simultaneously prevention perhaps absorption so that enhancing to the electronics of generation or hole while playing prevention or absorption
Efficiency.In order to enable the integrated circuit technology characteristic size for being provided with d type flip flop is smaller, while to the electronics or sky of generation
Cave plays prevention simultaneously or the efficiency of absorption is higher, in the present embodiment, two NMOS tubes 101 and a pair of a pair of of NMOS tube
The quantity of transistor 109 between two PMOS tube 102 of PMOS tube is both preferably 3.
Also interval is free between two NMOS tubes 101 of a pair of of NMOS tube and two PMOS tube 102 of a pair of of PMOS tube
White region 108, and transistor 109 is located at the left side of white space 108, white space 108 is located at the 2nd N trap 105 and
The left side of two substrate Ps 106.Electronics that white space 108 can be generated in bombardment of the sensitive nodes 107 by high energy particle or
Play the role of prevention or absorption to a certain extent in hole.
If generated in view of distance is too small between two metal-oxide-semiconductors when bombardment of the sensitive nodes 107 by high energy particle
Electronics or when hole, still may generate multiparticle overturning effect, will lead to if distance is too small between two metal-oxide-semiconductors
The integrated circuit technology characteristic size that d type flip flop must be provided with is larger.By two NMOS tubes 101 and a pair of a pair of of NMOS tube
Spacing distance between two PMOS tube 102 of PMOS tube is disposed as 1um~5um, in the present embodiment, to NMOS tube 101
Spacing distance between two NMOS tubes 101 and two PMOS tube 102 of a pair of of PMOS tube is preferably arranged to 3um.
A kind of d type flip flop of offer of the invention is provided with the 2nd N trap 105 in the first substrate P 103 of a pair of of NMOS tube,
And the 2nd N trap 105 be located between two NMOS tubes 101, the first N trap 104 of a pair of of PMOS tube is provided with the second substrate P 106,
And second substrate P 106 be located between two PMOS tube 102, the first substrate P 103 of NMOS tube 101 be located at two NMOS tubes
The 2nd N trap 105 between 101 can form a reverse-biased PN junction, i.e. back biased diode；First N trap 104 of PMOS tube 102 with
The second substrate P 106 between two PMOS tube 102 can form a reverse-biased PN junction, i.e. the isolation of realization trap.Work as a pair
The sensitive nodes 107 of one of PMOS tube 102 of one of NMOS tube 101 of NMOS tube or a pair of of PMOS tube are by high energy
When the bombardment of particle, the reverse-biased PN junction that trap formation is made between two NMOS tubes 101 or PMOS tube 102 can be to sensitive nodes
The electronics or hole generated when 107 bombardment by high energy particle plays the role of prevention or absorption, to inhibit sensitive
The charge generated when bombardment of the node 107 by high energy particle neighbouring sensitive nodes 107 diffusion, to efficiently avoid
It is overturn while multiple sensitive nodes 107, improves the reliability and safety of d type flip flop.
It is respectively 2.88MeVcm using the LET value that a tandem accelerator generates through testing2/mg、8.62MeV·cm2/
mg、12.6MeV·cm2/ mg and 21.3MeVcm2Four kinds of ground heavy ion irradiations of/mg test environment.It will be in normal work
The unguyed trigger of tradition, the traditional duplication redundancy of state reinforce trigger, tradition DICE structural strengthening trigger, anti-single particle
T-flip flop and trigger provided by the invention are connected to the output end of identical 1000 grades of reverser chains, and with
The clock frequency of 40MHz works, and the input terminal of 1000 grades of reverser chains connects low level.The upper tandem accelerator is generated
LET value is respectively 2.88MeVcm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeVcm2/ mg's
Ground heavy ion irradiation is tested in environment, counts each LET value each trigger during heavy ion irradiation and mistake output occurs
Number.The total fluence of the heavy ion irradiation of every kind of LET value is 107ion/cm2.Table 1 is please referred to, as it can be seen from table 1 the present invention mentions
The trigger of confession, traditional duplication redundancy reinforce trigger, tradition DICE structural strengthening trigger and anti-single particle overturning triggering
Device, it is d type flip flop provided by the invention that it is least that errors number, which occurs, therefore it can be concluded that d type flip flop provided by the invention
Ability of the ability of anti-multiple node upset effect better than the anti-multiple node upset effect of other ground d type flip flops in the prior art.
Table 1
In the description of the present invention, it is also necessary to which explanation is unless specifically defined or limited otherwise, term " setting ",
" installation ", " connected ", " connection " shall be understood in a broad sense, for example, it may be fixedly connected, may be a detachable connection or one
Connect to body；It can be mechanical connection, be also possible to be electrically connected；It can be directly connected, it can also be indirect by intermediary
It is connected, can be the connection inside two elements.For the ordinary skill in the art, on being understood with concrete condition
State the concrete meaning of term in the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. a kind of d type flip flop, which is characterized in that including at least identical metal-oxide-semiconductor of a pair of conductive type, each pair of metal-oxide-semiconductor
The setting of two metal-oxide-semiconductor intervals, the spacing distance between two metal-oxide-semiconductors of the identical metal-oxide-semiconductor of each pair of conduction type be 1um~
The drain electrode of 5um, each metal-oxide-semiconductor include sensitive nodes, and each metal-oxide-semiconductor includes conductive with the metal-oxide-semiconductor
Type opposite the first substrate or the first trap, the first substrate of one of metal-oxide-semiconductor of the identical metal-oxide-semiconductor of each pair of conduction type or
First trap is connect with the first substrate of another metal-oxide-semiconductor or the first trap, one of institute of the identical metal-oxide-semiconductor of each pair of conduction type
The first substrate for stating metal-oxide-semiconductor is provided with the second trap identical with the metal-oxide-semiconductor conduction type or the identical MOS of each pair of conduction type
First trap of one of them of the pipe metal-oxide-semiconductor is provided with the second substrate identical with the metal-oxide-semiconductor conduction type, and described
Two substrates or the second trap are located between two metal-oxide-semiconductors of each pair of metal-oxide-semiconductor.
2. d type flip flop according to claim 1, which is characterized in that two of the identical metal-oxide-semiconductor of each pair of conduction type
At least one transistor is provided between metal-oxide-semiconductor.
3. d type flip flop according to claim 2, which is characterized in that two of the identical metal-oxide-semiconductor of each pair of conduction type
Multiple transistors are provided between metal-oxide-semiconductor.
4. d type flip flop according to claim 2, which is characterized in that the transistor be metal-oxide-semiconductor or bipolar junction transistor with
And power transistor npn npn.
5. d type flip flop according to claim 1, which is characterized in that one of them of the identical metal-oxide-semiconductor of each pair of conduction type
The substrate of the metal-oxide-semiconductor is provided with white space, and the white space is located at the two of the identical metal-oxide-semiconductor of each pair of conduction type
Between a metal-oxide-semiconductor, and the white space is located at the left side of second substrate or the second trap.
6. d type flip flop according to claim 1, which is characterized in that two of the identical metal-oxide-semiconductor of each pair of conduction type
Spacing distance between metal-oxide-semiconductor is 3um.
7. d type flip flop according to claim 1, which is characterized in that the metal-oxide-semiconductor is NMOS tube, each NMOS tube
It include first substrate P opposite with the NMOS tube conduction type, second trap is N trap.
8. d type flip flop according to claim 1, which is characterized in that the metal-oxide-semiconductor is PMOS tube, each PMOS tube
It include the first N trap opposite with the PMOS tube conduction type, second substrate is the second substrate P.
9. d type flip flop according to claim 1, which is characterized in that the d type flip flop includes that multipair conduction type is identical
Metal-oxide-semiconductor, the identical metal-oxide-semiconductor of the multipair conduction type includes multipair PMOS tube and multipair NMOS tube.
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| CN201610366914.9A CN105932986B (en) | 2016-05-27 | 2016-05-27 | D type flip flop |
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| US8081010B1 (en) * | 2009-11-24 | 2011-12-20 | Ics, Llc | Self restoring logic |
| CN103811487A (en) * | 2014-01-20 | 2014-05-21 | 天津大学 | Digital integrated circuit filling unit for inhibiting single event effect charge diffusion |
| CN104811162A (en) * | 2015-05-27 | 2015-07-29 | 中国电子科技集团公司第四十七研究所 | D flip-flop with set terminal |
| CN105609504A (en) * | 2015-12-25 | 2016-05-25 | 北京时代民芯科技有限公司 | Well isolation type anti-SEU multi-node overturning storage unit layout structure |
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2016
- 2016-05-27 CN CN201610366914.9A patent/CN105932986B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8081010B1 (en) * | 2009-11-24 | 2011-12-20 | Ics, Llc | Self restoring logic |
| CN103811487A (en) * | 2014-01-20 | 2014-05-21 | 天津大学 | Digital integrated circuit filling unit for inhibiting single event effect charge diffusion |
| CN104811162A (en) * | 2015-05-27 | 2015-07-29 | 中国电子科技集团公司第四十七研究所 | D flip-flop with set terminal |
| CN105609504A (en) * | 2015-12-25 | 2016-05-25 | 北京时代民芯科技有限公司 | Well isolation type anti-SEU multi-node overturning storage unit layout structure |
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| CN105932986A (en) | 2016-09-07 |
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