CN105609504A - Well isolation type anti-SEU multi-node overturning storage unit layout structure - Google Patents

Well isolation type anti-SEU multi-node overturning storage unit layout structure Download PDF

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CN105609504A
CN105609504A CN201510993638.4A CN201510993638A CN105609504A CN 105609504 A CN105609504 A CN 105609504A CN 201510993638 A CN201510993638 A CN 201510993638A CN 105609504 A CN105609504 A CN 105609504A
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region
isolation
trap
dice
drain region
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CN105609504B (en
Inventor
赵元富
刘皓
陆时进
刘琳
岳素格
李鹏
张晓晨
李阳
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

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  • Non-Volatile Memory (AREA)

Abstract

The invention relates to a well isolation type anti-SEU multi-node overturning storage unit layout structure. The well isolation type anti-SEU multi-node overturning storage unit layout structure comprises well isolation areas (201), (202), (203), DICE unit areas (101), (103), (105), (107) and DICE units (102), (104), (106), (108). The well isolation areas are arranged between two DICE unit areas in a crossed manner. According to the well isolation type anti-SEU multi-node overturning storage unit layout structure, compared with the prior art, the distance between sensitive node pairs is further increased while all the sensitive node pairs in a DICE storage unit structure are effectively separated; and the well isolation structure is also beneficial for reducing the parasitic bipolar transistor effect and charge sharing effect between the sensitive node pairs, so that multi-node overturning caused by SEU in the DICE units is greatly inhibited, and the anti-SEU performance of anti-radiation SRAM is greatly improved.

Description

The anti-SEU multiple node upset of a kind of trap isolated form memory cell domain structure
Technical field
The present invention relates to a kind of memory cell technologies field, particularly the anti-SEU multinode of a kind of trap isolated form turns overUnloading storage unit domain structure.
Background technology
Single-particle inversion effect, refers to that high energy proton or high-energy neutron clash into radiation and space that atomic nucleus producesHeavy nucleus particle in cosmos ray, changes thereby generation High Density Charge causes the state of memory cell internal node,Thereby cause the storage Data flipping of storage class unit, this effect is the result of single particle effect, conventionallyBe called single-particle inversion effect (SEU).
For SRAM, according to single particle effect analysis, be memory cell to the most responsive place of single-particleBody, once because single-particle hits any one sensitive nodes in memory bank, can make store status occurChange. In traditional cmos SRAM memory cell, the node of storage information (electric charge mode) comprisesThe gate node of the phase inverter in unit and the output node of another phase inverter. So this type of element circuit is anti-Single-particle inversion design is most important.
The anti-SEU multiple node upset of memory cell reinforcement means mainly contains two kinds of reinforcement means: one is to intersectCellular construction, main method is that memory cell is divided into two identical half cell structure, each half-cellStructure has two complementary memory nodes, by four half cell structure from two memory cell are carried outArranged crosswise in horizontal or vertical direction is isolated the sensitive nodes of the storage identical data in former memory cellRight, the deficiency of this method is only to have isolated the sensitive nodes pair of storing identical data in memory cell, can notEffectively avoid SEU cause storage different pieces of information sensitive nodes to occur simultaneously upset situation; Another kind ofBe to carry out the sensitive nodes pair in isolated storage unit by increasing protection ring, this method has obtained certain effectReally, but also there is different defects, as large in cellar area, have in the face of particle under angle condition of incidence everyFrom problems such as the deficient validities.
Summary of the invention
The technical problem that the present invention solves is: overcome common DICE memory cell under sub-micro technique and existUnder SEU impact, can cause that in unit, multiple memory nodes overturn, and finally cause common DICE storageThere is the problem of upset in unit. Provide a kind of new trap isolated form domain Design of Reinforcement implementation, not onlyCan effectively separate all sensitive nodes pair in common DICE memory cell structure, increase sensitivityDistance between node pair; For PMOS, N trap isolation is effectively stablized N trap voltage, greatly reduced due toThere is the probability of upset in multiple memory nodes that parasitical bipolar transistor effect causes, and for NMOS,The hole that incoming particle produces is shunted in the isolation of N trap effectively, has greatly reduced because the shared effect of electric charge causesMultiple memory nodes there is the probability of upset, thereby greatly suppressed to be caused by SEU in DICE unitMultiple node upset, has increased substantially the anti-SEU performance of radioresistance SRAM.
Technical solution of the present invention is: the anti-SEU multiple node upset of a kind of trap isolated form memory cell domainStructure, comprises the first trap area of isolation, the second trap area of isolation, triple-well area of isolation, a DICEUnit area, the 2nd DICE unit area, wherein
The first trap area of isolation, the second trap area of isolation, triple-well area of isolation are all made up of N trap, NAbove trap, be provided with contact hole structure;
The one DICE unit area is decomposed into four identical piece regions, and decompose the 2nd DICE unit areaBe four identical piece regions, each region includes one-level latch structure, transfer tube, wherein, and one-levelLatch structure comprises PMOS load pipe, the NMOS driving tube of common grid, and transfer tube comprises with NMOS and drivingThe moving pipe nmos pass transistor in drain region altogether;
The first trap area of isolation, the second trap area of isolation, triple-well area of isolation intersection are in the layout of a DICEIn unit area, the 2nd DICE unit area.
Described the first trap area of isolation, the second trap area of isolation are in the layout of respectively in a DICE unit and depositBetween the load pipe PMOS drain region of storage identical data, and in the 2nd DICE unit, store identical dataBetween load pipe PMOS drain region.
Described the second trap area of isolation, triple-well area of isolation are in the layout of respectively in a DICE unit and storeBetween the load pipe PMOS drain region of identical data, and in the 2nd DICE unit, store the negative of identical dataCarry between pipe PMOS drain region.
Described the first trap area of isolation, the second trap area of isolation are in the layout of respectively in a DICE unit and storeBetween the drain region of the driving tube NMOS of identical data, and the source of the transfer tube NMOS of transmission identical dataBetween district, and in the 2nd DICE unit, store between the drain region of driving tube NMOS of identical data, andThe source region of the transfer tube NMOS of transmission identical data) between.
Described the second trap area of isolation, triple-well area of isolation are in the layout of respectively in a DICE unit and storeBetween the drain region of the driving tube NMOS of identical data, and the source of the transfer tube NMOS of transmission identical dataBetween district, and in the 2nd DICE unit, store between the drain region of driving tube NMOS of identical data, andBetween the source region of the transfer tube NMOS of transmission identical data.
Described the first trap area of isolation is in the layout of the load pipe of storing different pieces of information in a DICE unitBetween the drain region of PMOS drain region and driving tube NMOS, and store different pieces of information in the 2nd DICE unitLoad pipe PMOS drain region and the drain region of driving tube NMOS between.
Described the second trap area of isolation is in the layout of the load pipe of storing different pieces of information in a DICE unitBetween the drain region of PMOS drain region and driving tube NMOS, and store different pieces of information in the 2nd DICE unitLoad pipe PMOS drain region and the drain region of driving tube NMOS between.
Described triple-well area of isolation is in the layout of the load pipe of storing different pieces of information in a DICE unitBetween the drain region of PMOS drain region and driving tube NMOS, and store different pieces of information in the 2nd DICE unitLoad pipe PMOS drain region and the drain region of driving tube NMOS between.
PMOS load pipe drain region in described piece region, NMOS driving tube drain region storage data,Nmos pass transistor transmission data.
The present invention's advantage is compared with prior art:
(1) the present invention by trap area of isolation intersect layout in a DICE unit area, the 2nd DICEIn unit, effectively separate all sensitive nodes in DICE memory cell structure right in, enter oneStep has increased the distance between sensitive nodes pair, has solved existing anti-SEU multiple node upset property reliable for effect poorProblem;
(2) the present invention, by adding at trap area of isolation N trap, compared with existing anti-SEU technology, fallsLow parasitical bipolar transistor effect and electric charge are shared multinode that effect causes and occur the probability of upset, largeAmplitude has improved the anti-SEU performance of radioresistance SRAM;
(3) the present invention compared with prior art, by memory cell being divided into two DICE interleaved unitPart structure, increase sensitive nodes spacing, further reduced memory cell sensitive nodes to there is upsetProbability.
Brief description of the drawings
Fig. 1 is the schematic diagram of trap isolation structure position in integral planar in domain of the present invention;
Fig. 2 is the source transistor drain structure overall plan view in domain structure of the present invention;
Fig. 3 is the inner sensitive nodes distribution map in a DICE unit in domain structure of the present invention;
Fig. 4 is the inner sensitive nodes distribution map in the 2nd DICE unit in domain structure of the present invention.
Detailed description of the invention
The present invention overcomes common DICE memory cell under sub-micro technique can cause list under SEU impactIn unit, multiple memory nodes overturn, and finally cause common DICE memory cell that the deficiency of overturning occurs,Propose a kind of new anti-SEU multiple node upset of trap isolated form memory cell domain structure, can effectively divideFrom all sensitive nodes pair in common DICE memory cell structure, increase the distance between sensitive nodes pairFrom, wherein, for PMOS pipe, the isolation of N trap is effectively stablized N trap voltage, has reduced due to parasitic twoThere is the probability of upset in the multiple memory nodes that bipolar transistor effect causes, for NMOS pipe, N trap everyFrom the hole of effectively shunting incoming particle generation, reduce because electric charge is shared multiple storages that effect causesThere is the probability of upset in node, thereby has suppressed the multiple node upset being caused by SEU in DICE unit, largeAmplitude has improved the anti-SEU performance of radioresistance SRAM, below in conjunction with accompanying drawing, domain structure of the present invention is enteredRow describes in detail.
Domain structure of the present invention is the two DICE interleaved with trap isolation as shown in Figure 1 and Figure 2Element domain structure, comprises trap area of isolation, forms a DICE cellular zone by 201,202,203Territory comprises that 101,103,105,107, the two DICE unit areas comprise 102,104,106,108Composition, wherein, trap isolated location region 201,202,203 intersects and is in the layout of a DICE unit and theIn the middle of two DICE unit.
As shown in Figure 3, described trap area of isolation 201,202,203 makes in a DICE unit areaThe sensitive nodes of storage or transmission identical data is to further mutually away from layout. Concrete satisfied following rule:In the one DICE unit, store the load pipe PMOS drain region 01 and 03 of identical data, storage identical dataThe drain region 05 and 07 of driving tube NMOS, and the source region of the transfer tube NMOS of transmission identical data11 and 13, first arrange by the Integral cross of two DICE unit, by piece region 102,103 and 104Isolate, further isolate through the piece region 201 and 202 of trap isolation and then; The one DICEIn unit, store the load pipe PMOS drain region 02 and 04 of identical data, the driving tube of storage identical dataThe drain region 06 and 08 of NMOS, and the source region 12 and 14 of the transfer tube NMOS of transmission identical data,First arrange by the Integral cross of two DICE unit, isolated by piece region 104,105 and 106,Further isolate through the piece region 202 and 203 of trap isolation and then;
As shown in Figure 4, described trap area of isolation 201,202,203 makes to store in the 2nd DICE unitOr the sensitive nodes of transmission identical data is to further mutually away from layout. Concrete satisfied following rule: secondIn DICE unit, store the load pipe PMOS drain region 15 and 17 of identical data, store driving of identical dataThe drain region 19 and 21 of moving pipe NMOS, and the source region 23 of the transfer tube NMOS of transmission identical dataWith 25, first arrange by the Integral cross of two DICE unit, entered by piece region 103,104 and 105Row isolation, further isolates through the piece region 201 and 202 of trap isolation and then; The 2nd DICEIn unit, store the load pipe PMOS drain region 16 and 18 of identical data, the driving tube of storage identical dataThe drain region 20 and 22 of NMOS, and the source region 24 and 26 of the transfer tube NMOS of transmission identical data,First arrange by the Integral cross of two DICE unit, isolated by piece region 105,106 and 107,Further isolate through the piece region 202 and 203 of trap isolation and then;
As shown in Figure 3, described trap area of isolation 201,202,203 makes in a DICE unit areaThe sensitive nodes of storage different pieces of information is to will be mutually away from layout. Concrete satisfied following rule a: DICEIn unit, store the load pipe PMOS drain region 01 of different pieces of information and the drain region 06 of driving tube NMOS, headFirst arrange by the Integral cross of two DICE unit, isolated by piece region 102, pass through and then trapThe piece region 201 of isolation further isolates; Load pipe PMOS drain region 03 He of storage different pieces of informationThe drain region 08 of driving tube NMOS, first arranges by the Integral cross of two DICE unit, by piece region106 isolate, and further isolate and then through the piece region 203 of trap isolation; Store different numbersAccording to load pipe PMOS drain region 02 and the drain region 07 of driving tube NMOS, first mono-by two DICEThe Integral cross of unit is arranged, is isolated the piece region 202 isolating through trap and then by piece region 104Further isolate;
As shown in Figure 4, described trap area of isolation 201,202,203 makes in the 2nd DICE unit areaThe sensitive nodes of storage different pieces of information is to will be mutually away from layout. Concrete satisfied following rule: the 2nd DICEIn unit, store the load pipe PMOS drain region 15 of different pieces of information and the drain region 20 of driving tube NMOS, headFirst arrange by the Integral cross of two DICE unit, isolated by piece region 103, pass through and then trapThe piece region 201 of isolation further isolates; Load pipe PMOS drain region 17 Hes of storage different pieces of informationThe drain region 22 of driving tube NMOS, first arranges by the Integral cross of two DICE unit, by piece region107 isolate, and further isolate and then through the piece region 203 of trap isolation; Store different numbersAccording to load pipe PMOS drain region 16 and the drain region 21 of driving tube NMOS, first mono-by two DICEThe Integral cross of unit is arranged, is isolated the piece region 202 isolating through trap and then by piece region 105Further isolate.
As Fig. 3, shown in Fig. 4, described trap area of isolation 201,202,203 is effectively stablized N trap voltage,Greatly reduced between responsive PMOS device drain region due to parasitical bipolar transistor effect cause multipleThere is the probability of upset in memory node. Wherein region 201 and 202 is in the layout of respectively in a DICE unitBetween the load pipe PMOS drain region 01 and 03 of storage identical data, and store in the 2nd DICE unitBetween the load pipe PMOS drain region 15 and 17 of identical data; Region 202 and 203 is in the layout of respectivelyIn one DICE unit, store between the load pipe PMOS drain region 02 and 04 of identical data, and secondIn DICE unit, store between the load pipe PMOS drain region 16 and 18 of identical data.
As Fig. 3, shown in Fig. 4, described trap area of isolation 201,202,203 is shunted effectively into radionThe electronics that son produces, has greatly reduced between the drain region of responsive nmos device because electric charge is shared effect and causedMultiple memory nodes there is the probability of upset. Wherein region 201 and 202 is in the layout of respectively a DICEIn unit, store between the drain region 05 and 07 of driving tube NMOS of identical data, and transmission identical dataThe source region 11 and 13 of transfer tube NMOS between, and in the 2nd DICE unit, store identical dataBetween the drain region 19 and 21 of driving tube NMOS, and the source region of the transfer tube NMOS of transmission identical dataBetween 23 and 25. Region 202 and 203 is in the layout of respectively and in a DICE unit, stores identical dataBetween the drain region 06 and 08 of driving tube NMOS, and the source region of the transfer tube NMOS of transmission identical dataBetween 12 and 14, and the drain region of storing the driving tube NMOS of identical data in the 2nd DICE unitBetween 20 and 22, and between the source region 24 and 26 of the transfer tube NMOS of transmission identical data.
As Fig. 3, shown in Fig. 4, described trap area of isolation 201,202,203 is effectively stablized N trap voltage,Greatly reduce between responsive PMOS and nmos device drain region because parasitical bipolar transistor effect is drawnThere is the probability of upset in the multiple memory nodes that rise. Wherein region 201) to be in the layout of respectively a DICE mono-In unit, store between the load pipe PMOS drain region 01 and the drain region 06 of driving tube NMOS of different pieces of information,And the 2nd store load pipe PMOS drain region 15 and the driving tube NMOS of different pieces of information in DICE unitDrain region 20 between. Region 202 is in the layout of respectively the load of storing different pieces of information in a DICE unitBetween pipe PMOS drain region 02 and the drain region 07 of driving tube NMOS, and deposit in the 2nd DICE unitBetween the load pipe PMOS drain region 16 and the drain region 21 of driving tube NMOS of storage different pieces of information. Region 203Be in the layout of respectively load pipe PMOS drain region 03 and the driving tube of in a DICE unit, storing different pieces of informationBetween the drain region 08 of NMOS, and in the 2nd DICE unit, store the load pipe PMOS of different pieces of informationBetween the drain region 22 of drain region 17 and driving tube NMOS.
The content not being described in detail in description of the present invention belongs to those skilled in the art's known technology.

Claims (9)

1. the anti-SEU multiple node upset of a trap isolated form memory cell domain structure, is characterized in that comprisingThe first trap area of isolation (201), the second trap area of isolation (202), triple-well area of isolation (203), theOne DICE unit area (101,103,105,107), the 2nd DICE unit area (102,104,106,108), wherein
The first trap area of isolation (201), the second trap area of isolation (202), triple-well area of isolation (203)All all formed by N trap, above N trap, be provided with contact hole structure;
The one DICE unit area (101,103,105,107) be decomposed into four identical piece regions (101),Piece region (103), piece region (105), piece region (107), the 2nd DICE unit area (102,104,106,108) be decomposed into four identical piece regions (102), piece region (104), piece region (106),Piece region (108), each region includes one-level latch structure, transfer tube, wherein, one-level latch knotStructure comprises PMOS load pipe, the NMOS driving tube of common grid, and transfer tube comprises with NMOS driving tube commonThe nmos pass transistor in drain region;
The first trap area of isolation (201), the second trap area of isolation (202), triple-well area of isolation (203)Intersect and be in the layout of a DICE unit area (101,103,105,107), the 2nd DICE cellular zoneIn territory (102,104,106,108).
2. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the first described trap area of isolation (201) and the second trap area of isolation (202)Be in the layout of respectively load pipe PMOS drain region (01) and (03) of in a DICE unit, storing identical dataBetween, and load pipe PMOS drain region (15) and (17) of in the 2nd DICE unit, storing identical dataBetween.
3. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the second described trap area of isolation (202) and triple-well area of isolation (203)Be in the layout of respectively load pipe PMOS drain region (02) and (04) of in a DICE unit, storing identical dataBetween, and load pipe PMOS drain region (16) and (18) of in the 2nd DICE unit, storing identical dataBetween.
4. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the first described trap area of isolation (201) and the second trap area of isolation (202)Be in the layout of respectively the driving tube NMOS that stores identical data in a DICE unit drain region (05) and(07) between, and between the source region (11) and (13) of the transfer tube NMOS of transmission identical data,And the 2nd drain region (19) and (21st) of storing the driving tube NMOS of identical data in DICE unitBetween, and between the source region (23) and (25) of the transfer tube NMOS of transmission identical data.
5. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the second described trap area of isolation (202) and triple-well area of isolation (203)Be in the layout of respectively the driving tube NMOS that stores identical data in a DICE unit drain region (06) and(08) between, and between the source region (12) and (14) of the transfer tube NMOS of transmission identical data,And the 2nd drain region (20) and (22nd) of storing the driving tube NMOS of identical data in DICE unitBetween, and between the source region (24) and (26) of the transfer tube NMOS of transmission identical data.
6. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the first described trap area of isolation (201) is in the layout of in a DICE unit to be depositedBetween the storage load pipe PMOS drain region (01) of different pieces of information and the drain region (06) of driving tube NMOS,And the 2nd store load pipe PMOS drain region (15) and the driving tube NMOS of different pieces of information in DICE unitDrain region (20) between.
7. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: the second described trap area of isolation (202) is in the layout of in a DICE unit to be depositedBetween the storage load pipe PMOS drain region (02) of different pieces of information and the drain region (07) of driving tube NMOS,And the 2nd store load pipe PMOS drain region (16) and the driving tube NMOS of different pieces of information in DICE unitDrain region (21) between.
8. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: described triple-well area of isolation (203) is in the layout of in a DICE unit to be depositedBetween the storage load pipe PMOS drain region (03) of different pieces of information and the drain region (08) of driving tube NMOS,And the 2nd store load pipe PMOS drain region (17) and the driving tube NMOS of different pieces of information in DICE unitDrain region (22) between.
9. the anti-SEU multiple node upset of a kind of trap isolated form according to claim 1 memory cell domainStructure, is characterized in that: described piece region (101) is adjacent with piece region (102), piece region (103)Adjacent with piece region (104), piece region (105) is adjacent with piece region (106), piece region (107)Adjacent with piece region (108), the first trap area of isolation (201) is positioned at piece region (102) and piece region(103) between, the second trap area of isolation (202) be positioned at piece region (104), piece region (105) itBetween, triple-well area of isolation (203) is positioned between piece region (106), piece region (107), wherein,PMOS load pipe drain region in each piece region, NMOS driving tube drain region storage data, NMOS crystalline substanceBody pipe transmission data.
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CN106847332A (en) * 2016-12-23 2017-06-13 西安空间无线电技术研究所 A kind of SRAM memory cell SEL reinforcement means of low consumption of resources
CN108055032A (en) * 2018-01-09 2018-05-18 中国科学院微电子研究所 A kind of latch of anti-binode overturning
CN112131819A (en) * 2020-09-16 2020-12-25 中国电子科技集团公司第五十八研究所 DICE structure-based SRAM (static random Access memory) storage unit reinforcing method and SRAM storage array

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
CN105932986A (en) * 2016-05-27 2016-09-07 湖南融创微电子有限公司 D flip-flop
CN105932986B (en) * 2016-05-27 2019-01-22 湖南融创微电子有限公司 D type flip flop
CN106847332A (en) * 2016-12-23 2017-06-13 西安空间无线电技术研究所 A kind of SRAM memory cell SEL reinforcement means of low consumption of resources
CN108055032A (en) * 2018-01-09 2018-05-18 中国科学院微电子研究所 A kind of latch of anti-binode overturning
CN112131819A (en) * 2020-09-16 2020-12-25 中国电子科技集团公司第五十八研究所 DICE structure-based SRAM (static random Access memory) storage unit reinforcing method and SRAM storage array
CN112131819B (en) * 2020-09-16 2022-08-02 中国电子科技集团公司第五十八研究所 DICE structure-based SRAM (static random Access memory) storage unit reinforcing method and SRAM storage array

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