CN112131819B

CN112131819B - DICE structure-based SRAM (static random Access memory) storage unit reinforcing method and SRAM storage array

Info

Publication number: CN112131819B
Application number: CN202010972106.3A
Authority: CN
Inventors: 陈玉蓉; 沈婧; 黄韵荃; 张猛华
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2022-08-02
Anticipated expiration: 2040-09-16
Also published as: CN112131819A

Abstract

The invention relates to the technical field of integrated circuits, in particular to a DICE structure-based SRAM memory cell reinforcing method and an SRAM memory array. The method comprises the following steps: on the basis of a circuit design double-interlocking storage unit DICE structure, an NMOS isolation tube is added between NMOS tubes which can not share a source end and a drain end and have a switching function, and the grid electrode of the added NMOS isolation tube is connected with GND. The problem of in the prior art of territory, between the adjacent NMOS pipe, can produce the leakage current under total dose radiation is solved. Sensitive MOS tubes in circuit design are crossly arranged on the aspect of layout, and the distance of sensitive nodes is enlarged, so that the probability of circuit turnover during single-particle radiation is greatly reduced. The effect that the SRAM memory cell and the SRAM array have the radiation resistance capability on the premise of not influencing the functions is achieved.

Description

DICE structure-based SRAM (static random Access memory) storage unit reinforcing method and SRAM storage array

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a DICE structure-based SRAM memory cell reinforcing method and an SRAM memory array.

Background

SRAM (Static Random-Access Memory) is widely used in the aerospace field. Due to the complex space application environment, the interaction between the space high-energy charged particles and the device causes the change of the electrical parameters of the memory, and the data is wrong or lost and can not work normally, so how to ensure the normal work of the device in the radiation environment and improve the radiation resistance of the SRAM memory cell is a hotspot studied all the time.

The standard SRAM basic memory cell structure does not have value for use in a radiating environment. In the prior art, transistors are isolated from each other by field oxygen. In a conventional environment, the field oxide has no conducting channel and does not have leakage current, while in a radiation environment, an inversion type leakage channel under the field oxide is likely to be formed, so that the leakage channel extends to a source/drain region of an adjacent NMOS, and the leakage current is generated between adjacent NMOS tubes. Meanwhile, single particle radiation may also cause device upset and functional failure.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a method for reinforcing an SRAM memory cell based on a DICE structure and an SRAM memory array, so as to solve the problems in the prior art.

According to a first aspect, an embodiment of the present invention provides a method for reinforcing an SRAM memory cell based on a DICE structure, where the method includes:

on the basis of a circuit design double-interlocking storage unit DICE structure, an NMOS isolation tube is added between NMOS tubes which can not share a source end and a drain end and have the switch function, and the grid electrode of the NMOS isolation tube is connected with GND.

Optionally, the method further includes:

and adding a P isolation ring to the NMOS of the common source end in the SRAM memory cell according to a preset rule.

Optionally, the P isolation ring is connected to GND.

Optionally, the method further includes:

and adding an N isolation ring to the PMOS of the common source end in the SRAM memory cell according to a preset rule.

Optionally, the N isolation ring is connected to VDD.

Optionally, VDD and GND of the SRAM memory cell are criss-crossed to form a cross.

Optionally, VDD and GND in the lateral layout of the SRAM memory cell are made of three aluminum.

Optionally, five aluminum are used for VDD and GND in the vertical layout in the SRAM memory cell.

Optionally, the method further includes:

and performing cross layout on the sensitive MOS tubes in the aspect of layout, so that the distance between each pair of sensitive nodes is the same and the maximum distance is achieved at the same time.

Based on the two-point cell reinforcement, an SRAM memory array based on a DICE structure is provided, and the SRAM memory array is manufactured by the method of the first aspect.

On the basis of circuit design DICE structure, an NMOS isolation tube is added between NMOS tubes which can not share a source end and a drain end and have a switch function, and the grid of the added NMOS isolation tube is connected with GND, so that no leakage path exists after adjacent NMOS tubes are isolated, and the leakage influence on a storage unit caused by total dose radiation is solved.

Sensitive node pairs which are easy to turn over are arranged in a crossed mode on the layout, and circuit design of a DICE structure is combined, so that the single-event turning probability is greatly reduced, the circuit can have repair time, and the single-event resistance of a unit is improved.

On the basis of unit reinforcement, each storage unit in the array is isolated by the isolation ring by adding the P isolation ring and the N isolation ring, and the isolation rings are mutually independent, so that the problems of leakage current, single event upset and latch between adjacent SRAM storage units in the prior art are solved, and the effect of enabling the SRAM array to have radiation resistance on the premise of not influencing functions is achieved.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of an SRAM memory cell without an isolation transistor between two adjacent NMOS devices;

FIG. 2 is a plan view of an SRAM memory cell provided with an isolation pipe between two adjacent NMOS devices according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of an SRAM memory cell with an isolation pipe added between two adjacent NMOS devices according to an embodiment of the present invention;

FIG. 4 is a schematic plan view of a 12-transistor SRAM bitcell layout after adding an isolation transistor according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a SRAM bitcell circuit design providing a ruggedized DICE structure according to one embodiment of the present invention;

fig. 6 is a schematic diagram of an SRAM memory array after layout reinforcement according to an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

One embodiment of the present application provides a method for reinforcing an SRAM memory cell based on a DICE (dual interlocking memory cell) structure, the method being used for manufacturing a reinforced SRAM memory array, the method including:

on the basis of a circuit design DICE structure, an NMOS isolation tube is added between NMOS tubes which can not share a source end and a drain end and have a switching function, and the grid electrode of the added NMOS isolation tube is connected with GND.

The method of fabricating the DICE structure is not limited in this application.

According to the total dose radiation effect, the NMOS is mainly field oxygen strengthened, as shown in fig. 1, when the isolation tubes are not added to the two NMOS of the a tube and the C tube, the common part of the a tube and the C tube, i.e. the region 6, will cause field oxygen leakage under the influence of the total dose radiation. According to the layout, an NMOS isolation tube B tube is inserted between a tube A and a tube C for reinforcement, a plane view after reinforcement is shown in figure 2 (a cross section view after reinforcement is shown in figure 3), and the tube B separates a region 6 in figure 1, so that two

ends

2 and 3 are not isolated by field oxygen, but are isolated by a tube B with a grid end connected with GND. The gate of the B tube is connected with GND, so that the B tube is always in an off-working state, the function of the storage unit is not influenced, and the field leakage caused by the total dose effect can be prevented. According to the reinforcing mode, the field oxygen reinforcing design is carried out on the SRAM bitcell, as shown in FIG. 4, in the layout part of the NMOS tube, regions 15-36 in the figure are mutually isolated, and a channel formed by field oxygen leakage caused by total dose radiation of a transistor source and drain end does not exist, so that the function of the circuit is influenced or even fails.

Namely, on the basis of the circuit design DICE structure, an NMOS isolation tube is added between NMOS tubes which can not share a source end and a drain end and have the switch function, and the grid electrode of the added NMOS isolation tube is connected with GND, so that no leakage path exists after adjacent NMOS tubes are isolated, and the leakage influence on a storage unit caused by total dose radiation is solved.

Optionally, in the above embodiment, the method may further include: and adding a P isolation ring to the NMOS of the common source end in the SRAM memory cell according to a preset rule, wherein the P isolation ring is connected with GND. Similarly, an N isolation ring is added to the PMOS of the common source end in the SRAM memory cell according to a preset rule, and the N isolation ring is connected with VDD.

By adding the P isolating ring and the N isolating ring, each storage unit in the array is isolated by the isolating ring and is mutually independent, and the effect that the SRAM storage array has the radiation resistance capability on the premise of not influencing the function is achieved.

According to the single event upset effect, the layout design of the transistors P1-P4 and N5-N8 is performed on the circuit design of the SRAM memory cell based on the DICE structure, as shown in fig. 5, the 13 terminal and the 13 'terminal, and the 14 terminal and the 14' terminal are sensitive node pairs, and through the layout and the cross-splicing of the transistors, the 13 terminal of the transistor P1 and the 13 'terminal of the transistor P3, the 13 terminal of the transistor N5 and the 13' terminal of the transistor N7, the 14 terminal of the transistor P2 and the 14 'terminal of the transistor P4, and the 14 terminal of the transistor N6 and the 14' of the transistor N8 are ensured, and the active region distance between the 4 pairs of sensitive nodes reaches ten times of the minimum design rule at the same time. The design increases the distance between each pair of sensitive nodes from the physical layout, and greatly reduces the probability of the two nodes turning over at the same time. When one node is overturned, the other node can be repaired, and the single event upset resistance is greatly improved.

Optionally, VDD and GND in the horizontal layout in the SRAM memory cell are made of three aluminum, and VDD and GND in the vertical layout in the SRAM memory cell are made of five aluminum.

In the aspect of layout, the distance between each pair of sensitive nodes is ensured to be relatively farthest by adding an isolation ring at a proper position and by layout, and the single event upset effect generated by radiation and some influences on a storage unit caused by single event latching are solved. The layout has compact structure and proper area, improves the effects of resisting total dose radiation effect, single-particle upset effect and single-particle latch, has wide applicability, and is particularly suitable for the situation that commercial process lines do not adopt any radiation reinforcement measures in the process aspect. According to the design of the SRAM bitcell, the whole SRAM memory array adopts the layout as shown in figure 6, each SRAM bitcell is mutually isolated by an isolation ring, the units are turned and spliced up and down, and the power supply and the ground wire are criss-cross, so that the radiation resistance of the SRAM memory array is improved, the function is not influenced, and the area is saved.

The application also provides an SRAM memory array which is manufactured by the method and is not described herein again.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A SRAM memory cell reinforcing method based on a DICE structure is characterized by comprising the following steps:

on the basis of a circuit design double-interlocking storage unit DICE structure, an NMOS isolation tube is added between NMOS tubes which do not share a source end and a drain end and have a switching function at the same time, and the grid electrode of the added NMOS isolation tube is connected with GND;

the SRAM memory cell based on the DICE structure comprises transistors P1-P4 and N5-N12; P1-P4 are pull-up tubes, N5-N8 are access tubes, N9-N12 are transmission tubes, WP is a word line, and the transmission tube is controlled to be switched on and off; BL _, BL1, BL1_, BL are independent bit lines, N _A 、N _B 、N _C The isolation tube on the layout is used for preventing electric leakage;

the source ends of the pull-up tubes P1-P4 are all connected with VDD, and the drain ends are respectively connected with the source ends of the access tubes N5-N8; the grid end of the upward pulling pipe P1 is connected with the drain end of the upward pulling pipe P4, the grid end of the upward pulling pipe P2 is connected with the drain end of the upward pulling pipe P1, the grid end of the upward pulling pipe P3 is connected with the drain end of the upward pulling pipe P2, and the grid end of the upward pulling pipe P4 is connected with the drain end of the upward pulling pipe P3;

the drain terminals of the access pipes N5-N8 are all grounded, the gate terminal of the access pipe N5 is connected with the source terminal of the access pipe N6, the gate terminal of the access pipe N6 is connected with the source terminal of the access pipe N7, the gate terminal of the access pipe N7 is connected with the source terminal of the access pipe N8, and the gate terminal of the access pipe N8 is connected with the source terminal of the access pipe N5;

the gate ends of the transmission tubes N9-N12 are all connected with a word line WP, and the drain ends are respectively connected with independent bit lines BL _, BL1, BL1 _andBL; the source end of the transmission pipe N9 is connected with the source end of the access pipe N5, the source end of the transmission pipe N10 is connected with the source end of the access pipe N6, the source end of the transmission pipe N11 is connected with the source end of the access pipe N7, and the source end of the transmission pipe N12 is connected with the source end of the access pipe N8;

isolation tube N _A 、N _B 、N _C The gate ends of the transistors are grounded, the source ends are respectively connected with BL _, BL1 and BL1_, and the drain ends are respectively connected with the source ends of the transmission tubes N10-N12.

2. The method of claim 1, further comprising:

3. The method of claim 2, wherein the P-isolator is tied to GND.

4. The method of claim 1, further comprising:

5. The method of claim 4, wherein the N-spacer rings VDD.

6. The method of any one of claims 1 to 5, wherein VDD and GND of the SRAM memory cells are crisscrossed to form a cross.

7. The method of claim 6, wherein VDD and GND of the lateral layout in the SRAM memory cell are made of three aluminum.

8. The method according to claim 6, wherein VDD and GND of the vertical layout in the SRAM memory cell adopt five aluminum.

9. The method of any of claims 1 to 5, further comprising: and performing cross layout on the sensitive MOS tubes in the aspect of layout, so that the distance between each pair of sensitive nodes is the same and the maximum distance is achieved at the same time.

10. An SRAM memory array based on a DICE structure, wherein the SRAM memory array is fabricated by the method of any one of claims 1 to 9.