CN103811487A - Digital integrated circuit filling unit for inhibiting single event effect charge diffusion - Google Patents
Digital integrated circuit filling unit for inhibiting single event effect charge diffusion Download PDFInfo
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- CN103811487A CN103811487A CN201410025758.0A CN201410025758A CN103811487A CN 103811487 A CN103811487 A CN 103811487A CN 201410025758 A CN201410025758 A CN 201410025758A CN 103811487 A CN103811487 A CN 103811487A
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Abstract
The invention relates to the field of the design of a radiation hardened integrated circuit in microelectronics, and provides a digital integrated circuit filling unit for inhibiting single event effect charge diffusion to inhibit the diffusion of charge generated in SEE in a chip. An N trap at the upper part of the filling unit downwards extends and a P type active area as a substrate contact at the lower part of the filling unit upwards extends, so as to form a figure shape, and either a guard ring or guard drain structure is formed by the figure shape. The digital integrated circuit filling unit is mainly applied to the design of the radiation hardened integrated circuit in microelectronics.
Description
Technical field
The present invention relates to the radiation hardened integrated circuit design field in microelectronics, relate in particular to the radiation hardening that uses layout techniques, specifically, relate to the design of the digital integrated circuit filler cells that suppresses the diffusion of single particle effect electric charge.
Background technology
The progress of integrated circuit fabrication process causes current densities increase, device pitch to reduce, the diffusion of the ionization electric charge that single particle bombarding semiconductor produces in chip, can cause adjacent sensitizing range and be subject to single particle effect (Single Event Effect simultaneously, SEE) impact of electric charge, cause multiple node upset (Multi-node Upset, or multidigit upset (Multi-bit Upset, MBU) MNU).Radiation hardening method (Radiation-Hard By Design, RHBD) based on design conventionally in system-level, circuit level by increasing redundancy structure storage information, with the level errors that SEE is brought out shield, error detection or error correction.But traditional RHBD scheme is many only has a node to be subject to the hypothesis that SEE disturbs based on any time, MNU and MBU likely can cause the inefficacy of said method.On the other hand, based on RHBD, MNU and MBU are carried out to radiation hardening meeting because need more redundancy structure to affect area, power consumption and the performance of circuit.Take the five mould redundancy methods that carry out error correction for 2 bit mistakes as example, than the circuit without reinforcing, this scheme can be brought the area and the power consumption expense that exceed 400%, and because increase the path delay that uses voting machine circuit to bring.
Suppress the diffusion chip of SEE electric charge from source and be to carry out for MNU and MBU the positive method of radiation hardening.At present, existing more bibliographical information Guard-Ring(GR) and Guard-Drain(GD) structure to suppressing the effect of SEE electric charge diffusion.Wherein, GR is the heavily doped region of the same type with transistor substrate.For P type substrate N-well process, P type GR(PGR) and N-type GR(NGR) be made in respectively in substrate and N trap, and be connected to respectively ground GND and power vd D, hole and the electronics that therefore can produce for absorbing SEE respectively.GD is and the doped region of transistor substrate type opposite.GD is as reverse-biased PN junction, and electronics or the hole that can produce the SEE occurring in close region absorb, thereby reduce the quantity of electric charge that sensitive circuit node absorbs.Another method that can limit electric charge diffusion is that adjacent circuit unit is made in discrete N trap, stops the diffusion of electric charge in same N trap with this.
Summary of the invention
For overcoming the deficiencies in the prior art; the diffusion of the electric charge that realization inhibition SEE produces in chip; the technical solution used in the present invention is; suppress the digital integrated circuit filler cells of single particle effect electric charge diffusion; the N trap on filler cells top is to downward-extension; upwards extend the P type active area as substrate contact of bottom, forms graphics shape, and this graphics shape forms guard ring (Guard-Ring) or (Guard-Drain) structure is leaked in protection.
The graphics shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: the N well area on top is vacated a groove, and the P type active area of bottom extends upward into this groove.
The figure shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: top N trap extends downward the groove of P type active area, bottom from a side, and P type active area, bottom extends upwardly into the groove of N trap from opposite side.
The graphics shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: N well area top is U-shaped, at U-shaped middle part, N trap is with Y-shaped to downward-extension, and the blank space of all N traps is upwards extended and filled in the P type active area of bottom.
Technical characterstic of the present invention and effect:
1,, by layout design, reduced the join domain of N trap between standard cell circuit that filler cells splices, and then reduced because N trap connects the SEE electric charge causing and spread.
2, introduce GD structure in the latter half (the filler cells domain shown in Fig. 2, Fig. 3) of filler cells, help to absorb the electronics that SEE produces, stop its diffusion in chip.
3, according to filler cells width originally, it is carried out to corresponding domain transformation, do not use extra metal line, for integrated circuit layout, wiring does not exert an influence, completely compatible with standard digital design cycle.
Accompanying drawing explanation
Fig. 1 be the present invention propose the 1st) plant the domain structure of filler cells,
Fig. 2 be the present invention propose the 2nd) plant the domain structure of filler cells,
Fig. 3 be the present invention propose the 3rd) plant the domain structure of filler cells.
Embodiment
For large scale digital circuit, GR and GD technology are applied to the design of standard cell lib, the radiation hardening effect that these two kinds of methods can be brought is integrated in the standard design flow process of automation.Filler cells (Filler), as the conventional and indispensable unit in standard cell lib, only for keeping the continuity of N trap, VDD line and GND line, itself does not have any logic function conventionally.But, by the domain of filler cells is carried out to radioresistance transformation, can make it possess the structure of GR and GD.Meanwhile, can in filler cells, form the part isolation to N trap, thereby effectively suppress the diffusion of electric charge in N trap.
The present invention has proposed the domain structure example of three class filler cells altogether.In these three kinds of filler cells, be equipped with the contact of N-type active area as N trap, be equipped with P type active area as substrate contact, N-type active area is connected to first layer metal by contact hole and is connected to power supply again, and P type active area is connected to first layer metal by contact hole and is connected to ground again; Generally, N well area is on the top of filler cells, and P type active area is in the bottom of filler cells, and the domain of these three kinds of filler cells has respectively following structure:
1) in the domain of the first radioresistance filler cells, the N well area on top is vacated a groove, and the P type active area of bottom extends upward into this groove.
2) in the domain of the second radioresistance filler cells, in the N well area on top, vacate a groove, a groove is also vacated in the P type active area of bottom, and top N trap extends downward the groove of P type active area, bottom from a side, and P type active area, bottom extends upwardly into the groove of N trap from opposite side.
3) N well area top is U-shaped, and at U-shaped middle part, N trap is with Y-shaped to downward-extension, and the blank space of all N traps is upwards extended and filled in the P type active area of bottom.
The present invention proposes the layout design method of the filler cells of reinforcing for SEE, the diffusion of the electric charge that this filler cells can produce for inhibition SEE in chip.
Fig. 1, Fig. 2 and Fig. 3 have shown respectively the domain of the filler cells of reinforcing for single particle effect of three kinds of different in width.In Fig. 1, the mid portion of N well area reserves a groove, has so just greatly reduced the N trap join domain of the standard cell splicing with it in this left side, unit and right side.In fact, in this case, only have the connected region on this filler cells N trap top connecting the left and right standard cell of splicing with it.Reducing of connected region, spreads the ionization electric charge that effectively stops the SEE occurring in the standard cell region of splicing with it in left side (right side) to produce to another side.Meanwhile, the latter half of N trap inside grooves and this filler cells is used P type active area to form PGR, the hole producing in order to absorb SEE in substrate.The NGR that N trap forms via N-type active area is connected to power line by contact hole, and the PGR that P type active area forms is connected to ground wire via contact hole, and power and ground forms by the first metal layer.
In Fig. 2, the N well area of filler cells is except having reserved groove, and the N trap arm on its right side extends to the latter half of filler cells.This structure has reduced the left and right join domain of the standard cell circuit N trap of splicing with it, has formed a GD structure being made up of N trap and P type substrate simultaneously on P type substrate.This structure can be absorbed in the SEE electronics spreading in substrate, and this part absorbed electronics will be conducted to power line via N-type active area.
In Fig. 3, reserved two grooves in the N well area of filler cells, the N trap arm at its middle part extends to the latter half of filler cells, has formed GD structure with P type substrate.This structure can be absorbed in the SEE electronics spreading in substrate, and the N trap arm via middle part is absorbed into power line by this part absorbed electronics.P type active area extends among two grooves of part on filler cells, will form the PGR absorbing for SEE hole.In the filler cells of this structure, because filler cells size is larger, therefore left and right standard cell circuit distant of splicing with it, its N trap only connects via top is local, has reduced join domain.
According to filler cells width originally, select corresponding layout pattern in Fig. 1, Fig. 2 or Fig. 3 to transform it.Meanwhile, in the time of the domain of design other standards unit, should consider in advance the design rule problem that the filler cells domain proposing with the present invention may occur while splicing.
Claims (4)
1. one kind is suppressed the digital integrated circuit filler cells of single particle effect electric charge diffusion; it is characterized in that; the N trap on filler cells top is to downward-extension; upwards extend the P type active area as substrate contact of bottom; form graphics shape, this graphics shape forms guard ring (Guard-Ring) or (Guard-Drain) structure is leaked in protection.
2. the digital integrated circuit filler cells of inhibition single particle effect electric charge diffusion as claimed in claim 1, it is characterized in that, the graphics shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: the N well area on top is vacated a groove, and the P type active area of bottom extends upward into this groove.
3. the digital integrated circuit filler cells of inhibition single particle effect electric charge diffusion as claimed in claim 1, it is characterized in that, the figure shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: top N trap extends downward the groove of P type active area, bottom from a side, and P type active area, bottom extends upwardly into the groove of N trap from opposite side.
4. the digital integrated circuit filler cells of inhibition single particle effect electric charge diffusion as claimed in claim 1, it is characterized in that, the graphics shape of the P type active area as substrate contact of the N trap on filler cells top and bottom is specially: N well area top is U-shaped, at U-shaped middle part, N trap is with Y-shaped to downward-extension, and the blank space of all N traps is upwards extended and filled in the P type active area of bottom.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410025758.0A CN103811487A (en) | 2014-01-20 | 2014-01-20 | Digital integrated circuit filling unit for inhibiting single event effect charge diffusion |
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| CN201410025758.0A CN103811487A (en) | 2014-01-20 | 2014-01-20 | Digital integrated circuit filling unit for inhibiting single event effect charge diffusion |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932986A (en) * | 2016-05-27 | 2016-09-07 | 湖南融创微电子有限公司 | D flip-flop |
| US10635775B2 (en) | 2017-07-04 | 2020-04-28 | Samsung Electronics Co., Ltd. | Integrated circuit including filler cell |
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| US5406513A (en) * | 1993-02-05 | 1995-04-11 | The University Of New Mexico | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
| CN2849970Y (en) * | 2005-11-25 | 2006-12-20 | 联华电子股份有限公司 | Semiconductor structure |
| CN1988150A (en) * | 2005-12-23 | 2007-06-27 | 上海华虹Nec电子有限公司 | Static discharging protective element structure for improving trigger effect |
| CN101295715A (en) * | 2007-04-29 | 2008-10-29 | 联华电子股份有限公司 | High-voltage wireless radio frequency power element |
| WO2013078439A2 (en) * | 2011-11-22 | 2013-05-30 | Silicon Space Technology Corporation | Memory circuit incorporating radiation hardened memory scrub engine |
| US20130168818A1 (en) * | 2008-07-31 | 2013-07-04 | International Business Machines Corporation | Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits |
| CN203721724U (en) * | 2014-01-20 | 2014-07-16 | 天津大学 | Digital integrated circuit packing unit capable of restraining single event effect charge diffusion |
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2014
- 2014-01-20 CN CN201410025758.0A patent/CN103811487A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5406513A (en) * | 1993-02-05 | 1995-04-11 | The University Of New Mexico | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
| CN2849970Y (en) * | 2005-11-25 | 2006-12-20 | 联华电子股份有限公司 | Semiconductor structure |
| CN1988150A (en) * | 2005-12-23 | 2007-06-27 | 上海华虹Nec电子有限公司 | Static discharging protective element structure for improving trigger effect |
| CN101295715A (en) * | 2007-04-29 | 2008-10-29 | 联华电子股份有限公司 | High-voltage wireless radio frequency power element |
| US20130168818A1 (en) * | 2008-07-31 | 2013-07-04 | International Business Machines Corporation | Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits |
| WO2013078439A2 (en) * | 2011-11-22 | 2013-05-30 | Silicon Space Technology Corporation | Memory circuit incorporating radiation hardened memory scrub engine |
| CN203721724U (en) * | 2014-01-20 | 2014-07-16 | 天津大学 | Digital integrated circuit packing unit capable of restraining single event effect charge diffusion |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932986A (en) * | 2016-05-27 | 2016-09-07 | 湖南融创微电子有限公司 | D flip-flop |
| CN105932986B (en) * | 2016-05-27 | 2019-01-22 | 湖南融创微电子有限公司 | D type flip flop |
| US10635775B2 (en) | 2017-07-04 | 2020-04-28 | Samsung Electronics Co., Ltd. | Integrated circuit including filler cell |
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Application publication date: 20140521 |