CN2849970Y - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
CN2849970Y
CN2849970Y CN 200520132125 CN200520132125U CN2849970Y CN 2849970 Y CN2849970 Y CN 2849970Y CN 200520132125 CN200520132125 CN 200520132125 CN 200520132125 U CN200520132125 U CN 200520132125U CN 2849970 Y CN2849970 Y CN 2849970Y
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China
Prior art keywords
conductivity type
wellblock
integrated circuit
semiconductor structure
doped region
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Expired - Fee Related
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CN 200520132125
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Chinese (zh)
Inventor
许村来
陈佑嘉
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN 200520132125 priority Critical patent/CN2849970Y/en
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  • Semiconductor Integrated Circuits (AREA)

Abstract

The utility model relates to a semiconductor structure which comprises a first conduction type substrate, a first conduction type drainage area, an integrated circuit area, an isolation structure and a second conduction type doping area, wherein the first conduction type drainage area is arranged in the first conduction type substrate, the integrated circuit area is arranged on the first conduction type drainage area, an isolation structure is arranged in the first conduction type substrate and surrounds the integrated circuit area, and the second conduction type doping area is arranged in the first conduction type substrate and surrounds the isolation structure.

Description

Semiconductor structure
Technical field
The utility model relates to a kind of semiconductor structure, relates in particular to a kind of semiconductor structure that can prevent noise jamming.
Background technology
Because at very lagre scale integrated circuit (VLSIC) (Very Large Scale Integration, VLSI) and great scale integrated circuit (Ultra Large Scale Integration, ULSI) in, distance between the integrated circuit is also more and more nearer, and the capacitive coupling that is produced between integrated circuit (capacitive coupling) can produce some noises or crosstalk (cross-talk) signal.When the size of integrated circuit descends always, characteristic size (critical dimension) also and then diminishes, and the capacitive coupling between the then adjacent integrated circuit and the problem of noise are also just serious more.
Fig. 1 illustrate is the top view of existing a kind of semiconductor structure.Fig. 2 illustrate is the profile along Fig. 1 section line A-A '.
Please in P type substrate 100, have p type wells district 102, integrated circuit district 104, isolation structure 106, N type wellblock 108 and N type deep well area 110 simultaneously with reference to Fig. 1 and Fig. 2.Noise isolation design at present commonly used be that setting comes noise is isolated by N type wellblock 108 formed guard rings (guard ring) or form the mode of N type deep well area 110 below the integrated circuit district outside integrated circuit district 104.
Yet, in frequency of operation during, between N type wellblock 108 and the p type wells district 102, be easy to generate junction capacitance (junctioncapacitance) between N type deep well area 110 and p type wells district 102, N type deep well area 110 and P type substrate 100 and N type wellblock 108 and the P type substrate 100 greater than 1,000,000,000 hertz (GHz).Therefore noise can be coupled in the integrated circuit district 104 by the junction capacitance that is produced at P type substrate 100, and overall noise increases in the integrated circuit district 104 and cause, even the running of integrated circuit is caused harmful effect.
The utility model content
In view of this, the purpose of this utility model provides a kind of semiconductor structure, and effectively noise isolation avoids noise to enter in the integrated circuit district.
Another purpose of the present utility model provides a kind of semiconductor structure, can avoid integrated circuit to be subjected to noise jamming.
The utility model proposes a kind of semiconductor structure, comprise the first conductivity type substrate, the first conductivity type wellblock, integrated circuit district, isolation structure and the second conductivity type doped region.The first conductivity type wellblock is arranged in the first conductivity type substrate.The integrated circuit district is arranged on the first conductivity type wellblock.Isolation structure is arranged in the first conductivity type substrate and around the integrated circuit district.The second conductivity type doped region is arranged in the first conductivity type substrate and around isolation structure.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, also comprise the second conductivity type wellblock, be arranged in the first conductivity type substrate and, and the second conductivity type doped region is arranged in the second conductivity type wellblock around isolation structure.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, the doping content of the second conductivity type doped region is greater than the second conductivity type wellblock.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, the second conductivity type doped region is electrically connected to a predeterminated voltage.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, predeterminated voltage comprises ground connection.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, isolation structure comprises shallow slot isolation structure.
The utility model proposes a kind of semiconductor structure, comprise the first conductivity type substrate, the first conductivity type wellblock, integrated circuit district, isolation structure, the second conductivity type wellblock, the second conductivity type doped region and the second conduction type deep well area.The first conductivity type wellblock is arranged in the first conductivity type substrate.The integrated circuit district is arranged on the first conductivity type wellblock.Isolation structure is arranged in the first conductivity type substrate and around the integrated circuit district.The second conductivity type wellblock is arranged in the first conductivity type substrate and around isolation structure.The second conductivity type doped region is arranged in the second conductivity type wellblock and around isolation structure.The second conduction type deep well area is arranged in the first conductivity type substrate of first conductivity type wellblock below and with the second conductivity type wellblock and is connected.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, the doping content of the second conductivity type doped region is greater than the second conductivity type wellblock.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, the second conductivity type doped region is electrically connected to a predeterminated voltage.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, predeterminated voltage comprises ground connection.
Described according to a preferred embodiment of the present utility model, in above-mentioned semiconductor structure, isolation structure comprises shallow slot isolation structure.
Owing to have by the formed guard ring of the second conductivity type doped region in the semiconductor structure of the present utility model, can avoid noise to enter in the integrated circuit district effectively, so integrated circuit can stably be operated.Therefore in addition, in semiconductor structure of the present utility model, the second conductivity type doped region can be isolated most noise, can reduce the noise that is coupled to via junction capacitance in the integrated circuit district.
For above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrate is the top view of existing a kind of semiconductor structure;
Fig. 2 illustrate is the profile along Fig. 1 section line A-A ';
Fig. 3 illustrate is the top view of the semiconductor structure of the utility model one embodiment;
Fig. 4 illustrate is the profile along Fig. 3 section line B-B ';
Fig. 5 illustrate is the top view of the semiconductor structure of another embodiment of the utility model;
Fig. 6 illustrate is the profile along Fig. 5 section line C-C '.
The main element symbol description
100:P type substrate
102:P type and district
104,204,304: the integrated circuit district
106,206,306: isolation structure
108:N type wellblock
The 110:N type deep well area
200,300: the first conductivity type substrates
202,302: the first conductivity type wellblocks
208,308: the second conductivity type doped regions
210,310: the second conductivity type wellblocks
312: the second conduction type deep well area
Embodiment
Fig. 3 illustrate is the top view of the semiconductor structure of the utility model one embodiment.Fig. 4 illustrate is the profile along Fig. 3 section line B-B '.
Please be simultaneously with reference to Fig. 3 and Fig. 4, semiconductor structure comprises the first conductivity type substrate 200, the first conductivity type wellblock 202, integrated circuit district 204, isolation structure 206 and the second conductivity type doped region 208.
The first conductivity type substrate 200 for example is a P type silicon substrate.
The first conductivity type wellblock 202 is arranged in the first conductivity type substrate 200.The first conductivity type wellblock 202 for example is the p type wells district.The formation method of the first conductivity type wellblock 202 for example is to be that dopant carries out an ion implantation technology to silicon substrate and forms with boron.
Integrated circuit district 204 is arranged on the first conductivity type wellblock 202.Integrated circuit district 204 is for forming the zone of integrated circuit (not illustrating).Integrated circuit in the integrated circuit district 204 for example is made up of circuit elements such as resistance, electric capacity, inductance or metal-oxide semiconductor (MOS)s.Those skilled in the art can learn easily that integrated circuit can be memory circuitry, D/A conversion circuit or A/D conversion circuit etc., repeat no more in this.
Isolation structure 206 is arranged in the first conductivity type substrate 200 and around integrated circuit district 204, can become other semiconductor element or other integrated circuit district on the circuit region 204 and the first conductivity type substrate 200 in order to separated set.Isolation structure 206 for example is a shallow slot isolation structure.The material of isolation structure 206 for example is a silica.
The second conductivity type doped region 208 is arranged in the first conductivity type substrate 200 and around isolation structure 206.The second conductivity type doped region 208 for example is a N type doped region.The formation method of the second conductivity type doped region 208 for example is to be that dopant carries out an ion implantation technology and forms with phosphorus.The second conductivity type doped region 208 for example is to be electrically connected to a predeterminated voltage, and this predeterminated voltage for example is a ground connection.
In addition, also the second conductivity type wellblock 210 can be set in the first conductivity type substrate 200, and the second conductivity type wellblock 210 is around isolation structure 206, and the second conductivity type doped region 208 is arranged in the second conductivity type wellblock 210.The second conductivity type wellblock 210 for example is N type wellblock.The formation method of the second conductivity type wellblock 210 for example is to be that dopant carries out an ion implantation technology and forms with phosphorus.The doping content of the second conductivity type doped region 208 for example is greater than the second conductivity type wellblock 210.
Owing to have in the semiconductor structure by the second conductivity type wellblock, 210 formed guard rings and by the second conductivity type doped region, 208 formed guard rings, therefore can avoid integrated circuit district 204 to be subjected to noise jamming effectively.Therefore in addition, most noise is all isolated by the second conductivity type doped region 208, can reduce via the junction capacitance that is produced in the first conductivity type substrate 200 to be coupled to noise in the integrated circuit district 204.
Fig. 5 illustrate is the top view of the semiconductor structure of another embodiment of the utility model.Fig. 6 illustrate is the profile along Fig. 5 section line C-C '.
Please be simultaneously with reference to Fig. 5 and Fig. 6, semiconductor structure comprises the first conductivity type substrate 300, the first conductivity type wellblock 302, integrated circuit district 304, isolation structure 306, the second conductivity type doped region 308, the second conductivity type wellblock 310 and the second conduction type deep well area 312.
The first conductivity type substrate 300 for example is a P type silicon substrate.
The first conductivity type wellblock 302 is arranged in the first conductivity type substrate 300.The first conductivity type wellblock 302 for example is the p type wells district.The formation method of the first conductivity type wellblock 302 for example is to be that dopant carries out an ion implantation technology to silicon substrate and forms with boron.
Integrated circuit district 304 is arranged on the first conductivity type wellblock 302.Integrated circuit district 304 is for forming the zone of integrated circuit (not illustrating).Integrated circuit in the integrated circuit district 304 for example is made up of circuit elements such as resistance, electric capacity, inductance or metal-oxide semiconductor (MOS)s.Those skilled in the art can learn easily that integrated circuit can be memory circuitry, D/A conversion circuit or A/D conversion circuit etc., repeat no more in this.
Isolation structure 306 is arranged in the first conductivity type substrate 300 and around integrated circuit district 304, can become other semiconductor element or other integrated circuit district on the circuit region 304 and the first conductivity type substrate 300 in order to separated set.Isolation structure 306 for example is a shallow slot isolation structure.The material of isolation structure 306 for example is a silica.
The second conductivity type wellblock 310 is arranged in the first conductivity type substrate 300 and around isolation structure 306.The second conductivity type wellblock 310 for example is N type wellblock.The formation method of the second conductivity type wellblock 310 for example is to be that dopant carries out an ion implantation technology and forms with phosphorus.
The second conductivity type doped region 308 is arranged in the second conductivity type wellblock 310 and around isolation structure 306.The second conductivity type doped region 308 for example is a N type doped region.The doping content of the second conductivity type doped region 308 for example is greater than the second conductivity type wellblock 310.The formation method of the second conductivity type doped region 308 for example is to be that dopant carries out an ion implantation technology and forms with phosphorus.The second conductivity type doped region 308 for example is to be electrically connected to a predeterminated voltage, and this predeterminated voltage for example is a ground connection.
The second conduction type deep well area 312 is arranged in the first conductivity type substrate 300 of 302 belows, the first conductivity type wellblock and with the second conductivity type wellblock 310 and is connected.The second conduction type deep well area 312 for example is the N type deep well area.The formation method of the second conduction type deep well area 312 for example is to be that dopant carries out an ion implantation technology and forms with phosphorus.
Reach by the second conductivity type doped region, 308 formed guard rings owing to have in the semiconductor structure by the second conductivity type wellblock, 310 formed guard rings, the second conduction type deep well area 312; therefore can isolate noise effectively, can suppress noise and enter in the integrated circuit district 304.Therefore in addition, most noise is all isolated by the second conductivity type doped region 308, can reduce by the junction capacitance that is produced in the first conductivity type substrate 300 to be coupled to noise in the integrated circuit district 304.
Though first conductivity type in the various embodiments described above is to be example with the P type, and second conductivity type is to be example with the N type, but those skilled in the art are by the explanation of the foregoing description, can easily the utility model be applied in first conductivity type is that the N type and second conductivity type are the situation of P type, repeats no more in this.
In sum, the utility model has following advantage at least:
1. because have, therefore can avoid integrated circuit to be subjected to noise jamming effectively in the semiconductor structure of the present utility model by the formed guard ring of the second conductivity type doped region.
2. because noise isolation effectively, so integrated circuit can stably be operated in the semiconductor structure of the present utility model.
Therefore 3. in semiconductor structure of the present utility model, the second conductivity type doped region can be isolated most noise, can reduce the noise that is coupled to via junction capacitance in the integrated circuit district.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; under the prerequisite that does not break away from spirit and scope of the present utility model; can do a little change and retouching, therefore protection range of the present utility model is as the criterion when looking the claims person of defining.

Claims (11)

1. a semiconductor structure is characterized in that, comprising:
One first conductivity type substrate;
One first conductivity type wellblock is arranged in this first conductivity type substrate;
One integrated circuit district is arranged on this first conductivity type wellblock;
One isolation structure is arranged in this first conductivity type substrate and around this integrated circuit district; And
One second conductivity type doped region is arranged in this first conductivity type substrate and around this isolation structure.
2. semiconductor structure as claimed in claim 1 is characterized in that, also comprises one second conductivity type wellblock, be arranged in this first conductivity type substrate and around this isolation structure, and this second conductivity type doped region is arranged in this second conductivity type wellblock.
3. semiconductor structure as claimed in claim 2 is characterized in that, the doping content of this second conductivity type doped region is greater than this second conductivity type wellblock.
4. semiconductor structure as claimed in claim 1 is characterized in that, this second conductivity type doped region is electrically connected to a predeterminated voltage.
5. semiconductor structure as claimed in claim 4 is characterized in that this predeterminated voltage comprises ground connection.
6. semiconductor structure as claimed in claim 1 is characterized in that this isolation structure comprises shallow slot isolation structure.
7. a semiconductor structure is characterized in that, comprising:
One first conductivity type substrate;
One first conductivity type wellblock is arranged in this first conductivity type substrate;
One integrated circuit district is arranged on this first conductivity type wellblock;
One isolation structure is arranged in this first conductivity type substrate and around this integrated circuit district;
One second conductivity type wellblock is arranged in this first conductivity type substrate and around this isolation structure;
One second conductivity type doped region is arranged in this second conductivity type wellblock and around this isolation structure; And
One second conduction type deep well area is arranged in this first conductivity type substrate of below, this first conductivity type wellblock and with this second conductivity type wellblock and is connected.
8. semiconductor structure as claimed in claim 7 is characterized in that, the doping content of this second conductivity type doped region is greater than this second conductivity type wellblock.
9. semiconductor structure as claimed in claim 7 is characterized in that, this second conductivity type doped region is electrically connected to a predeterminated voltage.
10. semiconductor structure as claimed in claim 9 is characterized in that this predeterminated voltage comprises ground connection.
11. semiconductor structure as claimed in claim 7 is characterized in that, this isolation structure comprises shallow slot isolation structure.
CN 200520132125 2005-11-25 2005-11-25 Semiconductor structure Expired - Fee Related CN2849970Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200520132125 CN2849970Y (en) 2005-11-25 2005-11-25 Semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200520132125 CN2849970Y (en) 2005-11-25 2005-11-25 Semiconductor structure

Publications (1)

Publication Number Publication Date
CN2849970Y true CN2849970Y (en) 2006-12-20

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Application Number Title Priority Date Filing Date
CN 200520132125 Expired - Fee Related CN2849970Y (en) 2005-11-25 2005-11-25 Semiconductor structure

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811487A (en) * 2014-01-20 2014-05-21 天津大学 Digital integrated circuit filling unit for inhibiting single event effect charge diffusion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811487A (en) * 2014-01-20 2014-05-21 天津大学 Digital integrated circuit filling unit for inhibiting single event effect charge diffusion

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061220

Termination date: 20091225