CN201994298U

CN201994298U - Electrostatic discharge (ESD) protection structure of integrated circuit

Info

Publication number: CN201994298U
Application number: CN2010206617568U
Authority: CN
Inventors: 杭晓伟; 彭秋平; 张祯; 江石根; 谢卫国
Original assignee: SUZHOU HUAXIN MICROELECTRONICS CO Ltd
Current assignee: SUZHOU HUAXIN MICROELECTRONICS CO Ltd
Priority date: 2010-12-16
Filing date: 2010-12-16
Publication date: 2011-09-28
Anticipated expiration: 2020-12-16

Abstract

The utility model discloses an electrostatic discharge (ESD) protection structure of an integrated circuit. The ESD protection structure is arranged between an internal circuit of the integrated circuit and a pad and consists of a PN junction which occupies a certain area of a chip of the integrated circuit, wherein the PN junction is formed by connecting a plurality of small-area PN junctions in parallel on the occupied area of the chip, so that the volume of intrinsic silicon included in the PN junction is increased. In the ESD protection structure, the volume of the intrinsic silicon in a depletion region of the PN junction is increased without increasing the occupied area on the chip, so that the influence of energy produced by an ESD event on the circuit can be more effectively eliminated, and the anti-ESD performance of the circuit is improved.

Description

The esd protection structure of integrated circuit

Technical field

The utility model relates to technical field of integrated circuits, relates in particular to a kind of esd protection structure that can improve the integrated circuit of the anti-ESD performance of circuit.

Background technology

Along with people are more and more higher to the requirement of chip, in the application process of chip, people wish chip, and not only function is correct, has improved especially the requirement on the chip performance.And a key factor that influences chip performance is exactly ESD (Electrostatic Discharge, i.e. a static discharge), and ESD can bring destructive consequence for the electronic device environment, and it is the one of the main reasons that causes ic failure.Along with integrated circuit technology constantly develops; the characteristic size of cmos semiconductor is constantly dwindled; the gate oxide thickness of metal-oxide semiconductor (MOS) (MOS) is more and more thinner; electric current and voltage that metal-oxide-semiconductor can bear are also more and more littler; therefore to further optimize the anti-ESD performance of circuit, consider from the design of full chip esd protection structure.

Existing at metal-oxide semiconductor (MOS) pad PAD and internal circuit between adopt in the esd protection circuit of diode of PN junction type; because dissolving of intrinsic silicon need very big energy in the PN junction; the silicon that promptly dissolves several cus all needs very big energy, so diffused junction is more stable usually.So along with semi-conductive characteristic size is constantly dwindled, the volume of the silicon that comprises in the PN junction is also diminishing, and is shown in Figure 2 as Fig. 1, and wherein d1 is the PN junction of NSD/PSUB type, and d2 is the PN junction of PSD/NWell type.D1, d2 are as a whole to be arranged on the chip, and therefore when PN junction was reduced to certain area, dissolving of the intrinsic body silicon that it comprises may not effectively consume the energy that produces when esd event takes place, thereby caused the generation of esd event in the circuit.Therefore, how by improving the structure of PN junction, consume the energy that produces when more esd events take place, and avoid becoming of esd event to have in this technical field in one of technical problem that solves.

The utility model content

The purpose of this utility model is to propose a kind of esd protection structure that improves the anti-ESD performance of circuit; it on the basis of existing technology; volume by intrinsic silicon contained in the PN junction in the relative increase esd protection structure; and the energy that produces when more consuming esd event and taking place; and then avoid the generation of esd event, to improve the performance and the reliability of circuit.

For achieving the above object; the utility model proposes following technical scheme: a kind of esd protection structure of integrated circuit; it is arranged between the internal circuit and pad of integrated circuit; this esd protection structure is made up of the PN junction of the certain area of chip that takies integrated circuit; this PN junction is configured to PN junction by plural small size and is connected in parallel and forms on shared area of chip, to increase the volume of the intrinsic silicon that is comprised in the PN junction.

Wherein, the PN junction of described plural small size comprises the PN junction of second type of the PN junction of the first kind of plural small size and plural small size.

The first kind PN junction of described plural small size is the PN junction of the NSD/PSUB type that forms on the substrate of P type silicon, the PN junction of second type of described plural small size is the PN junction of the PSD/NWell type that forms on the substrate of P type silicon.

Contact area between described NSD and the PSUB is bigger than NSD in the existing protection structure and the contact area between the PSUB, and the contact area between PSD and the NWELL also increases than PSD in the existing protection structure and the contact area between the NWELL.

The form of described PN junction formation semiconductor diode is carried out esd protection to the internal circuit of integrated circuit.

The intrinsic silicon that is comprised in the described PN junction is the intrinsic silicon in the PN junction depletion region.

Compared with prior art; the esd protection structure of the integrated circuit that the utility model disclosed; it is under the situation that is not increased in shared area on the chip; increased the volume of the intrinsic silicon in the PN junction depletion region; because dissolving of intrinsic silicon need very big energy in the PN junction; thereby make more volume silicon can consume more energy, can be more effective the energy that produces of consumption esd event to the influence of circuit, improved the performance of the anti-ESD of circuit.Simultaneously, this esd protection structure does not need to change technology, the reliability height.

Description of drawings

Fig. 1 is the circuit diagram of existing esd protection structure;

Fig. 2 is the structural representation of existing esd protection structure;

Fig. 3 is the circuit diagram of the utility model esd protection structure;

Fig. 4 is the structural representation of the utility model esd protection structure.

Embodiment

Esd protection structure in the integrated circuit that the utility model disclosed is on the basis of existing technology; to carry out improvement design by integrally formed PN junction d1, d2 in the prior art (Fig. 1); do not increasing PN junction under the situation of the area that is occupied on the chip; it is designed to the internal circuit that places integrated circuit and the plural PN junction between pad PAD, and these PN junctions form the protection of ESD to the internal circuit of integrated circuit with the form of semiconductor diode.

As shown in Figure 3; the plural PN junction of esd protection structure of the present utility model comprises the PN junction d11 of a plurality of first kind and the PN junction d22 of a plurality of second types; wherein; be connected in parallel between the PN junction d11 of a plurality of first kind; it can be the PN junction as the NSD/PSUB type; also be connected in parallel between the PN junction d22 of a plurality of second types, it can be the PN junction as the PSD/NWell type.

Show in conjunction with Fig. 4, between the PN junction d11 of a plurality of first kind of connection parallel with one another, formed the PN junction of a lot of small sizes by doping, as the PN junction of NSD/PSUB and PSD/NWell type.Wherein the depletion region internal ratio existing P N of each PN junction knot comprises the intrinsic body silicon of more volume accordingly; simultaneously; contact area between NSD and the PSUB is bigger than NSD in the existing protection structure and the contact area between the PSUB, and the contact area between PSD and the NWELL also increases than PSD in the existing protection structure and the contact area between the NWELL.And because dissolving of the intrinsic body silicon of several cus need very big energy, therefore, it is then bigger to increase energy required when dissolving behind the intrinsic silicon, that is to say, the energy that the PN junction of this structure can more effective consumption esd event produces.

In like manner, PN junction d22 for a plurality of second types of connection parallel with one another, it also is the PN junction that has formed a lot of small sizes by doping, also comprised intrinsic body silicon in the depletion region of these PN junctions than existing PN junction more volume of the same area, therefore, also can more effectively consume the energy that esd event produces, and improve the performance of the anti-ESD of integrated circuit.

Technology contents of the present utility model and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present utility model and announcements and are done all replacement and modifications that does not deviate from the utility model spirit; therefore; the utility model protection range should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present utility model and modifications, and contained by the present patent application claim.

Claims

1. the esd protection structure of an integrated circuit; it is arranged between the internal circuit and pad of integrated circuit; it is characterized in that: this esd protection structure is made up of the PN junction of the certain area of chip that takies integrated circuit; this PN junction is configured to PN junction by plural small size and is connected in parallel and forms on shared area of chip, to increase the volume of the intrinsic silicon that is comprised in the PN junction.

2. the esd protection structure of integrated circuit as claimed in claim 1 is characterized in that: the PN junction of described plural small size comprises the PN junction of second type of the PN junction of the first kind of plural small size and plural small size.

3. the esd protection structure of integrated circuit as claimed in claim 2; it is characterized in that: the first kind PN junction of described plural small size is the PN junction of the NSD/PSUB type that forms on the substrate of P type silicon, and the PN junction of second type of described plural small size is the PN junction of the PSD/NWell type that forms on the substrate of P type silicon.

4. the esd protection structure of integrated circuit as claimed in claim 1 is characterized in that: the form that described PN junction forms semiconductor diode is carried out esd protection to the internal circuit of integrated circuit.

5. the esd protection structure of integrated circuit as claimed in claim 1 is characterized in that: the intrinsic silicon that is comprised in the described PN junction is the intrinsic silicon in the PN junction depletion region.