CN203760474U

CN203760474U - Special CMOS ESD original component structure

Info

Publication number: CN203760474U
Application number: CN201420103098.9U
Authority: CN
Inventors: 叶兆屏; 姚瑞琨; 林斌斌
Original assignee: GUANGZHOU CANBO ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: GUANGZHOU CANBO ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2014-03-07
Filing date: 2014-03-07
Publication date: 2014-08-06
Anticipated expiration: 2024-03-07

Abstract

The utility model discloses a special CMOS ESD original component structure. The structure is formed by a P-N-P-N four-layer semiconductor structure. The P-N-P-N four-layer semiconductor structure is provided with a gate terminal. The gate terminal is provided with a poly resistor. A GND accesses the poly resistor. The structure changes a trigger voltage and makes the voltage reach a voltage which protects an IC so that an ESD protection structure with a small area and a heavy current is used to protect the IC.

Description

A kind of special CMOS ESD original paper structure

Technical field

The utility model relates to semiconductor integrated circuit field, relates in particular to a kind of special CMOS ESD original paper structure.

Background technology

CMOS, i.e. Complementary Metal Oxide Semiconductor, is complementary metal oxide semiconductors (CMOS), voltage-controlled a kind of amplifying device.It is the elementary cell of composition cmos digital integrated circuit.ESD, i.e. Electro-Static discharge, is static discharge.Static discharge can bring destructive consequence to electronic device, is the one of the main reasons that causes ic failure.Along with integrated circuit technology development, the characteristic size of cmos circuit is constantly dwindled, the gate oxide thickness of pipe is more and more thinner, the area scale of chip is increasing, electric current and voltage that metal-oxide-semiconductor can bear are also more and more less, and peripheral environment for use does not change, therefore want the anti-ESD performance of further optimized circuit, how to make that full chip real estate is as far as possible little, ESD performance reliability meets the demands and do not need to increase extra processing step becomes the problem that IC designer mainly considers.

Summary of the invention

The purpose of this utility model is to overcome the deficiencies in the prior art, provides that a kind of cost is low, the special CMOS ESD original paper structure of dependable performance.

Above-mentioned purpose of the present utility model is achieved by following technical solution:

A kind of special CMOS ESD original paper structure, formed by P-N-P-N four-level semiconductor structure, described P-N-P-N four-level semiconductor structure is followed successively by P+ diffusion, N-well, P-substrate, N+diffusion, described P-N-P-N four-level semiconductor structure is provided with gate end, described gate end is provided with poly resistance, described poly resistance access GND.

Form basic latchup structure by this structure, add poly resistance to GND at gate end, make it produce parasitic capacitance and resistance to GND, reduce its trigger voltage.Large current path when esd discharge is provided.The trigger voltage that changes this structure makes its voltage that reaches protection IC, thereby utilizes the esd protection structure protection IC of the large electric current of small size.

Compared with prior art, the beneficial effects of the utility model are as follows:

The utility model changes trigger voltage by special CMOS ESD original paper structure makes its voltage that reaches protection IC, thereby utilizes the esd protection structure protection IC of the large electric current of small size.Its cost is low, dependable performance.Having and under unit are, have the highest ESD protective capacities compared with traditional ESD CMOS, is 5 times of above esd protection effects.And trigger voltage is lower, the chip esd protection being applied in IC design can be saved larger cost.

figure of description

Fig. 1 is structural representation of the present utility model;

Fig. 2 is that structure of the present utility model is prepared schematic diagram;

Fig. 3 is schematic diagram of the present utility model.

Embodiment

Below in conjunction with Figure of description and specific embodiment, the utility model is made further and being elaborated, but embodiment does not limit in any form the present invention.

Embodiment 1

As shown in Figure 1, a kind of special CMOS ESD original paper structure, formed by P-N-P-N four-level semiconductor structure, described P-N-P-N four-level semiconductor structure is followed successively by P+ diffusion, N-well, P-substrate, N+diffusion, described P-N-P-N four-level semiconductor structure is provided with gate end, and described gate end is provided with poly resistance, described poly resistance access GND.As Fig. 2, shown in 3, according to different processing procedures, regulate the implantation concentration in N/P region in figure, and X, Y, the distance of Z, and test by ESD, find out the optimum trigger voltage and the device area that are applicable to design voltage.

Claims

1. a special CMOS ESD original paper structure, it is characterized in that, formed by P-N-P-N four-level semiconductor structure, described P-N-P-N four-level semiconductor structure is followed successively by P+ diffusion, N-well, P-substrate, N+diffusion, described P-N-P-N four-level semiconductor structure is provided with gate end, and described gate end is provided with poly resistance, described poly resistance access GND.