(3) summary of the invention:
The present invention relates to Chinese medicine decocting pharmacy intelligence control system, the desktop in Chinese medicine decocting pharmacy arranges
Many control for decocting medicinal herbs, electricity medicine decocting tank puts Chinese medicine and water into, after sticking patient's mark, its power supply
Plug may be inserted at any time and chooses the pattern of boiling medicine and start to decoct on the socket that control for decocting medicinal herbs controls
Medicine, then inputs patient's identification code at main controller, and main controller passes through RS232 interface and host computer
Compunlcation.Typically boil medicine and begin with above warm water soaking phase half an hour, then have very hot oven,
The slow fire phases etc., at the end of boiling medicine, host computer computer shows patient's name by LED screen.Electricity is decocted
It is online that the power supply of medicinal cupping is individually connected to the outer electric power of system, and by control for decocting medicinal herbs by light electric coupling
Control bidirectional triode thyristor after device isolation to make to load energized power and time on its socket by the program of boiling medicine
Run.Main controller and each control for decocting medicinal herbs are all connected on same electric power netting twine and arrange main switch,
At the commutation diode that is followed by of main switch, system uses half wave communication and half-wave through electric lines of force to supply
Electricity, and it is respectively mounted cycle discriminator circuit in main controller and each control for decocting medicinal herbs, it is used for producing
Keep the lock in time of system system acting consistent, each installation one in its telecommunication circuit simultaneously
Communications electronics switch and switch drive module thereof.During system communication, connect all communications electronics and open
Close, communicated by electric power netting twine, before sign off, turn off all communications electronics switch.
Communication is by controlling lock in time to keep main controller and the communication operation of each control for decocting medicinal herbs
Consistent over a long time, the switch drive module of main controller and each control for decocting medicinal herbs is through electricity from power network
Resistance blood pressure lowering, just connect diode and isolate after cycle bears half-wave further, be connected to comparator input terminal,
Its reference voltage is 100Mv to 200Mv, and available diode drop obtains through electric resistance partial pressure,
Therefore the outfan of comparator is square-wave signal, and it creates after the diode rectification just connect again
Corresponding power network cycle bears the positive square-wave signal of half-wave, is connected to the I/O mouth of single-chip microcomputer, single-chip microcomputer
Performing traffic operation when scanning positive square-wave signal, this positive square-wave signal is additionally operable to drive communication electricity
Son switch, therefore communications electronics switch turns off when cycle positive half-wave, and cycle is connected when bearing half-wave.
Communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode, and carries out signal tune
Reason.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three and screens some realization to cycle
The identification decision of signal, recycling the cycle time set up lock in time, it is achieved main controller in system
Synchronous operation with each control for decocting medicinal herbs.
The cycle discriminator circuit structural representation of main controller and each control for decocting medicinal herbs as in figure 2 it is shown,
It is made up of two voltage comparators using hysteresis loop comparator, each voltage comparator all comprises
Filter circuit, the reference voltage of its voltage comparator is provided by mu balanced circuit.System arranges clock
Timer and synchrotimer.If be detected that adjacent two cycle signals are very, then take
Go out the clock timer timing time between these two adjacent cycle signal zero passages, be sequentially stored in
In cycle time memory cell, this cycle time memory cell can deposit 100 cycle times,
Often it is stored in a cycle time when being filled with, the most first removes the cycle time being stored at first, and
Calculate meansigma methods Tz of the cycle time being stored in and preserve, utilizing Tz value to differentiate cycle to be identified
Signal, to reduce the impact of power network frequency fluctuation, uses three to screen point simultaneously and reduces erroneous judgement
Probability.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.At cycle just
At the cycle zero passage of half cycle ascent stage, i.e. screening point 0 and arrange voltage zero-cross detection module, it is adopted
Negative half period, signal condition is isolated further through electric resistance partial pressure, diode with cycle positive half-wave signal
The clock end CLK of rear feeding d type flip flop, the Q of d type flip flop terminate single-chip microcomputer external interrupt mouth,
This external interrupt mouth is arranged to level triggers, the D end ground connection of d type flip flop, and S terminates single-chip microcomputer I
/ O mouth, this I/O mouth puts 1 at ordinary times.When cycle positive half-wave zero cross signal arrives, immediately its
After cycle signal rising edge make d type flip flop Q end be 0, single-chip microcomputer external interrupt mouth low level,
Thus produce interruption, interrupt service routine performs instruction: described I/O mouth sets to 0, the Central Shanxi Plain
Disconnected, timing, described I/O mouth are put 1, are opened interruption.Remaining two comparator is separately positioned on week
The ripple positive half cycle ascent stage, the examination point 1 and 50% to 70% at 35% to 50% place of crest voltage
The examination point 2 at place.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and opens
Beginning timing, when cycle voltage zero-cross, is arranged on the voltage zero-cross detection module screening point 0
In V0, the output voltage of d type flip flop jumps vanishing, produces and interrupts, records in its zero crossing
Break time Th0;Hereafter, the output of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Voltage, when week, wave voltage reached the threshold voltage of V1, output voltage saltus step from high to low,
Scanning records its bound-time Th1;Voltage comparator V2 at point 2 screened in same scanning record
Output voltage bound-time Th2, by the output electricity of Th0 and voltage zero-cross detection module V0
Pressure bound-time setting value Ts0 is made comparisons;The output voltage of Th1 and voltage comparator V1
During the output voltage saltus step of bound-time setting value Ts1 and Th2 and voltage comparator V2
Between setting value Ts2 make comparisons respectively, if in the range of allowable error, then this Zhen detected
Level signal is true, is otherwise false.Above-mentioned judge discriminator signal as true time, calculate this cycle letter
Clock timer number between zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Timing time Tzu, makes comparisons it with meansigma methods Tz of cycle time, if less than setting
Cycle time error Tzv then cycle signal is true, at this moment preserves Tzu and takes 20ms with synchronization
Timer timing time is added, and the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5ms
Between open interruption, clock timer timing to 25ms to 27ms when opening break period setting value Tk
Between pass break period setting value Tn time close interrupt.
After system boot, clock timer starts timing, when first all wave voltage mistake being detected
When zero, it is arranged on the output voltage saltus step of the voltage zero-cross detection module V0 screening point 0,
Thus producing interruption, the time T0 taking out cycle voltage over zero preserves, and clock timer is clear
Zero and start timing, at this moment cycle time voltage crosses zero Th0 is 0, and above-mentioned side pressed by single-chip microcomputer simultaneously
Method scans and judges discriminator signal.Due to detection is first cycle, clock timer be
Starting timing during cycle voltage zero-cross, the value of its Th0, Th1 and Th2 must add the cycle time
20ms deducts out the difference of break period setting value Tk, if three discriminator signals are true, takes
The time T0 of the cycle voltage over zero gone out is stored in synchrotimer as initial time, next
Secondary i.e. for the first time open the break period and take Tk.Being otherwise fictitious time, now the clock timer time must add
Upper T0, continues detection.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving inspection
Survey the cycle time, therefore the clock timer timing time between twice cycle signal zero passage be with
The cycle time, 20ms made comparisons, it is determined that cycle signal is true time, then be to take 20ms to subtract Th0
Difference be added with synchrotimer timing time, preserve the standard cycle time 20 i.e. for the first time
Ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all the most every time
Restart timing after being reset by clock timer when opening interruption, and be will when opening interruption
The standard cycle time counts in synchrotimer, and clock timer of having no progeny in opening resets, and otherwise judges
Cycle signal is fictitious time, and now the clock timer time must continue by upper plus T1=T0+Tk
Method of stating detects first cycle again.After first cycle signal of detection is very, recover with
Upper described cycle signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, open the break period all exists next time
After this opens the break period, when meansigma methods Tz of time delay cycle time, open interruption, and in opening
Have no progeny time delay Tns time close interrupt, arrange pass the break period be when cycle signal screen point 0 time
Do not produce interruption, at this moment must start to sweep more than the setting time point of Ts0 allowable error scope
Retouch, and when scanning is screened point 1 and screens point 2, voltage comparator output voltage does not produce
Saltus step, is all closing the interruption of break period Tns pass and is stopping scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks
Interrupt, and restart timing after clearing, close during timing to Tns and interrupt, so that synchrometer
Time the device time corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and this cycle judges
Time, discriminator signal is false, or the cycle time detected compares with meansigma methods Tz of cycle time
Exceed setting cycle time error Tzv, or clock timer timing is to closing break period setting value
During Tns, the voltage zero-cross detection module non-saltus step of V0 output voltage, do not produce interruption,
Then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and deposits
Storage, open the break period is to open the break period in last time to open interruption after Tz, the most next time
The secondary judgement cycle signal true and false, though if false or this detection discriminator signal is true last time is false,
Then taking N, will restore in memorizer after N+1, clock timer be had no progeny unclear zero continuation in opening
Timing, at this moment, next cycle of setting is opened the break period and is temporarily used out the break period instead and set temporarily
Definite value Tkz:
Tkz=(N+1) × Tz
Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, scanning is screened the time of point and can be obtained by simple computation
?.If at this moment detecting that cycle signal is true, then take out N in memorizer and preserve, and will deposit
N zero setting in reservoir, makes the clock timer clocking value Ts be: (Ts-Tkz) → Ts, at this moment takes
(N+1) value of × 20ms is added in synchrotimer, and recover use setting value Tks with
Tns, recovered clock timer is had no progeny clearing in opening.
The system synchronization time is the time of synchrotimer, adds current just at the clock meter of timing
Time device time.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by exporting with voltage comparator
Voltage jump time setting value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen
The point signal true and false, can select: Th0, Th1, Th2 are this cycle discriminator signal of true time and are
Very, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true
Time, this cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, owing to being
Main controller and each control for decocting medicinal herbs in system, the Tz value of its detection may be different with N value, at this moment,
Power network frequency cumulative error, being likely to result in the synchrotimer time cannot be true by detecting
Corrected during cycle signal, when detecting that cycle signal is true time, use clock timer to exist
Clocking value at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, and electricity
In the case of power net normal operation, N is much smaller than 25.
The cycle time error Tzv allowed and the flip-flop transition of voltage comparator output voltage set
Value, is taken its meansigma methods by test assessment and obtains.