CN105895580A - Manufacturing technology of semi-conductor packaging metal interconnection structure - Google Patents
Manufacturing technology of semi-conductor packaging metal interconnection structure Download PDFInfo
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- CN105895580A CN105895580A CN201610514383.3A CN201610514383A CN105895580A CN 105895580 A CN105895580 A CN 105895580A CN 201610514383 A CN201610514383 A CN 201610514383A CN 105895580 A CN105895580 A CN 105895580A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
- H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/8193—Reshaping
- H01L2224/81931—Reshaping by chemical means, e.g. etching
Abstract
The invention relates to a manufacturing technology of a semi-conductor packaging metal interconnection structure. The manufacturing technology is characterized by comprising the following steps: (1) manufacturing an adhesion layer, a seed layer and a photoresist on a substrate, and manufacturing an RDL (Redistribution Line)-layer electroplating window on the photoresist; (2) electroplating metal copper on the RDL-layer electroplating window; (3) removing the photoresist; (4) etching the adhesion layer and the seed layer; (5) etching the metal copper, thus ensuring consistent height of the metal copper. An etching mode of inverting the substrate is adopted when the metal copper is subjected to an etching technology, an etchant is enabled to be in contact with a bulge of highest metal copper first, gradual etching is carried out, needed heights of the metal copper are achieved, and the heights of the metal copper are enabled to be consistent. According to the manufacturing technology disclosed by the invention, the problem of inconsistent height of a metal layer is solved; compared with an existing technology, the manufacturing technology has better compatibility and is convenient and easy in implementation.
Description
Technical field
The present invention relates to the processing technology of a kind of semiconductor packages metal interconnection structure, a kind of wiring layer again and the electroplating manufacturing process of salient point.
Background technology
Due in the electroplating manufacturing process of semiconductor packages metal interconnection structure, concrete such as metallic copper (RDL) electroplating manufacturing process of wiring layer again and salient point (Bump) electroplating manufacturing process, (make or do not make the wafer of metallic circuit on material to be plated, substrate or glass) needed for the density of plating area or opening shape not of uniform size, cause the uniformity of metal height in the chip after plated metal or wafer poor, particularly in the region that areal concentration to be plated and opening size are the least, after its plating, the height of copper is the highest, overall uniformity is the poorest, and need the height of electro-coppering the highest, this difference is the most serious.The metal that highly heterogeneous phenomenon the is subsequent step interconnection related process of this electrodeposited coating brings bigger challenge；RDL layer height heterogeneity can cause such as metal level to be uneven, and stress is relatively big, and warpage seriously waits integrity problem, and particularly when the RDL layer making number of plies is more, this problem is the most serious；The metal layer height heterogeneity of salient point can cause metal to connect the serious integrity problems such as open circuit.
In copper RDL layer electroplating manufacturing process in semiconductor packages metal interconnection process, conventional RD L fabrication processing is as shown in Fig. 1-1～Fig. 1-5: (1) is as shown in Fig. 1-1, Fig. 1-2, substrate 104a makes adhesion layer 103a, Seed Layer 102a and photoresist 101a, photoresist 101a through gluing, exposed and developed formation RDL layer plating window 100a；(2) as Figure 1-3, window 100a plated metal copper 105a is electroplated at RDL layer；(3) as Figure 1-4, photoresist 101a is removed；(4) adhesion layer 103a and Seed Layer 102a as Figure 1-5, are etched away.Owing to the opening density of the RDL layer plating window 100a in A, B region to be plated is different, cause in electroplating process, the metal height of copper differs, that can plate in B region to be plated is more higher, after causing finally electroplating, the RDL layer height in whole region differs, uniformity be deteriorated, particularly when B region to be plated single RDL size compare at A less time, this phenomenon is even more serious.
In salient point electroplating manufacturing process in semiconductor packages metal interconnection process, tradition stud bump making technological process is as shown in Fig. 2-1～Fig. 2-5: (1) is as shown in Fig. 2-1, Fig. 2-2, substrate 104b makes adhesion layer 103b, Seed Layer 102b and photoresist 101b, photoresist 101b through gluing, exposed and developed formation salient point plating window 100b；(2) as Figure 2-3, window 100b plated metal copper 105b is electroplated at salient point；(3) as in Figure 2-4, plated metal nickel 106b on metallic copper 105b；(4) as shown in Figure 2-5, plated metal stannum silver 107b on metallic nickel 106b.Due to different in A, B region openings to be plated density, cause in electroplating process, the metal height of copper differs, that can plate in B region to be plated is more higher, and follow-up plated metal nickel and metallic tin silver can increase the weight of this phenomenon, causing final bump height to differ, uniformity is deteriorated, particularly when the single bump size in B region to be plated compare A region to be plated less time, this phenomenon is even more serious.
In prior art, the method improved for above-mentioned phenomenon is from electroplating technology itself, and such as regulation electric current density, the method such as additive formula to a certain degree improves this phenomenon.But this phenomenon is controlled root and is not effected a permanent cure, and improves DeGrain.When making RDL layer number and being more, due to synergistic effect, cause failure likelihood and risk the biggest, and this phenomenon the most not yet causes enough attention.When bump size is bigger, and when electroplating the highest (＞ 100 μm), this type of method still can not preferably solve.
Summary of the invention
The purpose of this part is summarize some aspects of embodiments of the invention and briefly introduce some preferred embodiments.Make a summary in this part and the description of the present application and denomination of invention may be done a little simplification or omit to avoid making the purpose of this part, specification digest and denomination of invention to obscure, and this simplification or omission cannot be used for limiting the scope of the present invention.
The problem differed in view of metal layer height present in RDL layer and salient point electroplating manufacturing process in above-mentioned and/or existing semiconductor packages metal interconnection process, it is proposed that the present invention.
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that the processing technology of a kind of semiconductor packages metal interconnection structure, solve the problem that metal layer height differs, and technique has preferable compatibility with existing technique, implements convenient and easy.
The technical scheme provided according to the present invention, the processing technology of described semiconductor packages metal interconnection structure, it is characterized in that, comprise the following steps:
(1) on substrate, make adhesion layer, Seed Layer and photoresist, make RDL layer plating window on a photoresist；
(2) window plated metal copper is electroplated at RDL layer；
(3) photoresist is removed；
(4) adhesion layer and Seed Layer are etched away；
(5) metallic copper is performed etching, make the highly consistent of metallic copper.
In a detailed description of the invention, described step (4) etches away Seed Layer and adhesion layer, then carries out after performing etching metallic copper.
In a detailed description of the invention, described metallic copper uses, when performing etching technique, the etching mode being inverted substrate, allows etching liquid first contact the bossing of the highest metallic copper, gradually etches, reach the height of required metallic copper, makes metallic copper highly consistent.
In a detailed description of the invention, described Seed Layer is copper seed layer, and adhesion layer is titanium layer.
The processing technology of described semiconductor packages metal interconnection structure, is characterized in that, comprise the following steps:
(1) on substrate, make adhesion layer, Seed Layer and photoresist, make salient point plating window on a photoresist；
(2) window plated metal copper is electroplated at salient point；
(3) photoresist is removed；
(4) metallic copper is performed etching, make the highly consistent of metallic copper；
(5) on metallic copper, metallic nickel and metallic tin silver are made again.
In a detailed description of the invention, described step (5) specifically uses following steps: coat photoresist at substrate surface, and photoresist covers Seed Layer and plated metal copper；Make window at photoresist and expose the upper surface of metallic copper；At metallic copper upper surface plated metal nickel；Plated metal stannum silver on metallic nickel.
The processing technology of semiconductor packages metal interconnection structure of the present invention, it is possible to solve the problem that metal layer height differs, and technique has preferable compatibility with existing technique, implements convenient and easy.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, in describing embodiment below, the required accompanying drawing used is briefly described, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.Wherein:
Fig. 1-1～Fig. 1-5 is copper RDL layer electroplating manufacturing process schematic diagram in prior art, wherein:
Fig. 1-1 is the schematic diagram making and obtaining RDL layer plating window.
Fig. 1-2 is the top view of Fig. 1-1.
Fig. 1-3 is the schematic diagram after plated metal copper.
Fig. 1-4 is the schematic diagram removing photoresist.
Fig. 1-5 is the schematic diagram etching away Seed Layer and adhesion layer.
Fig. 2-1～Fig. 2-5 is prior art bumps electroplating manufacturing process schematic diagram, wherein:
Fig. 2-1 is the schematic diagram making and obtaining salient point plating window.
Fig. 2-2 is the top view of Fig. 2-1.
Fig. 2-3 is the schematic diagram after plated metal copper.
Fig. 2-4 is the schematic diagram after plated metal nickel.
Fig. 2-5 is the schematic diagram of plated metal stannum silver.
Fig. 3-1～Fig. 3-5 is RDL layer electroplating manufacturing process schematic diagram in the embodiment of the present invention 1, wherein:
Fig. 3-1 is the schematic diagram making and obtaining RDL layer plating window.
Fig. 3-2 is the schematic diagram after plated metal copper.
Fig. 3-3 is the schematic diagram removing photoresist.
Fig. 3-4 is the schematic diagram etching away Seed Layer and adhesion layer.
Fig. 3-5 is that etching metallic copper makes the highly consistent schematic diagram of metallic copper.
Fig. 4-1～Fig. 4-8 is the embodiment of the present invention 3 bumps electroplating manufacturing process schematic diagram, wherein:
Fig. 4-1 is the schematic diagram making and obtaining salient point plating window.
Fig. 4-2 is the schematic diagram after plated metal copper.
Fig. 4-3 is the schematic diagram removing photoresist.
Fig. 4-4 is that etching metallic copper makes the highly consistent schematic diagram of metallic copper.
Fig. 4-5 is the schematic diagram of coating photoresist.
Fig. 4-6 exposes the schematic diagram of metallic copper upper surface for photoetching.
Fig. 4-7 is the schematic diagram after plated metal nickel.
Fig. 4-8 is the schematic diagram of plated metal stannum silver.
Detailed description of the invention
Understandable in order to enable the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with concrete accompanying drawing, the detailed description of the invention of the present invention is further described.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also use other to be different from alternate manner described here carrys out embodiment, those skilled in the art can do similar popularization in the case of intension of the present invention, and therefore the present invention is not limited by following public specific embodiment.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in implementing to make.
Embodiment 1: the processing technology of a kind of semiconductor packages metal interconnection structure, the present embodiment is the processing technology of RDL layer, comprises the following steps:
(1) as shown in figure 3-1, substrate 104-1 makes adhesion layer 103-1, Seed Layer 102-1 and photoresist 101-1, photoresist 101-1 through gluing, exposed and developed formation RDL layer plating window 100-1；The manufacture method of described adhesion layer 103-1, Seed Layer 102-1 and the manufacture method of photoresist 101-1 and RDL layer plating window 100-1 all uses existing common process；
(2) as shown in figure 3-2, window 100-1 plated metal copper 105-1 is electroplated at RDL layer；
(3) as shown in Fig. 3-3, photoresist 101-1 is removed；
(4) Seed Layer 102-1 and adhesion layer 103-1 as shown in Figure 3-4, are etched away；
(5) as in Figure 3-5, metallic copper 105-1 is performed etching, make that metallic copper 105-1's is highly consistent；The etching technics of described metallic copper 105-1 can use existing common process, preferably employ the etching mode being inverted substrate 104-1, allow etching liquid first contact the highest metallic copper 105-1 bossing with this, gradually etch, reach the height of required metallic copper 105-1.
Embodiment 2: the processing technology of a kind of semiconductor packages metal interconnection structure, the present embodiment is the processing technology of RDL layer, comprises the following steps:
Step (1)～step (3) are with embodiment 1；
(4) metallic copper 105-1 is performed etching, make that metallic copper 105-1's is highly consistent；
(5) Seed Layer 102-1 and adhesion layer 103-1 are etched away.
RDL layer processing technology disclosed in embodiment 1 and embodiment 2, after removing photoresist process, add the etching of a metallic copper, remove the height of a part of electro-coppering, metallic copper in plating is reached unanimity at electroplated regional height, so whole RDL layer height has a good uniformity after electricity Du, and when making multilamellar RDL layers of copper, also eliminate and above-mentioned differ the inefficacy hidden danger brought due to layers of copper height.The processing step of described etching metallic copper does not completes to carry out when photoresist there is also at plated metal copper, it is because now also having photoresist to exist, still suffer from non-calking district above copper RDL layer, now perform etching, etching defect can be caused owing to greatly there may be gas in etching process void district.
Embodiment 3: the processing technology of a kind of semiconductor packages metal interconnection structure, the present embodiment is the processing technology of salient point, comprises the following steps:
(1) as shown in Fig. 4-1, substrate 104-2 makes adhesion layer 103-2, Seed Layer 102-2 and photoresist 101-2, photoresist 101-2 through gluing, exposed and developed formation salient point plating window 100-2；The manufacture method of described adhesion layer 103-2, Seed Layer 102-2 and the manufacture method of photoresist 101-2 and salient point plating window 100-2 all uses existing common process；
(2) as shown in the Fig. 4-2, window 100-2 plated metal copper 105-2 is electroplated at salient point；
(3) as shown in Fig. 4-3, photoresist 101-2 is removed；
(4) as shown in Fig. 4-4, metallic copper 105-2 is performed etching, make that metallic copper 105-2's is highly consistent；The etching technics of described metallic copper 105-2 can use existing common process, preferably employ the etching mode being inverted substrate 104-2, allow etching liquid first contact the highest metallic copper 105-2 bossing with this, gradually etch, reach the height of required metallic copper 105-2；
(5) as illustrated in figures 4-5, Seed Layer 102-2 and metallic copper 105-2 are covered at substrate 104-2 surface-coated photoresist 101-3, photoresist 101-3；
(6) as Figure 4-Figure 6, photoresist 101-3 carries out gluing, the exposed and developed upper surface exposing metallic copper 105-2；
(7) as shown in figs. 4-7, at metallic copper 105-2 upper surface plated metal nickel 106-2；
(8) as Figure 4-8, plated metal stannum silver 107-2 on metallic nickel 106-2.
Stud bump making technique disclosed in embodiment 3, after step (2) plated metal copper completes, increase by a step etching technics, remove the height of a part of metallic copper so that the metallic copper in plating reaches unanimity at electroplated regional height, carry out plated metal nickel and the technique of metallic tin silver the most again.Due to before plated metal nickel and metallic tin silver, eliminate the differ solution plating metal ion that brings of metallic copper height and spread the range deviation brought, and the height of metallic copper compare metallic nickel and metallic tin silver height much higher, in plated metal nickel and metallic tin silver process, it reduces, so whole bump height has preferable uniformity after electricity Du largely owing to plating difference in height that above-mentioned phenomenon is brought also has.Embodiment 3 etches the processing step of metallic copper and does not completes to carry out when photoresist there is also at plated metal copper, it is because now also having photoresist to exist, salient point hole still suffers from, and now performs etching, and can cause etching defect owing to there may be gas in etching process Hole.
It should be noted that, above example is only in order to illustrate technical scheme and unrestricted, although the present invention being described in detail with reference to preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent, without deviating from the spirit and scope of technical solution of the present invention, it all should be contained in the middle of scope of the presently claimed invention.
Claims (6)
1. a processing technology for semiconductor packages metal interconnection structure, is characterized in that, comprises the following steps:
(1) on substrate, make adhesion layer, Seed Layer and photoresist, make RDL layer plating window on a photoresist；
(2) window plated metal copper is electroplated at RDL layer；
(3) photoresist is removed；
(4) adhesion layer and Seed Layer are etched away；
(5) metallic copper is performed etching, make the highly consistent of metallic copper.
2. the processing technology of semiconductor packages metal interconnection structure as claimed in claim 1, is characterized in that: described step (4) etches away Seed Layer and adhesion layer, then carries out after performing etching metallic copper.
3. the processing technology of semiconductor packages metal interconnection structure as claimed in claim 1, it is characterized in that: described metallic copper uses, when performing etching technique, the etching mode being inverted substrate, etching liquid is allowed first to contact the bossing of the highest metallic copper, gradually etch, reach the height of required metallic copper, make metallic copper highly consistent.
4. the processing technology of semiconductor packages metal interconnection structure as claimed in claim 1, is characterized in that: described Seed Layer is copper seed layer, and adhesion layer is titanium layer.
5. a processing technology for semiconductor packages metal interconnection structure, is characterized in that, comprises the following steps:
(1) on substrate, make adhesion layer, Seed Layer and photoresist, make salient point plating window on a photoresist；
(2) window plated metal copper is electroplated at salient point；
(3) photoresist is removed；
(4) metallic copper is performed etching, make the highly consistent of metallic copper；
(5) on metallic copper, metallic nickel and metallic tin silver are made again.
6. the processing technology of semiconductor packages metal interconnection structure as claimed in claim 5, is characterized in that: described step (5) specifically uses following steps: coat photoresist at substrate surface, and photoresist covers Seed Layer and plated metal copper；Make window at photoresist and expose the upper surface of metallic copper；At metallic copper upper surface plated metal nickel；Plated metal stannum silver on metallic nickel.
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| CN107658261A (en) * | 2017-08-23 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of chip back-end metal making technology |
| CN110476259A (en) * | 2017-03-24 | 2019-11-19 | 欧司朗光电半导体有限公司 | For manufacturing the method and opto-electronic device of opto-electronic device |
| CN111115556A (en) * | 2019-12-30 | 2020-05-08 | 青岛歌尔智能传感器有限公司 | Packaging method and packaging structure of micro-electro-mechanical system sensor |
| CN112420523A (en) * | 2020-10-21 | 2021-02-26 | 中国科学院微电子研究所 | Manufacturing method of copper rewiring layer, silicon optical device and chip |
| CN115831766A (en) * | 2023-01-10 | 2023-03-21 | 日月新半导体(昆山)有限公司 | Integrated circuit process and integrated circuit product |
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| CN112420523A (en) * | 2020-10-21 | 2021-02-26 | 中国科学院微电子研究所 | Manufacturing method of copper rewiring layer, silicon optical device and chip |
| CN115831766A (en) * | 2023-01-10 | 2023-03-21 | 日月新半导体(昆山)有限公司 | Integrated circuit process and integrated circuit product |
| CN115831766B (en) * | 2023-01-10 | 2023-05-02 | 日月新半导体(昆山)有限公司 | Integrated circuit process and integrated circuit product |
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