CN105870124A - Display device - Google Patents
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- CN105870124A CN105870124A CN201510029484.7A CN201510029484A CN105870124A CN 105870124 A CN105870124 A CN 105870124A CN 201510029484 A CN201510029484 A CN 201510029484A CN 105870124 A CN105870124 A CN 105870124A
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Abstract
The invention discloses a display device, which comprises an array substrate defining multiple pixel structures arranged in an array. Each pixel structure comprises a semiconductor layer, a first metal layer, a first insulated layer, a second metal layer and a second insulated layer, wherein the semiconductor layer is located on the substrate; the first metal layer is located on the substrate; the first insulated layer is located on the semiconductor layer, the first insulated layer is provided with a first opening, and a top surface of the semiconductor layer and a side surface of the first insulated layer are exposed from the first opening; the second metal layer is located on the first insulated layer and formed on the top surface of the semiconductor layer and the side surface of the first insulated layer via the first opening; and the second insulated layer is located on the second metal layer and the first insulated layer, the second insulated layer is provided with a second opening, and the second metal layer located on the side surface of the first insulated layer is exposed from the second opening.
Description
Technical field
The present invention relates to display device, and particularly relate to utilize the display device of thin film transistor (TFT).
Background technology
Process and high-quality show image to realize high-speed image, fill such as Color Liquid Crystal Display in recent years
The flat-panel screens put is widely used.In liquid crystal indicator, generally include two upper and lower bases
Plate, is bonded together to bind or to seal material.And liquid crystal material is received between two substrates, for
Keeping distance fixing between two plates, the granule with certain particle diameter is interspersed between above-mentioned two plates.
Generally, lower substrate surface is formed for the thin film transistor (TFT) as switch element, this film crystal
Pipe has and is connected to the gate electrode (gate electrode) of scan line (scanning line), is connected to data wire
The source electrode (source electrode) of (data line) and be connected to pixel electrode (pixel electrode)
Drain electrode (drain electrode).And upper substrate is placed in above infrabasal plate, this upper substrate surface is formed
One optical filter and multiple light screening materials (as being made up of resin black matrix (Resin BM)).The week of this two substrates
Fix while have sealing material bonding, and there is between two substrates liquid crystal material.Infrabasal plate is also referred to as
Array base palte (array substrate), and units as several in thin film transistor (TFT), contactant etc. formed thereon
Part is generally the most made by several lithographic fabrication process.
But, along with the lifting trend of the image resolution of display device, just need to be formed on infrabasal plate
During the several element more reduced such as thin film transistor (TFT), contactant equidimension, it is provided that can maintain or more carry
Rise the array base palte of the aperture opening ratio performance of display device.
Summary of the invention
According to an embodiment, the invention provides a kind of display device, comprise: array basal plate, definition
Go out the dot structure of multiple array arrangement.Those dot structures are respectively provided with: semi-conductor layer, are positioned at one
On substrate；One the first metal layer, is positioned on this substrate；One first insulating barrier, is positioned on this semiconductor layer,
This first insulating barrier has one first opening, this first opening expose an end face of this semiconductor layer and this
The one side of one insulating barrier；One second metal level, is positioned on this first insulating barrier, and first opens via this
This end face in this semiconductor layer of interruption-forming and this side of this first insulating barrier；And one second insulation
Layer, is positioned on this second metal level and this first insulating barrier, and this second insulating barrier has one second opening,
Wherein, this second opening exposes this second metal level on this side being positioned at this first insulating barrier, wherein,
This first opening, this second opening and this first metal layer putting in order as this first metal along a direction
Layer, this second opening, and this first opening.
According to another embodiment, above-mentioned display device, also include: a transparent substrates；And a display layer,
It is arranged between this transparent substrates and this array base palte.
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, cited below particularly one is the most real
Execute example, and the accompanying drawing appended by cooperation, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the upper schematic diagram of the layout situation of a kind of array base palte of one embodiment of the invention；
Fig. 2 is the section of the array base palte of 2-2 line segment along Fig. 1 of one embodiment of the invention
Schematic diagram；
Fig. 3 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present invention；
Fig. 4 is the schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present invention；
Fig. 5 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present invention；
Fig. 6 is the section of the array base palte of 6-6 line segment along Fig. 5 of one embodiment of the invention
Schematic diagram；
Fig. 7 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present invention；
Fig. 8 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present invention；
And
Fig. 9 is the generalized section of a kind of display device of one embodiment of the invention.
Symbol description
10,10 '～array base palte
100～substrate
102～semiconductor layer
102a～drain region
104～insulating barrier
106～metal level
108～insulating barrier
110～first opening
112～metal level
112 '～metal level
116～insulating barrier
118～second opening
120～transparency electrode
300～array base palte
350～display layer
400～transparent substrates
500～display device
A～geometric center
B～geometric center
P～pixel region
α～angle
Detailed description of the invention
Refer to Fig. 1-Fig. 2, it is shown that a kind of array base palte 10 of foundation one embodiment of the invention
A series of schematic diagrams, it is applicable to the application of the display device such as color liquid crystal display arrangement.Here, figure
1 is a upper schematic diagram, and Fig. 2 is then a generalized section, with display 2-2 line segment along Fig. 1
The section of of array base palte.
Refer to Fig. 1, array base palte 10 specifically includes that a substrate 100 (does not shows at this, refers to
Fig. 2), the semiconductor layer 102 of several U-shaped, be arranged at separatedly on one of substrate 100；Several gold
Belonging to layer 106, a first direction edge of edge such as X-direction is stretched and is positioned apart from of substrate 100,
And cover one of these a little semiconductor layers 104 respectively；One insulating barrier 108 (does not shows at this, refers to figure
2), it is formed on substrate 100, semiconductor layer 102, these a little the first metal layers 106；Several metal levels
112, a second direction edge of edge such as Y-direction is stretched and is positioned apart from insulating barrier 108 and partly covers
Cover one of one of these a little semiconductor layers 102；Several metal levels 112 ', are respectively arranged at two adjacent gold medals
Belong to and cover the another of one of these a little semiconductor layers 102 with part on of the insulating barrier 108 between layer 112
One；Several first openings 110, within being arranged at insulating barrier 108 separatedly, a little to expose this respectively
The end face (not showing at this, refer to Fig. 2) in several portions of semiconductor layer 102, and metal level 112 and gold
One that belongs to layer 112 ' is then respectively filled within one of these a little first openings 110, to be formed and quasiconductor
Electrical connection relation between layer 102；One insulating barrier 116 (not showing at this, refer to Fig. 2), smooth covers
Be formed at substrate 100, these a little metal levels 112 ', these a little metal levels 112 with on insulating barrier 108；Number
Individual second opening 118, is arranged in one of insulating barrier 116 separatedly, to expose this little metals respectively
One of the end face of of one of layer 112 ' and these a little first openings 110 partially overlapping lower section；Several
Transparency electrode 120, is arranged at intervals at and is positioned at this bit by two adjacent and staggered metal level 106 and two metals
Layer 112 is intersected on the insulating barrier 116 in the several pixel region P defined, and transparency conducting layer 120
One then fill in one of these a little second openings 118 in, with contact metal layer 112 '.In these a little pixels
Within district P, then it is respectively formed with a dot structure.
As it is shown in figure 1, along the first direction such as X-direction along stretching and these a little metal levels spaced
106 are used respectively as a gate line (gate line), and along as Y-direction one second direction edge stretch and
Then it is used respectively as a data wire (data line) every these a little metal wires 112 arranged, and this little first opens
Mouth 110 is used as the first contact hole (contact hole), and these a little second openings 118 connect as second
Contact hole is used.Here, the metal level 112 ' being formed in the first opening 110 for electrical connection one thin film
One drain region of transistor unit is used with the pixel electrode being subsequently formed, and the second opening 118 and
A part for one opening 110 is overlapping, thus exposes of metal level 112 ', and is formed at second and opens
Transparency electrode 120 in mouthfuls 118 partially overlaps metal level 112 and contacts it, and then defines and be electrically connected
Connect situation.
Refer to the schematic diagram of Fig. 2, to show the 2-2 along Fig. 1 according to one embodiment of the invention
The section of the array base palte 10 of line segment.
As in figure 2 it is shown, be additionally provided with another insulating barrier between semiconductor layer 102 and insulating barrier 108
104, to be used as the gate insulation layer (gate insulator) in a thin film transistor (TFT).At semiconductor layer 102
Within be then formed with a drain region 102a, the first opening 110 then breaks through this insulating barrier 104 and part
Expose the end face of this drain region 102a, metal level 112 ' is the most conformably formed at insulating barrier 108
Surface on and fill in the first opening 110, it covers via the first opening 110 and contact is
Drain electrode in the side wall surface of the insulating barrier 102 and 104 that one opening 110 is exposed and semiconductor layer 102
The end face of district 102a.
Furthermore, the second opening 118 being formed in insulating barrier 116 then partially overlaps in pixel region P
First opening 110, and then expose the metal being formed on insulating barrier 108 and in this first opening 110
Layer one of 112 ', transparency electrode 120 then in addition on the end face being formed at insulating barrier 116, its
The metal level 112 ' exposed by the second opening 118 is contacted within being also formed in the second opening 118
Part.It should be noted that the area of the metal level 112 ' exposed by the second opening 118 is more than being
The area of the end face of the semiconductor layer 102 that the first opening 110 is exposed.In other words, the second opening 118
Size more than the size of the first opening 110.
Situation as Figure 1-Figure 2, by being formed at the first opening 110 and metal by the second opening 118
A position between line 106, the most just can increase the area of coverage of transparency electrode 120 in pixel region P
Territory, and then increase the effective vent rate of pixel region P.
Continuing referring to Fig. 1-Fig. 2, the first opening 110 in pixel region P with the second opening 118 is
There is the one of decreasing dimensions from top to bottom and pull out taper (tapered shape) opening.And based on simplifying diagram mesh
, in Fig. 1, only show this little first opening 110 and full-sizes of the second opening 118, and
These a little first openings 110 and the second opening 118 are respectively provided with geometric center A and B.
As it is shown in figure 1, from upper that regard sight, the geometric center of this first opening 110 in pixel region P
A line A-B between geometric center B of A the second opening 118 adjacent thereto and metal wire 106
Between can have the angle α of substantially 90 degree, and this line A-B is perpendicular to metal wire 106.But,
In order to more increase the overlay area of the transparency electrode 120 in pixel region P and increase the effective of pixel region P
Aperture opening ratio, the then position of adjustable the second opening 118 so that its be closer to left metal wire 112 (as
Shown in Fig. 3) or the metal wire 112 (as shown in Figure 4) of right, and then make the geometry of the first opening 110
A line A-B between geometric center B of center A the second opening 118 adjacent thereto is the most vertical
In metal wire 106, and the angle [alpha] of an on-right angle will be accompanied between this line A-B and metal wire 106.
The visual actual demand of this angle [alpha] and more than 0 degree and be less than 90 degree.
Refer to Fig. 5-Fig. 6, it is shown that according to a kind of array base palte 10 ' of another embodiment of the present invention
A series of schematic diagrams.Fig. 5 is a upper schematic diagram, and Fig. 6 is then a generalized section, with display
The section of one of the array base palte of 6-6 line segment along Fig. 5.Here, the embodiment of Fig. 5-Fig. 6
Obtained by the embodiment shown in amendment Fig. 1-Fig. 2, therefore in Fig. 5-Fig. 6, similar elements uses identical mark
Shown by number, and the most only explain orally at the difference between itself and Fig. 1-embodiment illustrated in fig. 2.
Refer to Fig. 5, can more adjust and to be positioned at the metal level 112 ' of pixel region P, semiconductor layer 102
Part with and the relevant position of neighbouring associated components so that metal level 112 ' and the second opening 118
Divide and be overlapped in metal wire 106.Therefore, in transparency electrode 120 only partially fills in the second opening 118
And only part covers the end face of insulating barrier 116 and the portion of insulating barrier 118 exposed by the second opening 118
Divide side wall surface and the end face of metal level 112 ' and side wall surface.
Refer to Fig. 6, then show the section of of the array base palte of 6-6 line segment along Fig. 5,
In this transparency electrode 120 only partially fills in the second opening 118 and only part covers insulating barrier 116
End face and the partial sidewall face of insulating barrier 118 exposed by the second opening 118 and metal level 112 '
End face and side wall surface, metal level 112 ' above then partially overlap be positioned at lower section metal level
106。
Continue referring to Fig. 5-Fig. 6, the first opening 110 in pixel region P and across pixel region P
It is to there is the one of decreasing dimensions from top to bottom pull out taper (tapered with the second opening 118 of metal wire 106
Shape) opening.And based on simplifying diagram purpose, only show in Fig. 5 these a little first openings 110 with
One full-size of the second opening 118, and these a little first openings 110 are respectively provided with the second opening 118
One geometric center A and B.
As it is shown in figure 5, regard sight from upper, geometric center A of this first opening 110 adjacent thereto the
Can have substantially between a line A-B and metal wire 106 between geometric center B of two openings 118
One angle α of 90 degree, and this line A-B is perpendicular to metal wire 106.But, in order to more increase pixel
The overlay area of the transparency electrode 120 in district P and increase the effective vent rate of pixel region P, the most adjustable
The position of whole second opening 118 so that its be closer to left metal wire 112 (as shown in Figure 7) or
The metal wire 112 (as shown in Figure 8) of right, so make geometric center A of the first opening 110 and its
A line A-B between geometric center B of the second neighbouring opening 118 is no longer normal to metal wire 106,
And the angle [alpha] of an on-right angle will be accompanied between this line A-B and metal wire 106.This angle [alpha] is visually real
Border demand and more than 0 degree and be less than 90 degree.
Similar in appearance to the enforcement situation shown in Fig. 1-Fig. 4, the array base in the enforcement situation shown in Fig. 5-Fig. 8
It is formed between the first opening 110 and metal wire 106 also by by the second opening 118 in plate 10 '
Position, to increase the overlay area of the transparency electrode 120 in pixel region P, and increases pixel region P
Effective vent rate.
In the embodiment shown in Fig. 1-Fig. 4 and Fig. 5-Fig. 8, the material of substrate 100 for example, glass or
Plastic cement, the material of semiconductor layer 102 for example, polysilicon, the material of insulating barrier 104 and 108 is for example,
Identical or not phase can be included between silicon oxide, silicon nitride or a combination thereof, and different insulative layer 104 and 108
Same material, the material of metal level 106 for example, tungsten or aluminum, insulating barrier 116 then includes such as spin-coating glass
Or isolation material, the material for example, tungsten of metal level 112 and metal level 112 ' or aluminum and can concurrently form,
And transparency electrode 120 can include the transparent conductive material of tin indium oxide (ITO).And semiconductor layer 102
External form is the most non-to be limited with U-shaped, and it is alternatively L-shaped or other shapes.The making of above-mentioned component can use
Traditional array substrate manufacture technique is completed, therefore will herein be described in detail its relative production.
Refer to Fig. 9, it is shown that the one of a kind of display device 500 of foundation one embodiment of the invention cuts open
Face schematic diagram.
As it is shown in figure 9, display device 500 includes: array basal plate 300；One transparent substrates 350；With
And a display layer 400, it is arranged between transparent substrates 350 and this array base palte 300.In an embodiment
In, the array base palte 300 in display device 500 can include array base palte 10 as Figure 1-Figure 8
With 10 ', and can also include such as other components such as common electrode (not shown)s.And according to the reality of display device 500
Executing situation, for example, liquid crystal indicator or organic LED display device, display layer 400 then wraps
Include a liquid crystal layer or an Organic Light Emitting Diode layer.And in display device 500, according to display device 500
Enforcement situation, for example, liquid crystal indicator or organic LED display device, transparent substrates 350
On can also include other components just like colorized optical filtering thing (not shown), and transparent substrates 350 can include as
Glass or the light-transmitting materials of plastic cement.
Although disclosing the present invention in conjunction with preferred embodiment above, but it being not limited to the present invention,
Any those skilled in the art, without departing from the spirit and scope of the present invention, can change and retouching,
Therefore protection scope of the present invention should be with being as the criterion that the claim enclosed is defined.
Claims (10)
1. a display device, comprises:
Array base palte, defines the dot structure of multiple array arrangement, and those dot structures are respectively provided with:
Semiconductor layer, is positioned on a substrate；
The first metal layer, is positioned on this substrate；
First insulating barrier, is positioned on this semiconductor layer, and this first insulating barrier has one first opening,
This first opening exposes an end face and the one side of this first insulating barrier of this semiconductor layer；
Second metal level, is positioned on this first insulating barrier, and is formed at this partly via this first opening
This end face of conductor layer and this side of this first insulating barrier；And
Second insulating barrier, is positioned on this second metal level and this first insulating barrier, and this second insulation
Layer has one second opening, and wherein, this second opening exposes on this side being positioned at this first insulating barrier
This second metal level,
Wherein, this first opening, this second opening are suitable along the arrangement in a direction with this first metal layer
Sequence is this first metal layer, this second opening, and this first opening.
2. display device as claimed in claim 1, this second metal that wherein this second opening is exposed
The area of this end face of this semiconductor layer that the area of layer is exposed more than this first opening.
3. display device as claimed in claim 1, wherein this second metal level and this first metal layer portion
Divide overlap.
4. display device as claimed in claim 1, between wherein this first metal layer includes in the first direction
Every the first grid polar curve arranged and a second gate line, and this second metal level includes along a second direction
Spaced one first data wire and one second data wire, this first direction is different from this second direction,
This first grid polar curve, this second gate line, this first data wire and this second data line definition one pixel region,
This first opening and this second opening are positioned at this pixel region, and this semiconductor layer is electric with this first data wire
Connect.
5. display device as claimed in claim 4, wherein, this second opening be positioned at this first opening with
Between this first data wire.
6. display device as claimed in claim 4, wherein, this second opening portion be overlapped in this first
Metal level.
7. display device as claimed in claim 4, during wherein this first opening has one first geometry
The heart, and this second opening has one second geometric center, wherein this first geometric center and this second geometry
One line at center and this first grid polar curve have an angle, and this angle is more than 0 degree and less than 90 degree.
8. display device as claimed in claim 1, also includes:
Transparent substrates；And
Display layer, is arranged between this transparent substrates and this array base palte.
9. display device as claimed in claim 1, also comprises the first transparency electrode, this first transparent electrical
Pole is electrically connected with this second metal level by this second opening.
10. display device as claimed in claim 9, wherein this display layer is a liquid crystal layer or organic
LED layers.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910396959.4A CN110112145B (en) | 2015-01-21 | 2015-01-21 | display device |
| CN201510029484.7A CN105870124B (en) | 2015-01-21 | 2015-01-21 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510029484.7A CN105870124B (en) | 2015-01-21 | 2015-01-21 | Display device |
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| CN201910396959.4A Division CN110112145B (en) | 2015-01-21 | 2015-01-21 | display device |
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| CN105870124A true CN105870124A (en) | 2016-08-17 |
| CN105870124B CN105870124B (en) | 2019-06-07 |
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| CN201910396959.4A Active CN110112145B (en) | 2015-01-21 | 2015-01-21 | display device |
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| CN204596791U (en) * | 2015-01-21 | 2015-08-26 | 群创光电股份有限公司 | Display unit |
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| KR101026797B1 (en) * | 2003-08-11 | 2011-04-04 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
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| TWI261716B (en) * | 2004-05-13 | 2006-09-11 | Quanta Display Inc | Liquid crystal display apparatus and fabrication thereof |
| CN100381924C (en) * | 2005-01-31 | 2008-04-16 | 友达光电股份有限公司 | Liquid crystal display device and manufacturing method thereof |
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| CN102645808A (en) * | 2012-04-20 | 2012-08-22 | 京东方科技集团股份有限公司 | Manufacture method of array substrate, array substrate and display device |
| WO2014054500A1 (en) * | 2012-10-03 | 2014-04-10 | シャープ株式会社 | Liquid crystal display device |
| KR102015873B1 (en) * | 2013-01-03 | 2019-10-22 | 삼성디스플레이 주식회사 | Back plane of display and manufacturing method for the same |
| TWI520399B (en) * | 2013-05-31 | 2016-02-01 | 群創光電股份有限公司 | Organic light-emitting device and method for fabricating the same, and image display system employing the same |
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| CN1314608A (en) * | 2000-03-17 | 2001-09-26 | 精工爱普生株式会社 | Electrooptics device |
| US20050142676A1 (en) * | 2003-12-29 | 2005-06-30 | Lg.Philips Lcd Co., Ltd. | Method for fabricating polysilicon liquid crystal display device |
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| CN204596791U (en) * | 2015-01-21 | 2015-08-26 | 群创光电股份有限公司 | Display unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110112145A (en) | 2019-08-09 |
| CN105870124B (en) | 2019-06-07 |
| CN110112145B (en) | 2023-08-29 |
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