CN201893340U - Display panel - Google Patents
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- CN201893340U CN201893340U CN2010205166918U CN201020516691U CN201893340U CN 201893340 U CN201893340 U CN 201893340U CN 2010205166918 U CN2010205166918 U CN 2010205166918U CN 201020516691 U CN201020516691 U CN 201020516691U CN 201893340 U CN201893340 U CN 201893340U
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- gate
- display floater
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- picture element
- film transistor
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Abstract
A display panel of the utility model comprises a substrate and a plurality of pixel units. Each pixel unit comprises a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first gate electrode electrically connected with a first gate electrode wire, a first source electrode electrically connected with a data line and a first drain electrode electrically connected with a first pixel electrode; similarly, the second thin film transistor comprises a second gate electrode electrically connected with a second gate electrode wire, a second source electrode electrically connected with a data line and a second drain electrode electrically connected with a second pixel electrode; the first drain electrode extends towards the first gate electrode along the first direction so as to be overlapped on the first gate electrode; and the second drain electrode extends towards the second gate electrode along the first direction so as to be overlapped on the second gate electrode.
Description
Technical field
The utility model is about a kind of display floater, refers to a kind of display floater that reduces the difference between the adjacent picture element feedback voltage (feed through voltage) especially.
Background technology
Display floater mainly can be divided into single gate (single gate) display floater and the double-gate utmost point (dual gate) display floater according to the difference of drive pattern.Under identical resolution, compared to single gate display floater, the gate line number of double-gate utmost point display floater increases to twice, and the data wire number then is reduced to 1/2nd, so double-gate utmost point display floater uses more gate drive chip and less source driving chip.Because the cost and the power consumption of gate drive chip are all low than source driving chip, so double-gate utmost point display floater can have lower cost and power consumption.
Please refer to Figure 1A, Figure 1A has shown a kind of schematic diagram of double-gate utmost point display floater in the known technology.Shown in Figure 1A, a data wire S1, one first gate line G1, one second gate line G2 are arranged on the substrate 100.Be provided with a first film transistor T 1 in the left side of data wire S1, and be provided with one second thin-film transistor T2 on the right side of data wire S1, wherein the first film transistor T 1 and the second thin-film transistor T2 share same data wire S1.Moreover the first film transistor T 1 has electric capacity between identical lock/drain with the second thin-film transistor T2.More particularly, first gate 11 of the first film transistor T 1 and the overlapping area between first drain 13 are same as second gate 21 of the second thin-film transistor T2 and the overlapping area between second drain 23.Shown in Figure 1A, the width of each overlapping area is a, and length is b.
Yet if the interlayer alignment that causes because of manufacturing process is offset, the first film transistor T 1 will have electric capacity between different lock/drains with the second thin-film transistor T2.Please refer to Figure 1B, Figure 1B has shown the schematic diagram of the double-gate utmost point display floater of tool Y direction interlayer alignment skew in the known technology.Shown in Figure 1B, because first drain 13 of the first film transistor T 1 is the tops that extended to first gate 11 and second gate 21 by different directions respectively with second drain 23 of the second thin-film transistor T2, therefore when the formation gate produced the relative displacement of Y direction with the different retes of drain in manufacturing process, first gate 11 of the first film transistor T 1 and the overlapping area between first drain 13 can be greater than second gate 21 of the second thin-film transistor T2 and the overlapping areas between second drain 23.More particularly, first gate 11 of the first film transistor T 1 and the overlapping area width between first drain 13 are a, and length is b+u; Second gate 21 of the second thin-film transistor T2 and the overlapping area width between second drain 23 are a, and length is b-u.In view of the above, because the difference between the electric capacity between lock/drain of the electric capacity and the second thin-film transistor T2 between the lock/drain of the first film transistor T 1, the feedback voltage of two adjacent picture elements of its correspondence is different with making, and then causes film flicker (flicker) problem of display floater.
Summary of the invention
One of the purpose of this utility model is to provide a kind of display floater, to solve the film flicker problem that known technology was faced.
A preferred embodiment of the present utility model provides a kind of display floater, and it comprises a substrate and a plurality of picture elements unit that is arranged on the substrate.Each picture element unit comprises one first gate line, one second gate line, a data wire, one first picture element and one second picture element.Wherein, first picture element is to be arranged at a side of data wire and between first gate line and second gate line, and first picture element comprises one first pixel electrode and a first film transistor.The first film transistor comprises one first gate that is electrically connected to first gate line, one first drain that is electrically connected to one first source electrode of data wire and is electrically connected to first pixel electrode.In addition, second picture element is to be arranged at the opposite side of data wire and between first gate line and second gate line, and second picture element comprises one second pixel electrode and one second thin-film transistor.Same, second thin-film transistor comprises one second gate, one second source electrode that is electrically connected to data wire that is electrically connected to second gate line, one second drain that is electrically connected to second pixel electrode.Wherein, first drain extends along a first direction towards first gate being overlapped on first gate, and second drain extends to be overlapped on second gate along first direction towards second gate.
In each picture element unit of display floater of the present utility model, the bearing of trend that first drain is overlapped in first gate is same as the bearing of trend that second drain is overlapped in second gate.In view of the above, even if the interlayer alignment that causes because of manufacturing process is offset, the overlapping area between transistorized first gate of the first film and first drain can be same as second gate of second thin-film transistor and the overlapping area between second drain.Therefore, the feedback voltage of two adjacent picture elements can be kept unanimity, and then reduces the film flicker problem of display floater.
Description of drawings
Figure 1A has shown a kind of schematic diagram of double-gate utmost point display floater in the known technology.
Figure 1B has shown the schematic diagram of the double-gate utmost point display floater of tool Y direction interlayer alignment skew in the known technology.
Fig. 2 is the schematic diagram that shows the display floater of the utility model first preferred embodiment.
Fig. 3 A is the transistorized schematic diagram of the first film that shows the utility model first preferred embodiment.
Fig. 3 B shows the transistorized embodiment one of the first film of the present utility model.
Fig. 4 shows the transistorized embodiment two of the first film of the present utility model.
Fig. 5 shows the transistorized embodiment three of the first film of the present utility model.
Fig. 6 is the schematic diagram that shows the black matrix" of the corresponding picture element unit of the utility model.
Fig. 7 is the schematic diagram that shows the display floater of the utility model second preferred embodiment.
Wherein: 100,200-substrate; G1-first gate line; G2-second gate line; The S1-data wire; P1-first pixel electrode;
P2-second pixel electrode; T1-the first film transistor; T2-second thin-film transistor; The D1-first direction; The D2-bearing of trend;
11-first gate; 12-first source electrode; 13-first drain; 21-second gate; 22-second source electrode; 23-second drain;
30-photoresistance separation material; The 40-channel region; The 50-black matrix"; The 51-transparent area; The A-angle; 121,122-elongated end;
X, Y-direction; A, b, u-length.
Embodiment
In the middle of specification and follow-up claim, used some vocabulary to censure specific assembly.The person with usual knowledge in their respective areas should understand, and the producer may call same assembly with different nouns.This specification and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be to be an open term mentioned " comprising " in the middle of specification and the follow-up claim in the whole text, so should be construed to " including but not limited to ".In addition, " electric connection " speech is to comprise any indirect electric connection means that directly reach at this.Therefore, one first device is electrically connected at one second device described in the literary composition, then represents this first device can be directly connected in this second device, and perhaps this first device can be connected to this second device indirectly via seeing through other device or connection means.Be noted that graphic only for the purpose of description, do not map according to life size.
Please refer to Fig. 2, Fig. 2 is the schematic diagram that shows the display floater of the utility model first preferred embodiment.Be clear expression and simplified illustration, Fig. 2 is display part assembly and do not show all component only.As shown in Figure 2, display floater of the present utility model comprises a substrate 200 and a plurality of picture elements unit that is arranged on the substrate 200.Wherein, Fig. 2 has shown 4 picture element unit, and the picture element unit of first preferred embodiment is to arrange with matrix-style.Each picture element unit comprises one first gate line G1, one second gate line G2, a data wire S1, one first picture element and one second picture element.Wherein, first picture element is the side (for example left side of Fig. 2) that is arranged at data wire S1 and between the first gate line G1 and the second gate line G2, and first picture element comprises one first a pixel electrode P1 and a first film transistor T 1.The first film transistor T 1 comprises one first gate 11 that is electrically connected to the first gate line G1, one first drain 13 that is electrically connected to one first source electrode 12 of data wire S1 and is electrically connected to the first pixel electrode P1.Wherein, the first film transistor T 1 also comprises semi-conductor layer (figure do not show), is arranged between first source electrode 12, first drain 13 both and first gate 11.More particularly, first source electrode 12 and first drain 13 can be made of same layer pattern conductive layer, and first gate 11 can be made of another layer pattern conductive layer, and then semiconductor layer can be arranged between this two-layer patterned conductive layer.
In addition, as shown in Figure 2, second picture element system is arranged at the opposite side (for example right side of Fig. 2) of data wire S1 and between the first gate line G1 and the second gate line G2, and second picture element comprises one second pixel electrode P2 and one second thin-film transistor T2.Similarly, the second thin-film transistor T2 comprises one second gate 21, one second source electrode 22 that is electrically connected to data wire S1 that is electrically connected to the second gate line G2, one second drain 23 that is electrically connected to the second pixel electrode P2.Similarly, the second thin-film transistor T2 also comprises semi-conductor layer (figure do not show), is arranged between second source electrode 22, second drain 23 both and second gate 21.In this preferred embodiment, first drain 13 is to extend along a first direction D1 towards first gate 11 being overlapped on first gate 11, and second drain 23 also extends to be overlapped on second gate 21 towards second gate 21 along first direction D1.In addition, the display floater of first preferred embodiment can comprise at least one photoresistance separation material (photo-spacer) 30 in addition, be arranged between at least two picture element unit of a plurality of picture elements unit, be used for keeping the uniformity in the gap of the substrate 200 of the display floater substrate (figure do not show) corresponding, to prevent because of shortcomings such as the uneven institute in the gap show image that produced blur with another.It should be noted that the photoresistance separation material 30 among Fig. 2 is to be arranged on the first gate line G1 and the second gate line G2, but photoresistance separation material 30 of the present utility model the position is set not as limit, and can be arranged at according to designer's demand on other position.For instance, photoresistance separation material 30 also can be arranged on the assemblies such as semiconductor layer, source electrode or drain.
In each picture element unit of first preferred embodiment, the overlapping area of first drain 13 and first gate 11 is the overlapping areas that are same as second drain 23 and second gate 21, makes the first film transistor T 1 have electric capacity between identical lock/drain with the second thin-film transistor T2.Moreover, in each picture element unit of first preferred embodiment,, first drain 13 is same as the bearing of trend that second drain 23 is overlapped in second gate 21 because being overlapped in the bearing of trend of first gate 11.Therefore, even if because of making the interlayer alignment skew that variation produces horizontal direction or vertical direction, first drain 13 of the first film transistor T 1 and the variation of the overlapping area between first gate 11 can be same as second drain 23 of the second thin-film transistor T2 and the variation of the overlapping area between second gate 21.More particularly, the interlayer alignment skew on any direction all can make the feedback voltage of adjacent picture element in the utility model display floater keep unanimity.In view of the above, display floater of the present utility model can effectively solve in the known technology film flicker problem that difference caused because of the feedback voltage of adjacent picture element.
In addition, make the design that electric capacity does not change with the making skew between lock/drain in known technology, display floater of the present utility model can have electric capacity between lower lock/drain.More particularly, known technology is used for keeping the constant mode of electric capacity between lock/drain, is to make between the gate of single picture element and the drain to have two overlapping areas.Under the manufacturing process skew, the two overlapping areas compensation mutually of single picture element that is to say that the recruitment of one of them overlapping area can be same as the reduction of another overlapping area.Yet this known design can increase the occupied area of thin-film transistor, and reduces aperture opening ratio.Simultaneously, this known design can increase capacitance between the lock/drain of single picture element.In comparison, the occupied area of the thin-film transistor of the utility model display floater is less, can improve aperture opening ratio.And the thin-film transistor of the utility model display floater has capacitance between lower lock/drain, can reduce feedback voltage, and then improves display quality.
For the structure of the thin-film transistor of more clearly illustrating the utility model display floater, below further specify at the first film transistor T 1 of first preferred embodiment earlier.Please refer to Fig. 3 A, Fig. 3 A is the schematic diagram that shows the first film transistor T 1 of the utility model first preferred embodiment.As shown in Figure 3A, has a channel region 40 between first source electrode 12 and first drain 13.Watch from the upward angle of visibility degree, the shape of this channel region 40 can be the L type.Similarly, as shown in Figure 2, the second thin-film transistor T2 is same as the first film transistor T 1 substantially, thus also have a channel region 40 between second source electrode 22 and second drain 23, and the shape of channel region 40 is similarly the L type.In first preferred embodiment, first direction D1 is parallel to the bearing of trend of the first gate line G1 substantially, but the utility model is not as limit.Please refer to Fig. 3 B, Fig. 3 B is the embodiment one that shows the first film transistor T 1 of the present utility model.Shown in Fig. 3 B, the bearing of trend D2 of the first direction D1 and the first gate line G1 can have an included angle A, and included angle A is greater than 0 degree and less than 180 degree.More particularly, be same as the bearing of trend that second drain 23 is overlapped in second gate 21 as long as first drain 13 of each picture element unit is overlapped in the bearing of trend of first gate 11, the utility model can make the feedback voltage of adjacent picture element keep unanimity.
In addition, the thin-film transistor of the utility model display floater has other embodiment.Please refer to Fig. 4, Fig. 4 is the embodiment two that shows the first film transistor T 1 of the present utility model.As shown in Figure 4, has a channel region 40 between first source electrode 12 and first drain 13.Watch from the upward angle of visibility degree, the U type that is shaped as of this channel region 40, and be not limited to the L type of Fig. 3 A.Moreover, please refer to Fig. 5, Fig. 5 is the embodiment three that shows the first film transistor T 1 of the present utility model.As shown in Figure 5, first source electrode 12 comprises two elongated ends 121,122, and is overlapping with first gate 11 respectively, and first drain 13 is to be arranged between two elongated ends 121,122 of first source electrode 12.The structure narration of aforementioned relevant the first film transistor T 1 all is applicable to the second thin-film transistor T2, so repeated description no longer.And in same display floater, the first film transistor T 1 of each picture element unit is preferably with the second thin-film transistor T2 has identical channel shape.In view of the above, the design of the thin-film transistor structure of the utility model display floater can make the feedback voltage of adjacent picture element keep unanimity.
Please refer to Fig. 6, Fig. 6 is the schematic diagram that shows the black matrix" of the corresponding picture element unit of the utility model.As shown in Figure 6, display floater of the present utility model also comprises a black matrix" (Black Matrix, BM) 50.It should be noted that Fig. 6 only shows the part of the utility model black matrix" 50 corresponding picture element unit, and promptly formed by a plurality of black matrix" 50 corresponding to the black matrix" of a plurality of picture elements unit.In addition, black matrix" 50 can be arranged on the substrate 200, or is arranged on another corresponding substrate (figure does not show).In the utility model, black matrix" 50 has lighttight a plurality of net-like pattern, and have a plurality of transparent areas 51 in these net-like patterns, transparent area 51 is the first pixel electrode P1 and the second pixel electrode P2 of respectively corresponding each picture element unit substantially, and the distance between each transparent area 51 equates substantially.In view of the above, the utility model display floater can have preferable display effect, and the vertical stripe on the minimizing picture or the generation of horizontal stripe.
Please refer to Fig. 7, Fig. 7 is the schematic diagram that shows the display floater of the utility model second preferred embodiment.Below only partly describe at the difference of first preferred embodiment and second preferred embodiment, identical part repeats no more, and identical assembly is continued to use identical symbol and represented in graphic.As shown in Figure 7, the picture element unit is to arrange in the dislocation mode, and the first pixel electrode P1, the second pixel electrode P2 of each picture element unit and the first pixel electrode P1 of another adjacent picture element unit are arranged in the triangle mode.In view of the above, the arrangement mode of this dislocation can effectively promote the space utilization of display floater of the present utility model, and the area of non-display area is reduced increases aperture opening ratio.
In sum, in each picture element unit of display floater of the present utility model, the bearing of trend that first drain is overlapped in first gate is same as the bearing of trend that second drain is overlapped in second gate.In view of the above, even if the interlayer alignment that causes because of manufacturing process is offset, the overlapping area between transistorized first gate of the first film and first drain can be same as second gate of second thin-film transistor and the overlapping area between second drain.Therefore, the feedback voltage of two adjacent picture elements can be kept unanimity, and then reduces the film flicker problem of display floater.In addition, the occupied area of the thin-film transistor of the utility model display floater is less, can improve aperture opening ratio.And the thin-film transistor of the utility model display floater has capacitance between lower lock/drain, can reduce feedback voltage, and then improves display quality.
The above only is the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.
Claims (10)
1. a display floater is characterized in that, comprising:
One substrate; And
A plurality of picture elements unit is arranged on this substrate, and wherein respectively this picture element unit comprises:
One first gate line, one second gate line and a data wire;
One first picture element is arranged at a side of this data wire and between this first gate line and this second gate line, this first picture element comprises:
One first pixel electrode; And
One the first film transistor comprises:
One first gate is electrically connected to this first gate line;
One first source electrode is electrically connected to this data wire; And
One first drain is electrically connected to this first pixel electrode; And
One second picture element is arranged at the opposite side of this data wire and between this first gate line and this second gate line, this second picture element comprises:
One second pixel electrode; And
One second thin-film transistor comprises:
One second gate is electrically connected to this second gate line;
One second source electrode is electrically connected to this data wire; And
One second drain is electrically connected to this second pixel electrode;
Wherein this first drain extends along a first direction towards this first gate being overlapped on this first gate, and this second drain extends to be overlapped on this second gate towards this second gate along this first direction.
2. display floater according to claim 1 is characterized in that: this first direction is parallel to a bearing of trend of this first gate line substantially.
3. display floater according to claim 1 is characterized in that: a bearing of trend of this first direction and this first gate line has an angle, and this angle is greater than 0 degree and less than 180 degree.
4. display floater according to claim 1 is characterized in that: have a channel region respectively between this first source electrode and this first drain and between this second source electrode and this second drain.
5. display floater according to claim 4 is characterized in that: the L type that is shaped as of this channel region.
6. display floater according to claim 4 is characterized in that: the U type that is shaped as of this channel region.
7. display floater according to claim 1 is characterized in that: this first source electrode comprises that two elongated ends are overlapping with this first gate respectively, and this first drain is to be arranged between two elongated ends of this first source electrode.
8. display floater according to claim 1 is characterized in that: these picture element unit are to arrange with matrix-style.
9. display floater according to claim 1, it is characterized in that: these picture element unit are to arrange in the dislocation mode, and this first pixel electrode of one of adjacent this picture element unit of this first pixel electrode, this second pixel electrode of this picture element unit respectively and another is arranged in the triangle mode.
10. display floater according to claim 1, it is characterized in that: described display floater also comprises a black matrix" (Black Matrix, BM), wherein this black matrix" has lighttight a plurality of net-like pattern, and have a plurality of transparent areas in these net-like patterns, these transparent areas corresponding respectively substantially respectively this first pixel electrode and this second pixel electrode of this picture element unit, and respectively the distance between this transparent area equates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205166918U CN201893340U (en) | 2010-09-04 | 2010-09-04 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205166918U CN201893340U (en) | 2010-09-04 | 2010-09-04 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201893340U true CN201893340U (en) | 2011-07-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205166918U Expired - Fee Related CN201893340U (en) | 2010-09-04 | 2010-09-04 | Display panel |
Country Status (1)
| Country | Link |
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| CN (1) | CN201893340U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489923A (en) * | 2013-10-16 | 2014-01-01 | 京东方科技集团股份有限公司 | Film transistor as well as manufacturing method and repairation method thereof and array substrate |
| CN110112145A (en) * | 2015-01-21 | 2019-08-09 | 群创光电股份有限公司 | Display device |
-
2010
- 2010-09-04 CN CN2010205166918U patent/CN201893340U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489923A (en) * | 2013-10-16 | 2014-01-01 | 京东方科技集团股份有限公司 | Film transistor as well as manufacturing method and repairation method thereof and array substrate |
| CN103489923B (en) * | 2013-10-16 | 2017-02-08 | 京东方科技集团股份有限公司 | Film transistor as well as manufacturing method and repairation method thereof and array substrate |
| US10096686B2 (en) | 2013-10-16 | 2018-10-09 | Boe Technology Group Co., Ltd. | Thin film transistor, fabrication method thereof, repair method thereof and array substrate |
| CN110112145A (en) * | 2015-01-21 | 2019-08-09 | 群创光电股份有限公司 | Display device |
| CN110112145B (en) * | 2015-01-21 | 2023-08-29 | 群创光电股份有限公司 | display device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170808 Address after: Third, fourth floor, 1 floor, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: 350015 No. 1 Xingye Road, Mawei Science Park, Fujian, Fuzhou Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110706 Termination date: 20190904 |