CN105810605A - Test structure for checking insulation performance of side wall of poly-silicon grid - Google Patents

Test structure for checking insulation performance of side wall of poly-silicon grid Download PDF

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Publication number
CN105810605A
CN105810605A CN201610173720.7A CN201610173720A CN105810605A CN 105810605 A CN105810605 A CN 105810605A CN 201610173720 A CN201610173720 A CN 201610173720A CN 105810605 A CN105810605 A CN 105810605A
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CN
China
Prior art keywords
polysilicon
side wall
checking
insulating properties
gate side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610173720.7A
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Chinese (zh)
Inventor
吴奇伟
尹彬锋
王炯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201610173720.7A priority Critical patent/CN105810605A/en
Publication of CN105810605A publication Critical patent/CN105810605A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors

Abstract

The invention provides a test structure for checking insulation performance of a side wall of a poly-silicon grid. The test structure comprises a first test bonding pad, a second test bonding pad and a metal comb-shaped structure, wherein the metal comb-shaped structure is connected with the second test bonding pad, a first comb-shaped structure is connected with a poly-silicon structure, and the metal comb-shaped structure is connected with a through hole of a source/drain.

Description

For checking the test structure of polysilicon gate side wall insulating properties
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of test structure for checking polysilicon gate side wall insulating properties.
Background technology
In ic manufacturing process, owing to the improper meeting of making technology causes source/drain reach through hole to deviate desired value with the polysilicon distance as grid, directly result in grid curb wall bigger by electric field, it is easy to breakdown;And, when deviateing serious, source/drain reach through hole and polysilicon short can be caused.And the residue of source/drain reach through hole and inter polysilicon will also result in above-mentioned phenomenon.This problem not only can cause yield issues, more has potential security risk.
Lack the effective regulatory measure to above-mentioned phenomenon at present, it is impossible to assess the impact that reliability is produced.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that the test structure of a kind of insulating properties that polysilicon gate side wall can effectively be detected.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of test structure for checking polysilicon gate side wall insulating properties, including: the first testing weld pad, the second testing weld pad and the metal pectinate texture being connected with the second testing weld pad;Wherein, the first pectinate texture connects polysilicon structure, and metal pectinate texture connects source/drain reach through hole.
Preferably, polysilicon structure is grid polycrystalline silicon or is connected to grid polycrystalline silicon.
Preferably, polysilicon structure is the list structure parallel with the comb of metal pectinate texture, and metal pectinate texture and the first pectinate texture interlaced arrangement.
Preferably, the spacing of polysilicon structure and source/drain reach through hole follows minimal design specification, and the length of polysilicon structure meets design maximum specification.
Preferably, it is the oxide substrate generated by shallow ditch groove separation process under polysilicon structure and source/drain reach through hole.
In order to realize above-mentioned technical purpose, according to the present invention, additionally provide a kind of test structure for checking polysilicon gate side wall insulating properties, including: the first testing weld pad, the second testing weld pad and the metal serpentine configuration being connected with the second testing weld pad;Wherein, the first pectinate texture connects polysilicon structure, and metal serpentine configuration connects source/drain reach through hole.
Preferably, polysilicon structure is grid polycrystalline silicon or is connected to grid polycrystalline silicon.
Preferably, polysilicon structure is strip polysilicon structure or the comb-like polysilicon structure of the interlaced arrangement with metal serpentine configuration.
Preferably, the spacing of polysilicon structure and source/drain reach through hole follows minimal design specification, and, the length of polysilicon structure meets design maximum specification.
Preferably, it is the oxide substrate generated by shallow ditch groove separation process under polysilicon structure and source/drain reach through hole.
The test structure of present invention design effectively can detect at wafer end, namely certain bias is added at structure two ends, detection electric leakage, if detecting big electric leakage or the relatively low situation of breakdown voltage, then shows polysilicon and reach through hole spacing deviation desired value or has residue.Thus can find and improve process conditions in time, reduce quality risk cost.Thus, the test structure of present invention design can be used in the insulating properties of detection polysilicon gate side wall, it is possible to due to ranging offset or residue cause side wall to bear yield and integrity problem that electric field causes relatively greatly between detection polysilicon gate and source/drain reach through hole.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the structure top view of the test structure for checking polysilicon gate side wall insulating properties according to first preferred embodiment of the invention.
Fig. 2 schematically shows the sectional view of the test structure for checking polysilicon gate side wall insulating properties according to first preferred embodiment of the invention.
Fig. 3 schematically shows the structure top view of the test structure for checking polysilicon gate side wall insulating properties according to second preferred embodiment of the invention.
Fig. 4 schematically shows the sectional view of the test structure for checking polysilicon gate side wall insulating properties according to second preferred embodiment of the invention.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure is likely to be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure clearly with understandable, below in conjunction with specific embodiments and the drawings, present disclosure is described in detail.
It was found by the inventors of the present invention that source/drain reach through hole deviation occurs with polysilicon gate anode-cathode distance or has residue, the pressure performance of polysilicon gate side wall all will be caused to reduce.Therefore, inventor's design meets a plurality of or pectination required in following requirements or serpentine configuration, to play the resistance to pressure checking polysilicon gate side wall:
1. structure one end connects polysilicon, and the other end connects source/drain reach through hole;
2. polysilicon and source/drain reach through hole spacing follow minimal design specification, and length meets design maximum specification;
3. it is the oxide substrate generated by shallow ditch groove separation process (following design specification) under polysilicon and source/drain reach through hole, but not traditional silicon substrate, it is prevented that polysilicon bottom and source/drain reach through hole puncture.
<the first preferred embodiment>
Fig. 1 schematically shows the structure top view of the test structure for checking polysilicon gate side wall insulating properties according to first preferred embodiment of the invention.Fig. 2 schematically show shown in Fig. 1 according to the preferred embodiment of the invention for checking the sectional view along arrow tangent line shown in Fig. 1 of the test structure of polysilicon gate side wall insulating properties.
As depicted in figs. 1 and 2, according to first preferred embodiment of the invention for checking that the test structure of polysilicon gate side wall insulating properties includes: first testing weld pad the 10, second testing weld pad 20 and the metal pectinate texture 22 being connected with the second testing weld pad 20;Wherein, the first pectinate texture 11 connects polysilicon structure 11, and metal pectinate texture 22 connects source/drain reach through hole 30.
Wherein, for instance, polysilicon structure 11 can be specifically grid polycrystalline silicon or be connected to grid polycrystalline silicon 12 (as shown in Figure 2).Preferably, polysilicon structure 11 is the list structure parallel with the comb of metal pectinate texture 22.It is further preferred that metal pectinate texture 22 and the first pectinate texture 11 interlaced arrangement.
Wherein it is preferred to, the spacing of polysilicon structure 11 and source/drain reach through hole 30 follows minimal design specification.And, the length of polysilicon structure 11 meets design maximum specification.
Preferably, it is the oxide substrate 40 generated by shallow ditch groove separation process (such as, it then follows design specification) under polysilicon structure 11 and source/drain reach through hole.
Thus, it is possible to add certain bias at structure two ends, detection electric leakage, if detecting big electric leakage or the relatively low situation of breakdown voltage, then show polysilicon and reach through hole spacing deviation desired value or have residue.
<the second preferred embodiment>
Fig. 3 schematically shows the structure top view of the test structure for checking polysilicon gate side wall insulating properties according to second preferred embodiment of the invention.Fig. 4 schematically show shown in Fig. 3 according to the preferred embodiment of the invention for checking the sectional view along arrow tangent line shown in Fig. 3 of the test structure of polysilicon gate side wall insulating properties.
As shown in Figure 3 and Figure 4, according to second preferred embodiment of the invention for checking that the test structure of polysilicon gate side wall insulating properties includes: first testing weld pad the 10, second testing weld pad 20 and the metal serpentine configuration 60 being connected with the second testing weld pad 20;Wherein, the first pectinate texture 11 connects polysilicon structure 11, and metal serpentine configuration 60 connects source/drain reach through hole 30.
Wherein, for instance, polysilicon structure 11 can be specifically grid polycrystalline silicon or be connected to grid polycrystalline silicon 12 (as shown in Figure 2).Preferably, polysilicon structure 11 is strip polysilicon structure or the comb-like polysilicon structure of the interlaced arrangement with metal serpentine configuration 60.
Wherein it is preferred to, the spacing of polysilicon structure 11 and source/drain reach through hole 30 follows minimal design specification.And, the length of polysilicon structure 11 meets design maximum specification.
Preferably, it is the oxide substrate 40 generated by shallow ditch groove separation process (such as, it then follows design specification) under polysilicon structure 11 and source/drain reach through hole.
Equally, structure two ends add certain bias, detection electric leakage, if detecting big electric leakage or the relatively low situation of breakdown voltage, then show polysilicon and reach through hole spacing deviation desired value or have residue.
In a word, the test structure of present invention design effectively can detect at wafer end, namely adds certain bias, detection electric leakage at structure two ends, if detecting big electric leakage or the relatively low situation of breakdown voltage, then show polysilicon and reach through hole spacing deviation desired value or have residue.Thus can find and improve process conditions in time, reduce quality risk cost.Thus, the test structure of present invention design can be used in the insulating properties of detection polysilicon gate side wall 50 (as shown in Figure 2 and Figure 4), it is possible between detection polysilicon gate and source/drain reach through hole due to ranging offset or residue cause side wall to bear electric field is relatively big and the yield that causes and integrity problem.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the description such as the term in description " first ", " second ", " the 3rd " is used only for each assembly in differentiation description, element, step etc., rather than is used for logical relation or the ordering relation etc. that represent between each assembly, element, step.
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is not limited to the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the technology contents of the disclosure above and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.

Claims (10)

1. the test structure being used for checking polysilicon gate side wall insulating properties, it is characterised in that including: the first testing weld pad, the second testing weld pad and the metal pectinate texture being connected with the second testing weld pad;Wherein, the first pectinate texture connects polysilicon structure, and metal pectinate texture connects source/drain reach through hole.
2. the test structure for checking polysilicon gate side wall insulating properties according to claim 1, it is characterised in that polysilicon structure is grid polycrystalline silicon or is connected to grid polycrystalline silicon.
3. the test structure for checking polysilicon gate side wall insulating properties according to claim 1 and 2, it is characterized in that, polysilicon structure is the list structure parallel with the comb of metal pectinate texture, and metal pectinate texture and the first pectinate texture interlaced arrangement.
4. the test structure for checking polysilicon gate side wall insulating properties according to claim 1 and 2, it is characterized in that, the spacing of polysilicon structure and source/drain reach through hole follows minimal design specification, and the length of polysilicon structure meets design maximum specification.
5. the test structure for checking polysilicon gate side wall insulating properties according to claim 1 and 2, it is characterised in that be the oxide substrate generated by shallow ditch groove separation process under polysilicon structure and source/drain reach through hole.
6. the test structure being used for checking polysilicon gate side wall insulating properties, it is characterised in that including: the first testing weld pad, the second testing weld pad and the metal serpentine configuration being connected with the second testing weld pad;Wherein, the first pectinate texture connects polysilicon structure, and metal serpentine configuration connects source/drain reach through hole.
7. the test structure for checking polysilicon gate side wall insulating properties according to claim 6, it is characterised in that polysilicon structure is grid polycrystalline silicon or is connected to grid polycrystalline silicon.
8. the test structure for checking polysilicon gate side wall insulating properties according to claim 6 or 7, it is characterised in that polysilicon structure is strip polysilicon structure or the comb-like polysilicon structure of the interlaced arrangement with metal serpentine configuration.
9. the test structure for checking polysilicon gate side wall insulating properties according to claim 6 or 7, it is characterized in that, the spacing of polysilicon structure and source/drain reach through hole follows minimal design specification, and, the length of polysilicon structure meets design maximum specification.
10. the test structure for checking polysilicon gate side wall insulating properties according to claim 6 or 7, it is characterised in that be the oxide substrate generated by shallow ditch groove separation process under polysilicon structure and source/drain reach through hole.
CN201610173720.7A 2016-03-24 2016-03-24 Test structure for checking insulation performance of side wall of poly-silicon grid Pending CN105810605A (en)

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Application Number Priority Date Filing Date Title
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Cited By (1)

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CN109727956A (en) * 2019-01-08 2019-05-07 长江存储科技有限责任公司 A kind of test structure, semiconductor devices

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CN103178053A (en) * 2011-12-23 2013-06-26 上海华虹Nec电子有限公司 Wafer level test structure and method
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CN103887283A (en) * 2014-03-27 2014-06-25 上海华力微电子有限公司 Polycrystalline silicon residue monitoring structure
CN104201171A (en) * 2014-09-01 2014-12-10 上海华力微电子有限公司 Testing structure for detecting defect remains
CN104425455A (en) * 2013-09-09 2015-03-18 中芯国际集成电路制造(上海)有限公司 Test structure and test method for side ditch problem of shallow trench isolation structure
CN104465614A (en) * 2013-09-18 2015-03-25 中芯国际集成电路制造(上海)有限公司 Test structure and corresponding test method
CN104465615A (en) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Structure for monitoring leakage current and junction capacitance at source/drain electrode and gate joint position

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US20060148138A1 (en) * 2004-12-30 2006-07-06 Dongbuanam Semiconductor Inc. Field transistor monitoring pattern for shallow trench isolation defects in semiconductor device
KR101030295B1 (en) * 2004-12-30 2011-04-20 동부일렉트로닉스 주식회사 Field Transistor for Testing Isolation in Semiconductor Device
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CN102157496A (en) * 2010-02-12 2011-08-17 中芯国际集成电路制造(上海)有限公司 Contact hole test device and method for testing leakage current of grid by active area contact hole
CN103178053A (en) * 2011-12-23 2013-06-26 上海华虹Nec电子有限公司 Wafer level test structure and method
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* Cited by examiner, † Cited by third party
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CN109727956A (en) * 2019-01-08 2019-05-07 长江存储科技有限责任公司 A kind of test structure, semiconductor devices
CN109727956B (en) * 2019-01-08 2020-11-13 长江存储科技有限责任公司 Test structure and semiconductor device

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