JP4815861B2 - Evaluation method for evaluating positional relationship between PN junction surface of semiconductor device and bottom of trench - Google Patents

Description

  The present invention relates to a method for evaluating the positional relationship between a PN junction surface of a semiconductor device and a trench bottom, and in particular, has a structure having a portion in which cell regions are periodically thinned out from a plurality of continuous cell regions (hereinafter referred to as the following). This is suitable for electrical inspection of a portion where a cell region is thinned out for a trench gate type insulated gate bipolar transistor (hereinafter referred to as IGBT) having a thinned structure.

  Conventionally, a semiconductor device has a structure in which a semiconductor layer is electrically divided into two regions by a trench, one of the two regions is electrically connected to an electrode, and the other is not electrically connected to the electrode. is there.

  FIG. 11 shows a cross-sectional view of an IGBT having such a structure. The cross-sectional view shown in FIG. 11 is a cross-sectional view when cut across the trench. The IGBT shown in FIG. 11 is a trench gate type IGBT with a thinning structure.

The IGBT includes a P ⁺ type substrate 1, an N ⁻ type drift layer 2 disposed on the surface of the P ⁺ type substrate 1, and a P type base region 3 disposed on the surface of the N ⁻ type drift layer 2. , the N ⁺ -type emitter region 4 located on the inner surface side of the P-type base region 3, from the surface of the P-type base region 3, through the N ⁺ -type emitter region 4 and the P-type base region 3, N ^- -type A trench 5 having a depth reaching the drift layer 2, a gate insulating film 6 formed on the inner wall of the trench 5, a gate electrode 7 formed on the gate insulating film 6 inside the trench 5, Arranged on the surface of the P-type base region 3, an emitter electrode 8 electrically connected to a part of the P-type base region 3 and the N ⁺ -type emitter region 4, and the rear surface of the P ⁺ -type substrate 1. A collector electrode 9 electrically connected to the P ⁺ type substrate 1 It has.

In this IGBT, as shown in the left and right half in the figure, the P-type base region 3 is electrically divided into two regions 3a and 3b by a trench 5, and of these two regions 3a and 3b, N ⁺ type emitter region 4 and P type body region 10 are formed only in one region 3a. This one region 3 a is electrically connected to the emitter electrode 8 through the P-type body region 10. Further, the N ⁺ -type emitter region 4 is partially disposed in a region in the vicinity of the trench 5 in the one region 3a, and a channel is formed in a portion in contact with the trench 5 in the one region 3a. Thus, one region 3a where the IGBT element is formed is a cell region in the figure.

  Of the two regions 3a and 3b, the other region 3b is electrically insulated from the emitter electrode 8 and other electrodes by the insulating film 11, and is in an electrically floating state. . The other region 3b is a region obtained by thinning a cell region from a plurality of continuous cell regions, and is a floating region in the figure (see, for example, Patent Document 1).

As a method for evaluating the positional relationship between the PN junction surfaces of the N ⁻ -type drift layer 2 and the P-type base region 3 and the bottom 5a of the trench 5 in the semiconductor device having such a structure, SEM (Scanning Electron Microscopy), There are methods for evaluation using microscopic techniques such as SR (Spread Resistance) and SCM (Scanning Capacitance Microscopy). For example, in the evaluation method using SEM, the positional relationship between the PN junction surface and the bottom 5a of the trench 5 is evaluated by observing the cross section of the semiconductor device.

  As a method for measuring the trench depth, for example, there are the following two methods. As a first method, a groove as a detector portion that is deep and widens in advance is formed on a silicon substrate, and a trench for depth measurement is formed around this portion. There is a method of calculating the trench depth based on the distance from the trench where the bottom of the trench reaches the detector and the detector in the trench pattern (see Patent Document 2).

In addition, as a second method, a casting solution is dropped on a substrate on which a trench is formed, thereby forming a negative replica having a protruding portion along the shape of the trench. Based on the negative replica, a trench depth is formed. There is a method for calculating the thickness (see Patent Document 3).
No. 2003-204066 Japanese Patent No. 2783309 No. 2003-124279

  The evaluation method using the microscopic technique described above is a destructive measurement in which a portion to be measured of a sample is divided, and once analyzed, there is a problem that other analysis cannot be performed.

  Moreover, although the method of patent document 2, 3 can calculate trench depth, without destroying a semiconductor substrate, it is performed before metal wiring is formed on a substrate surface. It cannot be used after metal wiring is formed on the surface.

  The above-mentioned problem is a problem that occurs in the same manner even when the evaluation target is a semiconductor device other than the IGBT.

In view of the above points, the present invention provides an evaluation method capable of evaluating the positional relationship between the PN junction surface and the trench bottom without destroying the semiconductor substrate even after the metal wiring is formed on the substrate surface. The purpose is to do.

In order to achieve the above object, according to the first and second aspects of the invention, the insulation between the first electrode (7) and the second electrode (8) in a state where a voltage is applied to the third electrode (9). The volume of the membrane (6) is measured. Then, the measurement result, based on the magnitude of the relationship between the size and the third voltage applied to the electrodes (9) of the volume, is set to the this for evaluating the positional relationship.

  Here, regarding the relationship between the magnitude of the capacitance of the insulating film and the magnitude of the voltage applied to the third electrode, there is a difference between when the bottom of the trench has reached the PN junction surface and when not reached. . That is, only when the trench does not reach, the measured insulating film portion is different before and after the depletion layer formed in the vicinity of the PN junction extends to reach the bottom of the trench. A large capacity change occurs at a certain size.

  In addition, regarding the relationship between the capacitance of the insulating film and the magnitude of the voltage applied to the third electrode, when the bottom of the trench does not reach the PN junction surface, the PN junction between the bottom of the trench and the PN junction surface There is a certain relationship between the distance in the direction perpendicular to the surface and the magnitude of the voltage applied to the third electrode when the capacitance change described above occurs.

  Therefore, as in the present invention, by utilizing these relations, it is possible to determine whether the trench reaches the junction interface from the surface of the second semiconductor layer, the distance from the junction interface to the bottom of the trench, etc. The relative positional relationship between the joint surface and the bottom of the trench can be evaluated.

  Further, in the evaluation method of the present invention, since the capacity of the insulating film (6) between the first electrode (7) and the second electrode (8) is measured, metal wiring is formed on the substrate surface. Even after this, the positional relationship between the PN junction surface and the trench bottom can be evaluated without destroying the semiconductor substrate.

In concrete terms, between the invention described in claim 1, in a state where a voltage is applied to the different sizes third electrode (9), a first electrode (7) and the second electrode (8) A plurality of capacities of the insulating film (6) are measured.

  Subsequently, in the insulating film (6), the amount of change between the measurement results is the capacitance of both the part (6a) in contact with one region (3a) and the part (3b) in contact with the other region (3b), It is determined whether or not the size corresponds to the difference from the capacity of only the portion (6a) in contact with one region (3a). And the electrical connection state with the 2nd electrode (8) in the other area | region (3b) can be evaluated from the determination result.

  As described above, when the trench does not reach the PN junction surface in the relationship between the capacity of the insulating film and the voltage applied to the third electrode, one region and the other region Are connected to the lower side of the trench and are conductive. Therefore, the insulating film (6) has a portion (6a) in contact with one region (3a) and a portion (3b) in contact with the other region (3b). Both capacities are measured. When the voltage applied to the third electrode (9) has a certain magnitude, the depletion layer reaches the bottom of the trench, and one region and the other region are insulated, so one region of the insulating film This is because only the capacity of the portion (6a) in contact with (3a) is measured.

  In the present invention, it is necessary that the magnitude of the voltage applied to the third electrode is at least a magnitude within a range where the capacitance change occurs when the trench does not reach the PN junction surface.

In the second aspect of the present invention, the capacitance of the insulating film (6) between the first electrode (7) and the second electrode (8) in a state where a voltage is applied to the third electrode (9). taking measurement. The magnitude of the voltage applied to the third electrode (9) when the measured capacitance changes due to the depletion layer (21) generated near the junction surface (3c) reaching the bottom (5a) of the trench (5). Based on the above, the distance in the direction perpendicular to the PN junction surface (3c) from the PN junction surface (3c) to the bottom (5a) of the trench (5) can be calculated.

  In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
The present embodiment is an example in which the evaluation method of the present invention is applied to an electrical inspection method in a portion (the other region 3b) where a cell region is thinned out for a trench gate type IGBT having a thinned structure.

  First, the structure of the IGBT to be evaluated in this embodiment will be described. FIG. 1 shows a plan layout diagram of an IGBT to be evaluated in the first embodiment of the present invention. Since the cross-sectional structure taken along the line AA in FIG. 1 is the same as the cross-sectional structure shown in FIG. In FIG. 1, the emitter electrode 8 and the insulating film 11 in FIG. 11 are omitted.

  In the present embodiment, as shown in FIG. 1, the planar layout of the IGBT includes one region 3 a and the other region 3 b of the two regions electrically separated by the trench 5 in the P-type base region 3. In the layout, the plurality of other regions 3b are alternately surrounded by the trenches 5 and are alternately arranged in stripes.

In the present embodiment, in the structure shown in FIG. 11, for example, a silicon (Si) substrate is used as the P ⁺ type substrate 1, and the P type base region 3 is formed of an impurity diffusion layer. A silicon oxide film (SiO ₂ film) is used as the gate insulating film 6. The gate electrode 7 is made of polysilicon (Poly-Si) doped with phosphorus (P) at a high concentration to reduce resistance.

  Here, FIG. 2 shows an example of a normal structure, and FIG. 3 shows an example of an abnormal structure. 2 and 3 are partially enlarged views of the region B in FIG. 11, and the same reference numerals as those in FIG.

When the IGBT has a normal structure, as shown in FIG. 2, the trench 5 extends from the surface of the P-type base region 3 toward the N ⁻ -type drift layer 2, and the depth penetrates the P-type base region 3. The bottom 5a of the trench 5 (hereinafter referred to as the trench bottom 5a) reaches the N ⁻ type drift layer 2. In other words, in the case of the normal structure, the trench bottom 5 a is located closer to the N ⁻ type drift layer 2 than the PN junction surface 3 c formed by the N ⁻ type drift layer 2 and the P type base region 3.

  In this case, since the other region 3b is electrically separated from the one region 3a by the trench 5, the other region 3b is electrically floating.

On the other hand, when the IGBT has an abnormal structure, as shown in FIG. 3, the trench 5 extends from the surface of the P-type base region 3 toward the N ⁻ -type drift layer 2. It is shallower than. That is, in the case of the abnormal structure, the trench bottom 5a is located closer to the P-type base region 3 than the PN junction surface 3c.

  In this case, the other region 3b is not electrically separated from the one region 3a, and is electrically connected to the one region 3a. Therefore, the other region 3b is not floating.

2 and 3, the N ⁻ type drift layer 2 is electrically connected to the collector electrode 9 via the P ⁺ type substrate 1 which is omitted in FIGS.

The correspondence relationship between the present embodiment and the present invention is as follows. The N type corresponds to the first conductivity type, and the P type corresponds to the second conductivity type. The N ⁻ type drift layer 2 corresponds to the first semiconductor layer, and the P type base region 3 corresponds to the second semiconductor layer. The gate insulating film 6 corresponds to an insulating film, the gate electrode 7 corresponds to a first electrode, the emitter electrode 8 corresponds to a second electrode, and the collector electrode 9 corresponds to a third electrode.

  Next, a floating inspection method for the other region 3b performed on the IGBT having the above structure will be described. This floating inspection is to inspect whether or not the other region 3b is electrically floating with respect to the manufactured IGBT.

  In the present embodiment, whether or not the manufactured IGBT has an abnormal structure as shown in FIG. 3 is inspected by measuring the input capacitance of the IGBT. FIG. 4 shows a measurement circuit diagram for measuring the input capacitance of the IGBT. In this measuring circuit, as shown in FIG. 4, a capacitor is arranged between the collector and the emitter.

Specifically, as shown in FIG. 4, the collector - in a state of applying a reverse voltage V _CE of several V~ several hundred V between the emitter, the input capacitance (emitter at each applied voltage - capacitance between the gate C _A plurality of the total capacitance C _GC between the _GE and the collector-gate are measured. In this input capacitance measurement, a general measurement method can be employed.

Then, it is determined and the measurement result, based on the magnitude of the relationship between the magnitude of the collector voltage V _CE of the input capacitance, the other region 3b is whether the floating.

  That is, when the input capacitance in the case of the normal structure and the case of the abnormal structure are measured by the circuit shown in FIG. 4, only when the collector voltage is gradually increased as described later, only when the collector voltage is gradually increased. From that time on, the input capacitance changes greatly. Therefore, a plurality of input capacitances are measured while gradually increasing the collector voltage, and the presence or absence of a large change in the measured input capacitance is examined. As a result, if there is a large capacitance change, it can be determined that the other region 3b is not floating and that the IGBT has an abnormal structure. On the other hand, if there is no large capacitance change, the other region 3b is floating, and it can be determined that the IGBT has a normal structure.

Here, the relationship between the magnitude of the input capacitance and the collector voltage when the IGBT has a normal structure and an abnormal structure will be described. FIG. 5 shows the measurement results of the input capacitance when the collector voltage V _CE is changed in the range of 0 to 300 V for the normal structure and the abnormal structure IGBT.

  Note that normal products A and B in FIG. 5 are IGBTs having a normal structure, and abnormal products are IGBTs having an abnormal structure. In the normal product A, the distance in the direction perpendicular to the PN junction surface 3c from the PN junction surface 3c to the trench bottom 5a is larger than that in the normal product B. The normal products A and B and the abnormal product have the same conditions except that the positional relationship between the trench bottom 5a and the PN junction surface 3c is different.

  As shown in FIG. 5, in the case of the normal structure, when the collector voltage is gradually increased from 0V, the input capacitance slightly decreases between 1 to 10V, but after that, the input capacitance is almost constant up to 300V. Become. That is, it can be seen from FIG. 5 that in the relationship between the collector voltage and the input capacitance, there is a convex change point downward only when the collector voltage is between 1 and 10V.

  On the other hand, in the case of the abnormal structure, when the collector voltage is gradually increased from 0V, the input capacitance slightly decreases between 1 and 10V, as in the case of the normal structure. The input capacitance is greatly reduced when the collector voltage is 40V to 150V. That is, it can be seen from FIG. 5 that in the relationship between the collector voltage and the input capacitance, there is a convex change point downward between 1 and 10 V and the collector voltage is between 40 and 150 V. It can be seen that there is a convex change point toward.

In the case of an abnormal structure, for example, when the collector voltage is 40V, the input capacitance is about 2.7 × E ⁻⁹ nF , but when the collector voltage is 150V, it is about 2 × E ⁻⁹ nF . Note that the amount of decrease in input capacitance when the collector voltage is in the range of 40 to 150 V is larger than the amount of decrease in input capacitance when the collector voltage is in the range of 1 to 10 V, and is naturally larger than the range of measurement error.

  Therefore, the magnitude of the collector voltage is varied in a voltage range in which the input capacitance changes greatly in the case of an abnormal structure, for example, a range of several tens to several hundreds V, and a plurality of input capacitances of the manufactured IGBT are measured. Then, by examining whether or not the above-described large change in input capacitance has occurred, it is possible to inspect whether the other region 3b is floating.

  Next, the reason why a large change in input capacitance occurs when the collector voltage is increased as described above only in the case of an abnormal structure will be described.

FIGS. 6 and 7 show conceptual diagrams when the input capacitances of the IGBTs of the normal structure and the abnormal structure are measured. 6 and 7 are diagrams corresponding to FIGS. 2 and 3, respectively, and the same reference numerals as those in FIGS. Further, (a) and (b) in each figure show measurement situations when the collector voltage _{VCE is set} to 0V and several hundreds V, respectively.

When the IGBT has a normal structure, as shown in FIGS. 6A and 6B, when the IGBT input capacitance is measured, one region of the gate insulating film 6 is used as the emitter-gate capacitance _CGE. Only the capacitance of the gate insulating film 6a on one region side in contact with 3a is measured.

For this reason, even when the collector voltage V _CE is increased, as shown in FIG. 6B, the gate insulating film 6a on one side is measured as the emitter-gate capacitance C _GE . The change of the input capacitance is small, and the input capacitance is almost constant.

When a reverse voltage is applied between the collector and the emitter, and the applied voltage is increased, the depletion layer 21 generated in the vicinity of the PN junction surface 3c starts from the vicinity of the PN junction surface 3c to the P-type base region 3. It grows on the surface side (upper side in the figure). Therefore, when increasing the collector voltage, emitter - decreases the capacitance C _GE slightly between gates. In FIG. 5, the reason why the input capacitance decreases when the collector voltage V _CE is between 1 and 10 V is presumed to be that the depletion layer capacitance of the gate-collector capacitance C _GC decreases. The

On the other hand, when the IGBT has an abnormal structure, as shown in FIG. 7A, in the range where the collector voltage _VCE is low, there is a leakage path between the other region 3b and the one region 3a below the trench 5. Not floating. Therefore, when measuring the input capacitance of the IGBT, the emitter - as capacitance C _GE between the gate, as well as capacitance of the gate insulating film 6a of one area side, the other being formed in contact with the other region 3b The capacitance of the gate insulating film 6b on the region side is also measured.

Then, as shown in FIG. 7B, when the collector voltage V _CE has a certain value within the range of 40V to 150V, the depletion layer 21 reaches the trench bottom 5a, and therefore exists below the trench 5. The leaked path disappears. Therefore, only the capacitance of the gate insulating film 6a on one region side is measured as the emitter-gate capacitance _CGE .

For this reason, in the abnormal structure, when the input capacitance is measured while increasing the collector voltage, when the collector voltage V _CE exceeds a certain level (the size at which the depletion layer 21 reaches the trench 5), the input capacitance is Decrease significantly.

Next, main features of the present embodiment will be described. In the present embodiment, as described above, a plurality of input capacitances are measured in a state in which various voltages are applied to the collector electrode 9 with the emitter electrode 8 as the ground potential for the thinned trench gate type IGBT. . Then, when the voltage applied to the collector electrode 9 is gradually increased, the floating inspection of the other region 3b is performed by examining whether or not the capacitance value greatly decreases.

  Thereby, even after the metal wiring is formed on the substrate surface, the floating inspection of the other region 3b can be performed without destroying the semiconductor substrate.

Then, according to the method of the present embodiment, the abnormal structure of the IGBT as shown in FIGS. 8 and 9 can be detected. 8 and 9 are perspective views showing examples of the abnormal structure, and correspond to a region C in FIG. 8 and 9, the same components as those in FIG. 11 are denoted by the same reference numerals as those in FIG. 11. For convenience of explanation, only the N ⁻ -type drift layer 2, the P-type base region 3, and the trench 5 are provided. Show.

  The abnormal structure shown in FIG. 8 is a structure in which the trench 5 arranged completely surrounding the other region 3b has a uniform depth and the trench bottom 5a does not reach the PN junction surface 3c. Further, the abnormal structure shown in FIG. 9 is a structure in which the trench bottom 5a does not reach the PN junction surface 3c in the portion 5c of the trench 5 disposed so as to surround the other region 3b. Note that the abnormal structure shown in FIG. 9 can be detected by increasing the measurement accuracy.

  As another floating inspection method different from the present embodiment, a contact is provided in the other region 3b having a floating potential, and an electric resistance between the inspection pad electrically connected to this contact and the emitter electrode 8 is provided. There is a way to measure.

  However, in this method, it is necessary to provide a contact or a special structure such as a lead-out wiring for electrically connecting the contact and the inspection pad, which complicates the mask pattern and reduces the effective cell area. There was a problem such as.

  On the other hand, since the inspection method of this embodiment measures the input capacitance, it is not necessary to provide a special structure for the inspection of contacts, routing wirings, etc. in the IGBT. For this reason, the above-described problems can be solved.

(Second Embodiment)
In the first embodiment, whether or not the trench bottom 5a has reached the PN junction surface 3c in the floating inspection of the other region 3b, that is, the positional relationship in the depth direction between the PN junction surface 3c and the trench bottom 5a. The method for evaluating the above has been described as an example.

  On the other hand, in the present embodiment, for example, as shown in FIG. 8, the thinned trench gate type IGBT has the trench 5 having a uniform depth and the trench bottom 5a does not reach the PN junction surface 3c. In the case of an abnormal structure, a method for calculating the distance from the PN junction surface 3c to the trench bottom 5a in the direction perpendicular to the PN junction surface 3c will be described.

  FIG. 10 is a partial perspective view of a semiconductor device to be evaluated. The structure shown in FIG. 10 is the same as FIG. 8, and corresponds to the region C in FIG. In FIG. 10, the same components as those in FIG. 11 are denoted by the same reference numerals as those in FIG.

As shown in FIG. 10, in the direction perpendicular to the PN junction surface 3c (up and down direction in the figure), the distance from the PN junction surface 3c to the trench bottom 5a is W0, and the depletion layer 21 in the P-type base region 3 The distance from the end to the trench bottom 5a is defined as WV _CE .

When the input capacitance of the IGBT is measured, as described in the first embodiment, when the collector voltage V _CE is small and WV _CE > 0, the emitter-gate capacitance C _{GE is used} as one region side. Both the capacitance of the gate insulating film 6a and the capacitance of the gate insulating film 6b on the other region side are measured. On the other hand, when the collector voltage V _CE is increased and WV _CE <0, only the capacitance of the gate insulating film 6a on one region side is measured as the emitter-gate capacitance C _GE . That is, the input capacitance changes greatly with the collector voltage V _CE as the voltage when WV _CE = 0.

Therefore, in the present embodiment, as in the first embodiment, first, a plurality of IGBT input capacitances are measured, and the magnitude of the collector voltage V _CE when the input capacitance change point (WV _CE = 0) is obtained. . Then, from the magnitude of the collector voltage V _CE at that time, as described below, calculates the distance W0.

Here, there is a certain relationship between the magnitude of the collector voltage V _CE when the input capacitance changes and the distance W0 between the PN junction surface 3c and the trench bottom 5a. The smaller the distance W0, the smaller the collector voltage _VCE when the input capacitance changes. Therefore, in the case where various conditions other than the trench depth of the IGBT such as the impurity concentration of the N ⁻ type drift layer 2 and the P type base region 3 are constant, the above-described relationship is investigated in advance.

  Thus, the distance W0 in the direction perpendicular to the PN junction surface 3c from the PN junction surface 3c to the trench bottom 5a is calculated based on the magnitude of the collector voltage when the input capacitance changes and the relationship described above. be able to.

  Also in this embodiment, the input capacitance of the IGBT is measured, and the distance W0 from the PN junction surface 3c to the trench bottom 5a is calculated based on the measurement result. Therefore, the same effect as that of the first embodiment is obtained. have.

(Other embodiments)
(1) In the first embodiment, the case where the input capacitance is measured while changing the magnitude of the collector voltage V _CE in the range of several V to several hundred V has been described as an example. However, the number of input capacitances to be measured is arbitrary. Can be changed.

For example, the number of measurements can be two. In the case of the abnormal structure, whether or not there is a change in the input capacitance can be obtained by comparing the input capacitance when the magnitude of the collector voltage V _{CE is} the magnitude before and after the depletion layer 21 is expected to reach the trench bottom 5a. Because I understand. In this case, it is preferable to determine the magnitude of the collector voltage V _CE by assuming the position range of the trench bottom 5a in the case of an abnormal structure.

(2) In the first embodiment, a case where a floating inspection is performed by comparing a plurality of measured input capacitances and determining whether or not there is a large change in input capacitance when the collector voltage _VCE is increased is taken as an example. However, as long as it is based on the relationship between the magnitude of the input capacitance and the magnitude of the collector voltage _VCE , the floating test can be performed by another method.

For example, as in the second embodiment, the distance W0 in the direction perpendicular to the PN junction surface 3c from the PN junction surface 3c to the trench bottom 5a is calculated from the magnitude of the collector voltage _VCE when the input capacitance changes. It is also possible to calculate and perform a floating inspection from the positive and negative of the distance W0.

Further, for example, the floating inspection can be performed from the absolute value of the input capacitance when the collector voltage V _CE is a predetermined magnitude.

As can be seen from FIG. 5, when the collector voltage V _CE is in the range of 0 to 40 V, in the abnormal structure, the capacitance of the gate insulating films 6a and 6b located on both sides of the trench 5 is measured. Is larger than the input capacity of normal products. On the other hand, when the collector voltage V _CE is 100 V or more, the abnormal structure has a larger distance between the trench bottom 5a and the PN junction surface 3c than the normal structure, and the gate insulating film 6a on one region side is short. This is because the input capacity of the abnormal product is smaller than the input capacity of the normal product.

Accordingly, the floating inspection can be performed by measuring the input capacitance when the collector voltage V _CE is in the range of 0 to 40 V or 100 V or more and determining whether or not the measurement result is within the appropriate range. Note that the appropriate range is the size range of the input capacitance when the collector voltage V _CE is normal structure when the range of more than 0~40V or 100 V.

(3) In each of the above-described embodiments, the case where the input capacitance (C _GE + C _GC ) of the IGBT is measured has been described as an example. However, only the capacitance C _GE between the emitter and the gate can be measured. As described above, in the case of the abnormal structure, when the capacitance _CGC between the emitter and the gate is measured while changing the collector voltage _VCE , a large capacitance change occurs.

(4) In the above-described embodiments, the case where the magnitude of the collector voltage V _CE is changed in the range of several V to several hundred V has been described as an example. In contrast, the range for changing the collector voltage V _CE, when the abnormal structure, as long as the voltage across the depletion layer 21 is assumed to reach the bottom of the trench 5a, N ^- -type drift layer 2, P-type Any change can be made according to various conditions such as the impurity concentration of the base region 3.

  (5) In each of the above-described embodiments, the P-type base region 3 has been described as an example of the second semiconductor layer, but other regions may be used as the second semiconductor layer. That is, the present invention can be applied as an evaluation method for a trench formed in a region different from the P-type base region 3 in a thinned-out trench gate type IGBT. In addition, IGBTs whose conductivity types are all opposite to the IGBTs of the above-described embodiments can be evaluated.

  Further, in each of the above-described embodiments, the case where the trench gate type IGBT having a thinned-out structure is an evaluation target has been described as an example. However, the present invention is not limited to this, and other semiconductor devices such as a MOS can also be the evaluation target.

  In this case, the structure of the semiconductor device may have at least the following configuration. That is, two first semiconductor layers and second semiconductor layers having different conductivity types are joined, a trench is formed so as to extend from the surface of the second semiconductor layer toward the first semiconductor layer, The first electrode is formed through an insulating film inside, one of the regions facing each other across the trench is electrically connected to the second electrode, and the other region is It is not electrically connected to the second electrode, or the other region is electrically connected only via one region connected below the trench, and the first semiconductor layer is It is electrically connected to the three electrodes.

It is a figure which shows the planar layout of IGBT used as evaluation object in 1st Embodiment of this invention. It is a figure which shows the normal structure in IGBT in FIG. It is a figure which shows the abnormal structure in IGBT in FIG. It is a measurement circuit diagram for measuring the input capacitance of IGBT. The IGBT of normal structure and abnormal structures is a diagram showing a measurement result of the input capacitance when ranging collector voltage _{V CE} is 0～300V. It is a conceptual diagram of the measurement situation of the input capacitance when the IGBT has a normal structure, (a) shows when the collector voltage V _CE is 0 V, and (b) shows when the collector voltage V _CE is several hundred V. It is a conceptual diagram of the measurement situation of the input capacitance when the IGBT has an abnormal structure, (a) shows when the collector voltage V _CE is 0 V, and (b) shows when the collector voltage V _CE is several hundreds V. It is a figure which shows the example of the abnormal structure in IGBT in FIG. It is a figure which shows the example of the abnormal structure in IGBT in FIG. It is a fragmentary perspective view of IGBT for demonstrating the evaluation method in 2nd Embodiment of this invention. It is sectional drawing of the trench gate type IGBT of a thinning structure.

Explanation of symbols

DESCRIPTION OF ^SYMBOLS 1 ... P ⁺ type | mold board | substrate, 2 ... N ^- type drift layer, 3 ... P type base area | region,
3a ... one of the two regions divided by the trench 5 in the P-type base region 3,
3b ... P-type base region 3 and the other of the two regions divided by trench 5;
3c ... PN junction surface, 4 ... N ⁺ type emitter region,
5 ... trench, 5a ... trench bottom,
6 ... Gate insulating film,
6a: a gate insulating film on one region side, 6b: a gate insulating film on the other region side,
7 ... Gate electrode, 8 ... Emitter electrode,
9 ... Collector electrode, 10 ... P-type body region,
21 ... depletion layer.

Claims (2)

A first conductivity type first semiconductor layer (2);
A second semiconductor layer (3) of a second conductivity type disposed on the surface of the first semiconductor layer (2);
Is formed on the second semiconductor layer (3), and said second semiconductor layer (3) from the surface having a depth that reaches the first semiconductor layer (2) of the trench (5),
An insulating film (6) formed on the inner wall of the trench (5);
A first electrode (7) formed in the trench (5) and on the insulating film (6);
The second semiconductor layer (3) is electrically divided into two regions (3a, 3b) by the trench (5), and one region (3a) of the two regions (3a, 3b). A second electrode (8) that is electrically connected to the other region (3b) of the two regions (3a, 3b);
PN junction of the first semiconductor layer (2) and the second semiconductor layer (3) performed on a semiconductor device including a third electrode (9) electrically connected to the first semiconductor layer (2). A method for evaluating a positional relationship between a surface (3c) and a bottom (5a) of the trench (5),
A plurality of capacitances of the insulating film (6) between the first electrode (7) and the second electrode (8) are measured with different voltages applied to the third electrode (9). And
The amount of change between the measurement results is the capacitance of both the portion (6a) in contact with the one region (3a) and the portion (3b) in contact with the other region (3b) of the insulating film (6), It is determined whether or not the size corresponds to the difference from the capacity of only the portion (6a) in contact with the one region (3a),
From the determination result, the electrical connection state with the second electrode (8) in the other region (3b) is evaluated, and the positional relationship between the PN junction surface of the semiconductor device and the bottom of the trench is characterized. Evaluation methods. A first conductivity type first semiconductor layer (2);
A second semiconductor layer (3) of a second conductivity type disposed on the surface of the first semiconductor layer (2);
A trench formed in the second semiconductor layer (3), extending from the surface of the second semiconductor layer (3) toward the first semiconductor layer, and shallower than the second semiconductor layer (3) ( 5) and
An insulating film (6) formed on the inner wall of the trench (5);
A first electrode (7) formed in the trench (5) and on the insulating film (6);
Electrically connected to one region (3a) of two regions (3a, 3b) disposed opposite to each other across the trench (5) in the second semiconductor layer (3); and It is electrically connected to the other region (3b) of the two regions (3a, 3b) only through the one region (3a) coupled to the lower side of the trench (5). A second electrode (8);
PN junction of the first semiconductor layer (2) and the second semiconductor layer (3) performed on a semiconductor device including a third electrode (9) electrically connected to the first semiconductor layer (2). A method for evaluating a positional relationship between a surface (3c) and a bottom (5a) of the trench (5),
While applying a voltage to the different sizes and the third electrode (9), the capacitance of the insulating film (6) between the first electrode (7) and the second electrode (8), a plurality Measurement And
The depletion layer (21) generated in the vicinity of the junction surface (3c) reaches the bottom (5a) of the trench (5), so that the measurement capacitance is the one region (3a) of the insulating film (6). ) When changing from the capacitance of both the portion (6a) in contact with the second region (3b) and the portion (3b) in contact with the other region (3b) to the capacitance of only the portion (6a) in contact with the one region (3a) Based on the magnitude of the voltage applied to the third electrode (9), the distance in the direction perpendicular to the PN junction surface (3c) from the PN junction surface (3c) to the bottom (5a) of the trench (5) The method for evaluating the positional relationship between the PN junction surface of the semiconductor device and the bottom of the trench is characterized in that:

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