JP6164099B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a trench having a portion having a width wider than an opening on the bottom side of the opening.

  Conventionally, as a semiconductor device in which this type of trench is formed, a semiconductor device including a trench gate type insulated gate bipolar transistor (hereinafter simply referred to as IGBT) has been proposed (see, for example, Patent Document 1).

Specifically, in this semiconductor device, an N ⁻ type drift layer is formed on the collector layer, and a P type base layer is formed on the surface layer portion of the drift layer. An N ⁺ -type emitter layer is formed on the surface layer of the base layer. In addition, a plurality of trenches that extend through the base layer and the emitter layer and reach the drift layer are extended in a predetermined direction. The plurality of trenches have a so-called ridge shape having a portion that is wider on the bottom side than the opening and wider than the opening. That is, the interval between adjacent trenches has a portion that is narrower than the opening on the bottom side. In addition, the width in the trench is, in other words, the interval between the opposing side walls in the trench.

  A gate insulating film and a gate electrode are sequentially formed on the wall surface of each trench. An emitter electrode electrically connected to the base layer and the emitter layer is formed on the base layer and the emitter layer, and a collector electrode electrically connected to the collector layer is provided on the back surface of the collector layer. Yes.

  In such a semiconductor device, the holes flowing into the drift layer pass between the adjacent trenches and pass through the base layer as compared to the case where the interval between adjacent trenches is constant at the opening side interval. And it is possible to accumulate many holes in the drift layer. Thereby, the supply amount of electrons injected into the drift layer can be increased, and the on-voltage can be reduced.

  The semiconductor device is manufactured as follows. First, a semiconductor substrate in which a buffer layer, a drift layer, and a base layer are sequentially formed on a collector layer is prepared. Subsequently, anisotropic etching such as reactive ion etching (hereinafter simply referred to as RIE) is performed to form a first trench in the base layer.

  Then, anisotropic etching such as RIE is performed again on the bottom surface of the first trench to form a second trench communicating with the first trench. Next, isotropic etching is performed on the second trench. Thereby, the bowl-shaped trench which has a part whose width | variety is wider than an opening part in the bottom part side rather than an opening part is comprised by the 1st, 2nd trench. Thereafter, the semiconductor device is manufactured by appropriately forming a gate insulating film, a gate electrode, and the like.

JP 2012-80074 A

  In such a semiconductor device, since the width of the narrowest portion of the interval between adjacent trenches greatly affects the characteristics (ON voltage) of the semiconductor device, it is preferable to grasp the width of this portion. However, in the trench having a portion wider than the opening on the bottom side of the opening, the shape of the trench cannot be observed from the surface of the semiconductor substrate (the opening side of the trench). That is, it is impossible to grasp the width of the narrowest portion of the interval between adjacent trenches from the surface of the semiconductor substrate.

  Note that such a problem is not a problem that occurs only in the semiconductor device in which the IGBT having the ridge-shaped trench is formed. That is, the same occurs in a semiconductor device in which a trench having a width wider than the opening is formed on the bottom side of the opening.

  An object of the present invention is to provide a semiconductor device manufacturing method capable of grasping the width of the narrowest portion of the interval between adjacent trenches.

In order to achieve the above object, according to the first aspect of the present invention, a semiconductor substrate (1), a plurality of element trenches (4) formed in the semiconductor substrate, and an electrode (6) embedded in the element trenches are provided. And the plurality of element trenches have a shape having a width wider than the opening on the bottom side of the opening, and the interval between adjacent element trenches is on the opening side on the bottom side. The method for manufacturing a semiconductor device having a narrower portion is characterized by the following points.

That is, a step of preparing a semiconductor wafer (20) having an element region (21a) and a test region (21b), and simultaneously forming a plurality of element trenches in the element region of the semiconductor wafer, In the step of forming a plurality of test trenches (31 to 35) and the step of embedding an electrode in the device trench and the test trench, and forming the test trench, the opening of the adjacent test trench After the step of embedding the electrodes after the step of embedding the electrodes, the intervals on the sides are made different from each other, and a part of the intervals is made narrower than the interval on the opening side of the adjacent element trench. Adjacent the electrically connected electrode is embedded by testing whether the embedded electrode is electrically connected Of the adjacent element trenches based on the distance on the opening side of the test trench and the distance on the opening side of the adjacent test trench in which the electrode that is not electrically connected is embedded. It is characterized by estimating the width of the narrowest part of the.

  In this way, by forming a test trench in the test region, embedding an electrode in the test trench, and inspecting whether the electrode embedded in the adjacent test trench is electrically connected, The width of the narrowest portion of adjacent element trenches can be estimated.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the semiconductor device in 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 3 is a schematic plan view after performing the step of FIG. FIG. 5 is a schematic plan view after performing the step of FIG. It is a plane schematic diagram of the test area in the second embodiment of the present invention. It is a plane schematic diagram of the area for a test in the modification of a 2nd embodiment of the present invention. It is a plane schematic diagram of the test area in the third embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. First, the structure of a semiconductor device manufactured by applying the semiconductor device manufacturing method of the present invention will be described. In the present embodiment, a semiconductor device in which an IGBT is formed will be described as an example.

As shown in FIG. 1, the semiconductor device includes a semiconductor substrate 1 having an N ⁻ type drift layer 2. A P-type base layer 3 is formed on the surface side (surface layer portion) of the drift layer 2. Also, a plurality of element trenches 4 formed along the normal direction to the main surface 1a of the semiconductor substrate 1 and reaching the drift layer 2 through the base layer 3 are striped in a predetermined direction (perpendicular to the paper surface in FIG. 1). It is extended in the shape.

  Each element trench 4 communicates with the first element trench 4a formed in the base layer 3 and the first element trench 4a, and from the vicinity of the interface between the base layer 3 and the drift layer 2 to the drift layer 2. The second element trench 4b is formed. Specifically, the first element trench 4 a has a rectangular cross section formed along the normal direction to the main surface 1 a of the semiconductor substrate 1. That is, the first element trench 4a has a constant width. Further, the second element trench 4b has a substantially elliptical shape having a portion whose width is wider than the width of the first element trench 4a in the cross section in FIG. That is, the element trench 4 has a so-called bowl shape in the cross section in FIG.

  The width of the element trench 4 is, in other words, the distance between the opposing side walls in the element trench 4 (the width in the left-right direction in FIG. 1). In addition, the second element trench 4b of the present embodiment has an elliptical shape in which the width of the center portion is widest in the depth direction (the direction perpendicular to the main surface 1a of the semiconductor substrate 1).

  In the adjacent element trenches 4, the interval between the narrowest portions of the adjacent second element trenches 4 b (A in FIG. 1) is the interval between the adjacent first element trenches 4 a (B in FIG. 1). It is narrower. In the present embodiment, since the width of the center portion in the depth direction of the second element trench 4b is the largest, the interval between the narrowest portions of the adjacent second element trenches 4b is adjacent to the second element trench 4b. This is the distance between the center portions of the second element trenches 4b in the depth direction.

  A gate insulating film 5 made of a thermal oxide film or the like is formed on the sidewall of each element trench 4, and a gate electrode 6 made of a conductive material such as doped Poly-Si is formed on the gate insulating film 5. Has been.

An N ⁺ -type emitter layer 7 is formed on the side portion of the first element trench 4 a in the surface layer portion of the base layer 3. Further, in the surface layer portion of the base layer 3, it is between the adjacent first element trenches 4 a, opposite to the first element trench 4 a across the emitter layer 7, and adjacent to the second element trenches. A P ⁺ -type contact layer 8 having a higher concentration than the base layer 3 is formed in a portion facing the drift layer 2 located between 4b. In other words, the contact layer 8 is formed immediately above the drift layer 2 located between the second element trenches 4 b in the surface layer portion of the base layer 3. In this embodiment, the contact layer 8 is formed to a position deeper than the emitter layer 7.

  On the main surface 1a of the semiconductor substrate 1, an interlayer insulating film 9 and an emitter electrode 10 are formed. The emitter electrode 10 is electrically connected to the emitter layer 7 and the contact layer 8 through a contact hole 9 a formed in the interlayer insulating film 9.

A collector layer 11 is formed on the back side of the drift layer 2 (opposite to the main surface 1 a side of the semiconductor substrate 1) and is electrically connected to the collector layer 11 on the collector layer 11. A collector electrode 12 is formed. An N ⁺ type buffer layer 13 is formed between the drift layer 2 and the collector layer 11. The buffer layer 13 is not necessarily required, but is provided for improving the breakdown voltage and steady loss performance by preventing the depletion layer from spreading.

  The above is the configuration of the semiconductor device of this embodiment. Next, the operation of such a semiconductor device will be briefly described.

  In the semiconductor device, when a predetermined voltage is applied to the gate electrode 6, an N-type inversion layer is formed in a portion of the base layer 3 in contact with the element trench 4. Then, electrons are supplied from the emitter layer 7 to the drift layer 2 through the inversion layer, and holes are supplied from the collector layer 11 to the drift layer 2, and the resistance value of the drift layer 2 decreases due to conductivity modulation and is turned on. It becomes a state.

  At this time, the interval between the narrowest portions of the adjacent second element trenches 4b (A in FIG. 1) is made narrower than the interval between the adjacent first element trenches 4a (B in FIG. 1). For this reason, the holes supplied to the drift layer 2 are formed in the base layer as compared with the case where the interval between the adjacent element trenches 4 is constant at the interval between the adjacent first element trenches 4a (B in FIG. 1). It becomes difficult to escape through 3. Accordingly, a large amount of holes can be accumulated in the drift layer 2, thereby increasing the total amount of electrons supplied to the drift layer 2, thereby reducing the on-resistance.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS.

  First, as shown in FIG. 2A, a semiconductor wafer 20 having a collector region 11, a buffer layer 13, a drift layer 2, and a base layer 3 formed in this order and having an element region 21a and a test region 21b is prepared. .

  The element region 21a is a region where the IGBT shown in FIG. 1 is formed. The test region 21b is a region in which test trenches 31 to 35 for estimating the shape of the device trench 4 formed in the device region 21a are formed. In the present embodiment, the semiconductor wafer 20 is formed. A dicing line or the like used when dividing the chip into chips is used.

  Then, an etching mask 14 composed of a silicon oxide film or the like is formed on the main surface 20a (on the base layer 3) of the semiconductor wafer 20 by a chemical vapor deposition (hereinafter simply referred to as CVD) method or the like, and then the etching is performed. The mask 14 is patterned.

  Subsequently, as shown in FIGS. 2B and 5, anisotropic etching such as RIE is performed using the etching mask 14. As a result, the first element trench 4a constituting the opening side portion of the element trench 4 is formed in the element region 21a. In addition, first test trenches 31a to 35a constituting the opening side portions of the test trenches 31 to 35 are formed in the test region 21b. Thereafter, if necessary, a step of removing damage to the wall surfaces of the formed first element trenches 4a and first test trenches 31a to 35a by chemical dry etching (CDE) or the like is performed.

  Here, the shape of the first test trenches 31a to 35a (test trenches 31 to 35) of the present embodiment will be described. The first test trenches 31a to 35a have the same opening width as that of the first element trench 4a. The first test trenches 31a to 35a are formed in the same process as the first element trench 4a, and thus have the same cross-sectional shape.

  The first test trenches 31a to 35a are extended in the same direction as the first element trench 4a. Further, the first test trenches 31a to 35a have the same width in the extending direction (longitudinal direction), but are formed so that the end portions in the longitudinal direction protrude alternately in the planar shape.

  The adjacent first test trenches 31a to 35a are formed so as to have different intervals. Specifically, the interval between the adjacent first test trench 31a and the first test trench 32a is a, and the interval between the adjacent first test trench 32a and the first test trench 33a is b. ing. Further, the distance between the adjacent first test trench 33a and the first test trench 34a is c, and the distance between the adjacent first test trench 34a and the first test trench 35a is d.

  In the present embodiment, the distances a to d between the adjacent first test trenches 31 a to 35 a are gradually increased from the element region 21 a side (the left side of FIG. 2B and the left side of FIG. 5). In the present embodiment, the distance c between the adjacent first test trenches 33 a and the first test trench 34 a is equal to the distance B on the opening side of the adjacent element trench 4.

  Next, as shown in FIG. 2C, the insulating film 5a constituting a part of the gate insulating film 5 is formed by thermal oxidation on the wall surfaces of the first element trench 4a and the first test trenches 31a to 35a. To do. In this embodiment, the insulating film 5a is a thermal oxide film formed by thermal oxidation, but may be an oxide film formed by a CVD method or the like, for example.

  Thereafter, as shown in FIG. 3A, in the step of FIG. 4A described later, the wall surfaces of the first element trench 4a and the first test trenches 31a to 35a are suppressed from being thermally oxidized. An oxygen-impermeable protective film 15 is formed. In the present embodiment, a SiN film or the like is formed by a CVD method so as to cover the wall surfaces of the first element trench 4a and the first test trenches 31a to 35a. That is, after the process of FIG. 3A is completed, the insulating film 5a and the protective film 15 are sequentially laminated on the wall surfaces of the first element trench 4a and the first test trenches 31a to 35a.

  Subsequently, as shown in FIG. 3B, anisotropic etching such as RIE is performed. Thus, the protective film 15 and the insulating film 5a disposed on the bottom surface are selectively removed while leaving the protective film 15 disposed on the side wall of the first element trench 4a and the first test trenches 31a to 35a. To do.

  Thereafter, anisotropic etching such as RIE is performed again on the bottom surface of the first element trench 4a using the protective film 15 as an etching mask, thereby reaching the drift layer 2 in communication with the first element trench 4a. A two-element trench 4b is formed. Similarly, anisotropic etching such as RIE is performed again on the bottom surfaces of the first test trenches 31a to 35a using the protective film 15 as an etching mask, thereby drifting in communication with the first test trenches 31a to 35a. Second test trenches 31b to 35b reaching layer 2 are formed.

  Since the second test trenches 31b to 35b are formed in the same process as the second element trench 4b, they have the same cross-sectional shape. 3B, anisotropic etching is performed using the protective film 15 disposed on the wall surfaces of the first element trench 4a and the second test trenches 31b to 35b as an etching mask. Therefore, after this step, the width of the second element trench 4b and the second test trenches 31b to 35b are still narrower than the width of the first element trench 4a.

  Next, as shown in FIG. 3C, the second element trench 4b and the second test trenches 31b to 35b are isotropically etched using the protective film 15 as an etching mask. As a result, in the element region 21a, the width of the central portion of the second element trench 4b is wider than the width of the first element trench 4a, and the bowl-shaped element trench 4 is formed.

  On the other hand, in the test region 21b, as described above, the intervals between the adjacent first test trenches 31a to 35a are different from each other. Specifically, the interval a between the adjacent first test trench 31a and the first test trench 32a and the interval b between the adjacent first test trench 32a and the first test trench 33a are for adjacent elements. It is narrower than the interval B on the opening side of the trench 4.

  For this reason, when the second test trenches 31b to 35b are isotropically etched, the second test trenches may communicate with each other. FIG. 3C illustrates a case where the second test trench 31b and the second test trench 32b and the second test trench 32b and the second test trench 33b communicate with each other.

  Here, the present embodiment is characterized in that part of the adjacent first test trenches 31a to 35a is intentionally communicated. That is, in the process of FIG. 2B, when performing the process of FIG. 3C, a part of the adjacent test trenches 31 to 35 (second test trenches 31b to 35b) communicates. The interval between the first test trenches 31a to 35a is determined.

  Subsequently, as shown in FIG. 4A, the insulation on the wall surface of the second element trench 4b and the second test trenches 31b to 35b is thicker than the insulating film 5a formed on the wall surface of the first element trench 4a. A film 5b is formed. In the present embodiment, an oxygen-impermeable protective film 15 is disposed in the first element trench 4a and the second test trenches 31b to 35b, and a thermal oxide film is formed on the wall surface of the first element trench 4a. Not formed. For this reason, for example, by performing wet oxidation by appropriately adjusting the heating time at 1150 ° C., the insulating film 5b thicker than the insulating film 5a is formed. Thus, the gate insulating film 5 is formed by the insulating film 5a formed in the first element trench 4a and the insulating film 5b formed in the second element trench 4b.

  Next, as shown in FIG. 4B, the protective film 15 is removed. After that, as shown in FIG. 4C, a conventional general semiconductor device manufacturing process is performed to embed a conductive material such as doped Poly-Si constituting the gate electrode 7, or to form an emitter layer 7 and a contact. A layer 8, an interlayer insulating film 9, an emitter electrode 10, and a collector electrode 12 are formed.

  In FIG. 4C, the emitter layer 7 and the contact layer 8 are omitted. Further, at least the gate electrode 7 may be formed in the test region 21b.

  In the test region 21b, as shown in FIG. 6, electrodes 41 to 45 electrically connected to the gate electrode 6 embedded in the test trenches 31 to 35 are formed. In the present embodiment, since the test trenches 31 to 35 are formed so that the end portions in the longitudinal direction protrude alternately in the planar shape, the electrodes 41 to 45 are formed at the end portions on the protruding side, respectively. To do. Thus, the freedom degree at the time of forming the electrodes 41-45 can be improved by forming so that the edge part of the test trenches 31-35 may protrude alternately.

  Subsequently, by inspecting whether the gate electrodes 6 embedded in the test trenches 31 to 35 are electrically connected to each other, the interval between the narrowest portions of the adjacent element trenches 4 is estimated. To do.

  In the present embodiment, as shown in FIG. 4C, the adjacent test trench 31 and the test trench 32, and the adjacent test trench 32 and the test trench 33 communicate with each other. Therefore, the electrode 41 and the electrode 42 are electrically connected through the gate electrode 6 embedded in the test trenches 31 and 32, and the electrode 42 and the electrode 42 are connected through the gate electrode 6 embedded in the test trenches 32 and 33. The electrode 43 is electrically connected.

  On the other hand, the adjacent test trench 33 and the test trench 34 and the adjacent test trench 34 and the test trench 35 are not in communication with each other. For this reason, the electrode 43 and the electrode 44 and the electrode 44 and the electrode 45 are not electrically connected.

  Here, in this embodiment, before performing the manufacturing process of the semiconductor device, the test trenches 31 to 35 adjacent to each other are intentionally communicated, and then the semiconductor device is cleaved so that the element trench 4 is exposed. The width of the narrowest portion of the adjacent element trenches 4 is investigated. This is because the shape (etching state) of the trench changes even if a trench formation step (etching step) is performed on the same wafer due to the density of the trench to be formed.

  Specifically, when the electrodes 41 and 42 are electrically connected, when the electrodes 42 and 43 are electrically connected, when the electrodes 43 and 44 are electrically connected, the electrodes 44 and 45 are electrically connected. In the case of connection, the width of the narrowest portion of each adjacent element trench 4 is examined. That is, the width of the narrowest portion of the adjacent element trenches 4 when the electrodes 41 to 45 are electrically connected with respect to the intervals a to d on the opening side of the adjacent test trenches 31 to 35. Is investigating.

  Note that this investigation step need only be performed once before performing the semiconductor device. That is, the distances a to d on the opening side of the adjacent test trenches 31 to 35 and the narrowest portion of the adjacent element trenches 4 when the electrodes 41 to 45 are electrically connected. You don't need to do this once you know the relationship with width.

  In the present embodiment, the electrode 42 and the electrode 43 are electrically connected, and the electrode 43 and the electrode 44 are not electrically connected. For this reason, the width of the narrowest portion of the interval between the adjacent element trenches 4 is based on the result of the investigation in advance, and the interval between the adjacent element trenches 4 when the adjacent test trenches 32 and 33 communicate with each other. Between the width of the narrowest portion and the width of the narrowest portion of the interval between the adjacent element trenches 4 when the adjacent test trenches 33 and 34 communicate with each other. it can.

  As described above, in this embodiment, whether or not the test trenches 31 to 35 are formed in the test region 21b and the gate electrode 6 embedded in the test trenches 31 to 35 is electrically connected is determined. By examining the above, it is possible to estimate the width of the narrowest portion of the interval between the adjacent element trenches 4.

  In the present embodiment, the adjacent test trenches 31 to 35 are intentionally communicated, and then the semiconductor device is cleaved so that the element trench 4 is exposed. The width of the narrowed part is being investigated. For this reason, after investigating the interval between the adjacent test trenches 31 to 35 and the interval between the adjacent element trenches 4, the interval between the adjacent element trenches 4 can be obtained without cleaving the semiconductor device in each manufacturing process. The width of the narrowest portion can be estimated, and the manufacturing process can be greatly simplified.

  That is, the following may be considered in order to grasp the width of the narrowest portion of the interval between the adjacent element trenches 4. That is, first, after manufacturing a plurality of semiconductor devices, one of the semiconductor devices is cleaved so that the element trenches 4 are exposed. Then, the width of the narrowest portion of the interval between the adjacent element trenches 4 is measured by observing a cross section of the cleaved semiconductor device, and the adjacent element trenches 4 in other semiconductor devices are measured based on the measurement result. A method of estimating the width of the narrowest part of the interval is also conceivable.

  However, in such a method, each time a semiconductor device is manufactured, a semiconductor device (semiconductor wafer) dedicated to cleavage for measurement (estimation) must be prepared, which increases the number of manufacturing steps. On the other hand, in this embodiment, after investigating the interval between the adjacent test trenches 31 to 35 and the interval between the adjacent element trenches 4, the adjacent elements can be formed without cleaving the semiconductor device in each manufacturing process. The width of the narrowest portion of the interval between the trenches 4 can be estimated. For this reason, the manufacturing process can be greatly simplified.

  In this embodiment, the example in which the test trenches 31 to 35 are formed in the test region 21b has been described. However, more test trenches having different intervals on the opening side may be formed.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the shape of the test trenches 31 to 35 formed in the test region 21b is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment. Is omitted.

  In the present embodiment, as shown in FIG. 7, the test trench 31 is extended in a direction orthogonal to the extension direction of the element trench 4. The test trenches 32 to 35 are extended in the same direction as the element trench 4. Then, the widths between the opening of the test trench 31 and the openings of the test trenches 32 to 35 are made different from each other. That is, in the present embodiment, the width between the opening of the test trench 31 and the openings of the test trenches 32 to 35 corresponds to the interval between the openings of adjacent test trenches of the present invention. .

  In the present embodiment, the distance between adjacent test trenches 31 and test trenches 32 is a, and the distance between adjacent test trenches 31 and test trenches 33 is b. An interval between the adjacent test trench 31 and the test trench 34 is c, and an interval between the adjacent test trench 31 and the test trench 35 is d. FIG. 7 is a schematic plan view of the test region 21b after the step of FIG.

  According to this, when inspecting whether the gate electrodes 6 embedded in the test trenches 31 to 35 are electrically connected to each other, the continuity between the electrode 41 and any of the electrodes 42 to 45 is inspected. do it. That is, the electrode 41 can be a common electrode. Therefore, the inspection process can be simplified.

(Modification of the second embodiment)
When the electrode 41 is used as a common electrode in the inspection step as in the second embodiment, test trenches 31 to 35 may be formed as shown in FIG. That is, the test trench 31 is formed in an annular shape. Further, the test trenches 32 to 35 are formed in the circumferential direction along the ring. Then, the widths between the opening of the test trench 31 and the openings of the test trenches 32 to 35 are made different from each other. In other words, in this case, the width between the opening of the test trench 31 and the openings of the test trenches 32 to 35 corresponds to the distance between the adjacent test trench openings of the present invention.

  Even in this case, since the electrode 41 electrically connected to the gate electrode 6 embedded in the annular test trench 31 can be a common electrode, the same effect as the second embodiment can be obtained. it can.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the shape of the test trenches 31 to 34 formed in the test region 21b is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment. Is omitted.

  In the present embodiment, as shown in FIG. 9, a pair of test trenches 31 to 34 that are separated by a predetermined interval are formed. And the width | variety between the opening parts in each pair of the test trenches 31-34 is varied. That is, in the present embodiment, the width between the openings of the pair of test trenches 31 to 34 corresponds to the interval between the openings of adjacent test trenches of the present invention.

  When the test trenches 31 to 34 are formed in this way, the gate electrodes 6 are electrically connected to each other by determining whether or not each pair of electrodes 41 to 44 is electrically connected. Inspect whether or not

  In the present embodiment, the distance between the pair of test trenches 31 is a, and the distance between the pair of test trenches 32 is b. The distance between the pair of test trenches 33 is c, and the distance between the pair of test trenches 34 is d. FIG. 9 is a schematic plan view of the test region 21b after the step of FIG. 4C.

  Even if such test trenches 31 to 34 are formed, the same effect as in the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above embodiments, the semiconductor device in which the IGBT is formed is taken as an example, but the present invention can be applied to a semiconductor device that does not have the collector layer 11. In each of the above embodiments, the test region 21b may be incorporated in the element region 21a. That is, when the semiconductor wafer 20 is divided into chips, the test area 21b may remain in the chip.

  Further, the present invention is not limited to the method of manufacturing the semiconductor device having the above-described eaves-shaped element trench 4, and a trench having a width wider than the width of the opening is formed on the bottom side of the opening. The present invention can be applied to a method for manufacturing a semiconductor device. For example, the present invention can be applied to a method of manufacturing a semiconductor device having a tapered trench having a bottom surface wider than an opening.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 4 Element trench 6 Electrode 20 Semiconductor wafer 21a Element area 21b Test area 31-35 Test trench

Claims (5)

A semiconductor substrate (1);
A plurality of device trenches (4) formed in the semiconductor substrate;
An electrode (6) embedded in the element trench,
The plurality of element trenches have a shape having a portion that is wider than the opening on the bottom side of the opening,
In the method for manufacturing a semiconductor device, the interval between the adjacent element trenches is such that the bottom side has a portion narrower than the opening side .
Preparing a semiconductor wafer (20) having an element region (21a) and a test region (21b);
Forming the plurality of device trenches in the device region of the semiconductor wafer and simultaneously forming the plurality of test trenches (31 to 35) in the test region;
Embedding the electrode in the element trench and the test trench,
In the step of forming the test trench, the interval on the opening side of the adjacent test trench is made different from each other, and a part of the interval is narrower than the interval on the opening side of the adjacent element trench. And
After the step of embedding the electrode, in the test region, the electrode embedded in the adjacent test trench is inspected to determine whether or not the electrode is electrically connected. Based on the distance between the adjacent test trench openings where the electrodes are embedded and the distance between the adjacent test trench openings where the electrodes that are not electrically connected are embedded A method of manufacturing a semiconductor device, wherein the width of the narrowest portion of the interval between adjacent element trenches is estimated.   In the step of forming the test trench, the plurality of test trenches are extended in a predetermined direction, and the width of the opening side between the adjacent test trenches in a direction orthogonal to the predetermined direction is adjacent to the test trench. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the distance is on the opening side of the trench for use.   In the step of forming the test trench, one of the test trenches is extended in a predetermined direction, and the remaining test trenches are extended in a direction perpendicular to the predetermined direction and extended in the predetermined direction. A width between the opening of the test trench provided and the opening of the test trench extended in the orthogonal direction is set as an interval on the opening side of the adjacent test trench. A method for manufacturing a semiconductor device according to claim 1.   In the step of forming the test trench, one of the test trenches is formed in an annular shape, and the remaining test trenches are formed in a circumferential direction along the annular shape, thereby forming the annular shape. The width between the opening of the test trench and the opening of the test trench along the circumferential direction is set as an interval on the opening side of the adjacent test trench. A method for manufacturing a semiconductor device. In the step of forming the test trench, a plurality of pairs of test trenches spaced apart by a predetermined distance are formed, and the widths between the openings of the pair of test trenches are adjacent to each other on the opening side of the test trench The method of manufacturing a semiconductor device according to claim 1, wherein an interval of

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