JP2004140040A - Method for evaluating vertical mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evaluate the embedded depth of the gate electrode of a vertical MOSFET by fabricating the vertical MOSFET becoming an actual product and an evaluation element on the same semiconductor substrate by the same process and then measuring the electrical characteristics of the evaluation element. <P>SOLUTION: In the fabrication process of a vertical MOSFET, an n-type vertical MOSFET becoming an actual product and a p-type lateral MOSFET for evaluation having a gate electrode structure identical to that of the vertical MOSFET are fabricated on the same semiconductor substrate 11 by performing ion implantation for forming the source region 17 of the vertical MOSFET while masking the forming region of the lateral MOSFET. The embedded depth of the gate electrode 16 of the lateral MOSFET is determined by measuring the threshold voltage of the lateral MOSFET for evaluation and then the embedded depth of the gate electrode 16 of the vertical MOSFET is evaluated based on the depth thus determined. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for evaluating a vertical MOSFET having a buried gate electrode, and more particularly to a method for evaluating a buried depth of a buried gate electrode of a vertical MOSFET.
[0002]
[Prior art]
FIG. 4 is a cross-sectional view showing a general configuration of an n-type vertical MOSFET. The vertical MOSFET having the configuration shown in FIG. 4 is manufactured as follows. First, a p-type impurity such as boron is implanted into an n-type epitaxial growth layer 12 on an n-type semiconductor substrate 11 and diffused to form a p-type channel layer 13. Next, the trench 14 is formed by anisotropic dry etching. The bottom of the trench 14 penetrates the p-type channel layer 13 and is buried in the n-type epitaxial growth layer 12.
[0003]
Next, a gate insulating film 15 is formed inside the trench 14, and the inside is further filled with polysilicon to form a gate electrode 16. Next, the substrate surface is covered with an ion implantation mask for forming a source region, and n-type impurities such as arsenic are ion-implanted and diffused to form n-type source regions 17 on both sides of the trench 14. Next, the gate electrode 16 is covered with an interlayer insulating film 18 and a source electrode 19 electrically connected to the n-type source region 17 and the p-type channel layer 13 is formed on the surface of the substrate, resulting in the state shown in FIG. The gate electrode 16 is connected to a metal electrode exposed on the substrate surface in a cross section different from the cross section shown in FIG.
[0004]
In this configuration, the n-type epitaxial growth layer 12 becomes a drain region. Further, although not shown in FIG. 4, a drain electrode and a passivation film are formed. As shown by a broken line in FIG. 4, in a vertical MOSFET having a buried gate electrode 16, a source 21 is provided on a substrate surface, a drain 22 is provided on a trench bottom, and a vertical direction (depth direction) is provided along a trench side wall. Channel 23 is formed.
[0005]
The element characteristics of the vertical MOSFET having the above-described configuration are determined by the burying depth of the gate electrode 16 buried in the p-type channel layer 13 and the n-type epitaxial growth layer 12. Therefore, it is necessary to evaluate the buried depth of the buried gate electrode 16. Conventionally, in this evaluation, a wafer for fabricating a device for evaluation that does not become a product is prepared separately from a wafer for fabricating a vertical MOSFET that becomes an actual product, and the wafer is evaluated using the same process as the actual manufacturing process. (Vertical MOSFET) is manufactured, and the cross-sectional shape of the element is observed by an electron microscope or the like. It should be noted that a method of performing evaluation in the course of an actual manufacturing process without producing an element for evaluation has not been disclosed yet, and the technology has not been established.
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional evaluation method, a wafer that does not become a product is required, and since an element that does not become a product is manufactured on this wafer, there is a problem that the cost is increased. In addition, when observing the cross-sectional shape of the evaluation element, the production of an observation sample and the operation of an electron microscope and the like are performed manually, which causes a problem that the production lead time is increased.
[0007]
The present invention has been made in view of the above problems, and a vertical MOSFET as an actual product and an element for evaluation are manufactured in the same process on the same semiconductor substrate, and the electrical characteristics of the element for evaluation are electrically controlled. It is an object of the present invention to provide a method for evaluating a vertical MOSFET in which the characteristics are measured to evaluate the buried depth of a gate electrode of the vertical MOSFET.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a method for evaluating a vertical MOSFET according to the present invention is an ion forming method for forming a source region of a vertical MOSFET while masking a formation region of a horizontal MOSFET in a vertical MOSFET manufacturing process. By performing the implantation, on the same semiconductor substrate, a second conductive type lateral MOSFET for evaluation having the same gate electrode structure as that of the first conductive type vertical MOSFET as an actual product is manufactured. Then, the threshold voltage of the lateral MOSFET for evaluation is measured, and the burying depth of the gate electrode of the vertical MOSFET is evaluated.
[0009]
According to the present invention, with respect to the lateral MOSFET, when the burying depth of the gate electrode is increased, the channel length is increased and the threshold voltage is increased. Therefore, the threshold voltage of the lateral MOSFET is measured, and By obtaining the buried depth of the gate electrode, the buried depth of the gate electrode of the vertical MOSFET having the same gate electrode structure as the lateral MOSFET can be evaluated.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of a p-type lateral MOSFET for evaluation used in carrying out a method according to the present invention. As shown in FIG. 1, an n-type epitaxial growth layer 12 is stacked on an n-type semiconductor substrate 11, and a p-type channel layer 13 is formed on a surface layer of the n-type epitaxial growth layer 12. The n-type semiconductor substrate 11, the n-type epitaxial growth layer 12, and the p-type channel layer 13 are common to an n-type vertical MOSFET (see FIG. 4) manufactured at a location different from the lateral MOSFET shown in FIG. .
[0011]
The second trench 34 penetrates through the p-type channel layer 13 and reaches the n-type epitaxial growth layer 12. The second trench 34 has the same depth and the same opening width as the trench of the vertical MOSFET (see FIG. 4, reference numeral 14). The gate insulating film 15 is provided inside the second trench 34. The inside of the gate insulating film 15 is filled with polysilicon to be the gate electrode 16. The gate electrode 16 is covered with an interlayer insulating film 18 and is connected to a metal electrode (not shown in the figure) exposed on the substrate surface in a cross section different from the cross section shown in FIG. The gate insulating film 15, the gate electrode 16, and the interlayer insulating film 18 are common to the vertical MOSFET (see FIG. 4).
[0012]
In this lateral MOSFET, in the p-type channel layer 13, one side portion of the second trench 34, a portion indicated by a broken line on the left side in the illustrated example becomes the source 41, and a side portion on the opposite side thereof, the right side in the illustrated example The portion indicated by the broken line is the drain 42. Therefore, the source electrode 39 is formed on the source 41 and the drain electrode 38 is formed on the drain 42 on the substrate surface. The source electrode 39 and the drain electrode 38 are common to the source electrode (see FIG. 4, reference numeral 19) of the vertical MOSFET. Further, the channel 43 is formed in the n-type epitaxial growth layer 12.
[0013]
The horizontal MOSFET having the above-described configuration is manufactured by the same manufacturing process as the vertical MOSFET (see FIG. 4). However, when an n-type impurity such as arsenic is ion-implanted to form an n-type source region (see FIG. 4, reference numeral 17) of the vertical MOSFET, the formation region of the horizontal MOSFET is covered with an ion implantation mask, To prevent the n-type impurity from being ion-implanted into the formation region of. Further, when forming the source electrode (see reference numeral 19 in FIG. 4) of the vertical MOSFET, the source electrode 39 and the drain electrode 38 in the horizontal MOSFET are insulated.
[0014]
FIG. 2 is a characteristic diagram showing the relationship between the channel length of the lateral MOSFET shown in FIG. 1 and the buried depth of the buried gate electrode in the epitaxial growth layer. As shown in FIG. 2, in the lateral MOSFET, when the burying depth of the gate electrode 16 in the n-type epitaxial growth layer 12 increases, the distance along the gate insulating film 15 in the n-type epitaxial growth layer 12 increases. The distance between the source 41 and the drain 42, that is, the channel length becomes longer.
[0015]
FIG. 3 is a characteristic diagram showing the relationship between the threshold voltage and the channel length of the lateral MOSFET shown in FIG. As shown in FIG. 3, in the lateral MOSFET, as the channel length increases, the threshold voltage increases. Therefore, by measuring the threshold voltage of the lateral MOSFET, it is possible to know the burying depth of the gate electrode 16 of the lateral MOSFET in the n-type epitaxial growth layer 12 from the relationship shown in FIGS.
[0016]
Since the gate electrode structure of the lateral MOSFET shown in FIG. 1 is the same as the gate electrode structure of the vertical MOSFET shown in FIG. 4, the burying depth of the gate electrode 16 of the vertical MOSFET in the n-type epitaxial growth layer 12 is reduced. Can be asked for. Therefore, it is possible to evaluate how deeply the gate electrode 16 of the vertical MOSFET is buried in the p-type channel layer 13 and the n-type epitaxial growth layer 12.
[0017]
According to the above-described embodiment, a p-type horizontal MOSFET for evaluation having the same gate electrode structure as the vertical MOSFET is provided on a wafer for producing an n-type vertical MOSFET as an actual product, together with the vertical MOSFET. Can be produced. By measuring the threshold voltage of the lateral MOSFET and obtaining the buried depth of the gate electrode 16 of the lateral MOSFET, the buried depth of the gate electrode 16 of the vertical MOSFET can be evaluated.
[0018]
In the above, the present invention is not limited to the above-described embodiment, but can be variously modified. In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also true.
[0019]
【The invention's effect】
According to the present invention, a second conductive type horizontal MOSFET for evaluation having the same gate electrode structure as the vertical MOSFET is provided on a wafer for manufacturing the first conductive vertical MOSFET as an actual product together with the vertical MOSFET. A MOSFET can be manufactured. Then, by measuring the electrical characteristics of the lateral MOSFET and determining the buried depth of the gate electrode of the lateral MOSFET, the buried depth of the gate electrode of the vertical MOSFET can be evaluated.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a horizontal MOSFET for evaluation used in a method for evaluating a vertical MOSFET according to the present invention.
FIG. 2 is a characteristic diagram showing a relationship between a channel length of the lateral MOSFET shown in FIG. 1 and a buried depth of a buried gate electrode in an epitaxial growth layer.
FIG. 3 is a characteristic diagram showing a relationship between a threshold voltage and a channel length of the lateral MOSFET shown in FIG.
FIG. 4 is a cross-sectional view illustrating a configuration of a vertical MOSFET.
[Explanation of symbols]
Reference Signs List 11 n-type semiconductor substrate 12 n-type epitaxial growth layer 13 p-type channel layer 14 trench 15 gate insulating film 16 gate electrode 17 n-type source region 21, 41 source 22, 42 drain 23, 43 channel 34 second trench

Claims (3)

A first conductivity type epitaxial growth layer on the first conductivity type semiconductor substrate, a second conductivity type channel layer on the epitaxial growth layer, and penetrating the channel layer into the epitaxial growth layer; A gate insulating film inside the trench, a buried gate electrode inside the gate insulating film, a first conductivity type source region on a side of the trench on the surface of the channel layer, the epitaxial growth layer In evaluating the buried depth of the gate electrode of the vertical MOSFET of the first conductivity type having a drain region,
Having the epitaxial growth layer on the semiconductor substrate, having the channel layer on the epitaxial growth layer, having a second trench having the same depth as the trench, and having a gate insulating film inside the second trench Having a buried gate electrode inside the gate insulating film, wherein both side portions of the second trench of the channel layer are a second conductivity type source region and a second conductivity type drain region, respectively; A second conductivity type lateral MOSFET, in which a channel is formed along a contact portion between the gate insulating film and the epitaxial growth layer in the second trench when in the ON state, is manufactured in the same manufacturing process as the vertical MOSFET. A step of fabricating the vertical MOSFET at a location different from the vertical MOSFET;
Measuring the electrical characteristics of the channel of the lateral MOSFET, and evaluating the embedded depth of the gate electrode of the vertical MOSFET based on the measurement result;
A method for evaluating a vertical MOSFET, comprising: The relationship between the threshold voltage of the lateral MOSFET and the channel length of the lateral MOSFET and the relationship between the channel length of the lateral MOSFET and the depth at which the buried gate electrode of the lateral MOSFET is buried in the epitaxial growth layer are obtained in advance. And the process of
The threshold voltage of the lateral MOSFET is measured, the channel length of the lateral MOSFET is determined based on the threshold voltage obtained by the measurement, and the buried gate electrode of the lateral MOSFET is determined based on the determined channel length. Determining a burying depth, and evaluating the burying depth of the gate electrode of the vertical MOSFET based on the obtained burying depth;
The method for evaluating a vertical MOSFET according to claim 1, comprising: When implanting a first conductivity type impurity into the channel layer to form a source region of the vertical MOSFET, mask the formation region of the lateral MOSFET so that the impurity is not implanted into the formation region of the lateral MOSFET. The method for evaluating a vertical MOSFET according to claim 1, wherein the evaluation is performed.

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