CN105744202B - A kind of V BY ONE signal processing methods and device - Google Patents
A kind of V BY ONE signal processing methods and device Download PDFInfo
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- CN105744202B CN105744202B CN201610083873.2A CN201610083873A CN105744202B CN 105744202 B CN105744202 B CN 105744202B CN 201610083873 A CN201610083873 A CN 201610083873A CN 105744202 B CN105744202 B CN 105744202B
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- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 238000013500 data storage Methods 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims description 49
- 238000003860 storage Methods 0.000 claims description 14
- 238000004891 communication Methods 0.000 claims description 4
- 238000010008 shearing Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000001514 detection method Methods 0.000 description 4
- 230000011664 signaling Effects 0.000 description 4
- 241000208340 Araliaceae Species 0.000 description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a kind of V BY ONE signal processing methods and device, this method to include：(1) V BY ONE source images signals are received, the V BY ONE source images signals is parsed and is restored clock and view data；(2) shear treatment is carried out to described image data according to control signal and obtains effective image data, and stored the effective image data and obtain data storage；(3) data storage is read according to output signal refresh rate, and according to the recovered clock is encoded the data storage of reading according to V BY ONE agreements to obtain V BY ONE picture signals.The present invention can carry out shear treatment and cache to V BY ONE source images signal, and use reference clock of the recovered clock as output signal, the V BY ONE source images signals of low refresh rate, low lane numbers can be converted into the V BY ONE picture signals of high refresh rate, high lane numbers, avoid and use external clock line, so as to reduce PCB layout difficulty, the antijamming capability and signal output quality of signal are enhanced.
Description
Technical field
The present invention relates to technical field of image signal processing, and in particular to a kind of V-BY-ONE signal processing methods and dress
Put.
Background technology
With the continuous development of display panel manufacturing technology, the display device of 4K resolution ratio is popularized on a large scale at present,
It is expected that coming years in the market can occur the display module of 8K, 10K ultrahigh resolution successively.These ultrahigh resolution display modules
Signal source can typically use V-BY-ONE signals, because high resolution, image data amount are big, the display module one of 8K resolution ratio
As can use 32lane (data channel) or 64lane V-BY-ONE signals, the display module of 10K resolution ratio can then use
64lane V-BY-ONE signals.
The display module of ultrahigh resolution can all use in links such as research and development, productions has static images point screen function
V-BY-ONE image signal sources its image display quality is detected.In the prior art, the general base of V-BY-ONE image sources
Realized in FPGA architecture, due to the V-BY- of the limitation of fpga chip performance, at present single fpga chip most multipotency output 24lane
ONE signals, thus it is unrealistic using single FPGA chip solution when carrying out screen to ultrahigh resolution display module；Using more
During fpga chip scheme, a fpga chip exports 16lane V-BY-ONE signals, is then exported together by 2 (4)
32lane (64lane) V-BY-ONE signals.For more fpga chip schemes, due to requiring each lane V-BY-ONE signals reference
Clock is homologous, therefore can use an external clock line, and otherwise the anomalies such as film flicker occur in display module.It is and outer
The clock line put can have a strong impact on PCB design, cause to connect up difficulty increasing, while external clock line poor anti jamming capability, meeting
Influence the conveying length and signal quality of cable.
The content of the invention
For above-mentioned the deficiencies in the prior art, the present invention discloses a kind of V-BY-ONE signal processing methods and device, to V-
BY-ONE source images signal carries out shear treatment and cache, and uses reference clock of the recovered clock as output signal,
The V-BY-ONE source images signals of low refresh rate, low lane numbers can be converted into the V-BY-ONE figures of high refresh rate, high lane numbers
As signal, avoid using external clock line, so as to reduce PCB layout difficulty, enhance the antijamming capability and letter of signal
Number output quality.
Technical scheme is used by realizing mesh of the present invention：A kind of V-BY-ONE signal processing methods, this method include：
(1) V-BY-ONE source images signals are received, the V-BY-ONE source images signal is parsed and is restored clock and figure
As data；
(2) according to control signal described image data are carried out with shear treatment and obtains effective image data, and described in storage
Effective image data obtain data storage；
(3) data storage is read according to output signal refresh rate, and according to the recovered clock by the storage of reading
Data are encoded to obtain V-BY-ONE picture signals according to V-BY-ONE agreements.
Preferably, the control signal includes image cut pattern information, source images resolution information.
Preferably, described image shear mode information includes effective image-region shearing instruction.
In addition, the present invention also provides a kind of V-BY-ONE signal processing apparatus, the device include an exterior storage medium with
And it is arranged at V-BY-ONE source images signal transmitting and receivings module, image cut module and V-BY- in a PLD
ONE picture signal output modules；
The V-BY-ONE source images signal transmitting and receiving module is used to receive V-BY-ONE source images signals, and parses the V-
BY-ONE source images signals are restored clock and view data；
Described image shear module is used to obtain effectively figure to described image data progress shear treatment according to control signal
As data；
The exterior storage medium obtains data storage for storing the effective image data；
The V-BY-ONE picture signals output module is used to read the data storage according to output signal refresh rate, and
The data storage of reading encoded according to V-BY-ONE agreements according to the recovered clock to obtain V-BY-ONE picture signals.
Preferably, apparatus of the present invention also include the buffer control module being arranged in the PLD；It is described
The effective image data are write the exterior storage medium by image cut module by the buffer control module；The V-
BY-ONE picture signals output module reads the data storage in the exterior storage medium by the buffer control module.
The present invention has advantages below：
(1) present invention is cached processing to the effective image data of V-BY-ONE source images signals, can be by low brush
New rate, the V-BY-ONE source images signals of low lane numbers are converted into high refresh rate, the V-BY-ONE picture signals of high lane numbers.
(2) signal transacting is carried out parallel using multiple apparatus of the present invention, due to using recovered clock as output signal
Reference clock, the reference clock of each device output signal is homologous, avoids using external clock line, so as to reduce PCB cloth
Line difficulty, enhance the antijamming capability and signal output quality of signal
Brief description of the drawings
Fig. 1 is the structured flowchart of V-BY-ONE signal processing apparatus of the present invention.
Fig. 2 is the Organization Chart that V-BY-ONE signal processing apparatus of the present invention is applied to the detection of high-resolution module.
Fig. 3 is the embodiment that V-BY-ONE signal processing apparatus of the present invention is applied to the detection of 10K modules.
Fig. 4 is the embodiment that V-BY-ONE signal processing apparatus of the present invention is applied to the detection of 8K modules.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
Programmable patrolled as shown in figure 1, a kind of V-BY-ONE signal processing apparatus disclosed by the invention includes being arranged at one
Collect V-BY-ONE source images signal transmitting and receivings module, image cut module, buffer control module and the V-BY-ONE images in device
Signal output module, and an exterior storage medium electrically connected with buffer control module.
In above-described embodiment, V-BY-ONE source images signal transmitting and receivings module is used to receive V-BY-ONE source images signals, and
Parsing V-BY-ONE source images signals are restored clock and view data；Image cut module is used for according to control signal to figure
Effective image data are obtained as data carry out shear treatment；Exterior storage medium obtains storing number for storing effective view data
According to；Buffer control module is used to realize the read-write for carrying out exterior storage medium data；V-BY-ONE picture signal output modules
For according to output signal refresh rate read data storage, and according to recovered clock by the data storage of reading according to V-BY-ONE
Agreement is encoded to obtain V-BY-ONE picture signals.
In above-described embodiment, PLD selects fpga chip；Exterior storage medium selects DDR cache chips；
Control signal is transmitted using low speed communication interfaces such as IIC interfaces or UART interfaces.
In above-described embodiment, control signal includes image cut pattern information, source images resolution information, and wherein image is cut
The pattern of cutting is divided into cross shear pattern or vertical shear pattern.
As shown in Fig. 2 when the V-BY-ONE signal sources detection one using a low resolution, low refresh rate, low lane numbers
During individual high-resolution V-BY-ONE modules, multiple apparatus of the present invention concurrent workings can be used to form a detecting system.For
It is easy to that the present invention is described further, hereafter apparatus of the present invention is referred to as V-BY-ONE signal processing apparatus.
10K modules detect embodiment：
As shown in figure 3, it for the V-BY-ONE signal sources of 5120x2160,4lane signaling interface is one to use a resolution ratio
Individual resolution ratio provides image sensing signal for the V-BY-ONE modules of 10240x4320,64lane signaling interface, can use 4
The concurrent working of V-BY-ONE signal processing apparatus is handled V-BY-ONE picture signals.
In above-described embodiment, V-BY-ONE signal sources are that 4 V-BY-ONE signal processing apparatus are assigned with 4lane's respectively
V-BY-ONE source images signals, and be that 4 V-BY-ONE signal processing apparatus are assigned with control signal respectively with IIC interfaces.V-
On BY-ONE signal processing apparatus after electricity, V-BY-ONE signal sources are according to the module information of V-BY-ONE modules respectively to 4 V-
BY-ONE signal processing apparatus is initialized and issues control information, and control information includes resolution ratio 10240x4320, refreshed
The effective image-region of rate 60Hz, cross shear pattern, effective image-region, wherein V-BY-ONE signal processing apparatus 1 is corresponding
No. 1 region in accompanying drawing, No. 2 regions in the effective image-region respective figure of V-BY-ONE signal processing apparatus 2, V-BY-
No. 3 regions in the effective image-region respective figure of ONE signal processing apparatus 3, V-BY-ONE signal processing apparatus 4 it is effective
No. 4 regions in image-region respective figure.
In above-described embodiment, the signal processing after the completion of the initialization of V-BY-ONE signal processing apparatus is：
(1) V-BY-ONE signal sources are the V-BY-ONE that 4 V-BY-ONE signal processing apparatus send 4lane 10K respectively
Source images signal；
(2) 4 V-BY-ONE signal processing apparatus parse to V-BY-ONE source images signals respectively, when generation recovers
Clock and view data；
(3) 4 V-BY-ONE signal processing apparatus carry out shear treatment to view data respectively according to control information, obtain
The view data of corresponding effective image-region；
The view data of effective image-region is sent into DDR cache chips by (4) 4 V-BY-ONE signal processing apparatus respectively
Middle caching；
(5) 4 V-BY-ONE signal processing apparatus read 16lane figure with 60Hz refresh rate from DDR cachings respectively
Picture data,；
(6) 4 V-BY-ONE signal processing apparatus respectively according to recovered clock by the 16lane view data of reading according to
V-BY-ONE agreements are encoded to obtain the V-BY-ONE picture signals of 64lane altogether.
In above-described embodiment, because each V-BY-ONE signal processing apparatus is entered using recovered clock as reference clock
Row V-BY-ONE is encoded, so the reference clock of the V-BY-ONE picture signals of each V-BY-ONE signal processing apparatus generation is same
Source.
8K modules detect embodiment：
As shown in figure 4, it for the V-BY-ONE signal sources of 3840x2160,4lane signaling interface is one to use a resolution ratio
Individual resolution ratio provides image sensing signal for the V-BY-ONE modules of 7680x4320,32lane signaling interface, can use 2
The concurrent working of V-BY-ONE signal processing apparatus is handled V-BY-ONE picture signals.
In above-described embodiment, V-BY-ONE signal sources are that 2 V-BY-ONE signal processing apparatus are assigned with 4lane's respectively
V-BY-ONE source images signals, and be that 2 V-BY-ONE signal processing apparatus are assigned with control signal respectively with IIC interfaces.V-
On BY-ONE signal processing apparatus after electricity, V-BY-ONE signal sources are according to the module information of V-BY-ONE modules respectively to 2 V-
BY-ONE signal processing apparatus is initialized and issues control information, and control information includes resolution ratio 7680x4320, refresh rate
60Hz, vertical shear pattern, effective image-region, the effective image-region of wherein V-BY-ONE signal processing apparatus 1 correspond to attached
No. 1 region in figure, No. 2 regions in the effective image-region respective figure of V-BY-ONE signal processing apparatus 2.
In above-described embodiment, the signal processing after the completion of the initialization of V-BY-ONE signal processing apparatus is：
(1) V-BY-ONE signal sources are the V-BY-ONE that 2 V-BY-ONE signal processing apparatus send 4lane 8K respectively
Source images signal；
(2) 2 V-BY-ONE signal processing apparatus parse to V-BY-ONE source images signals respectively, when generation recovers
Clock and view data；
(3) 2 V-BY-ONE signal processing apparatus carry out shear treatment to view data respectively according to control information, obtain
The view data of corresponding effective image-region；
The view data of effective image-region is sent into DDR cache chips by (4) 2 V-BY-ONE signal processing apparatus respectively
Middle caching；
(5) 2 V-BY-ONE signal processing apparatus read 16lane figure with 60Hz refresh rate from DDR cachings respectively
Picture data,；
(6) 2 V-BY-ONE signal processing apparatus respectively according to recovered clock by the 16lane view data of reading according to
V-BY-ONE agreements are encoded to obtain the V-BY-ONE picture signals of 32lane altogether.
Similarly, in above-described embodiment, because each V-BY-ONE signal processing apparatus uses recovered clock as ginseng
Examine clock and carry out V-BY-ONE codings, so the ginseng of the V-BY-ONE picture signals of each V-BY-ONE signal processing apparatus generation
It is homologous to examine clock.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (10)
1. a kind of V-BY-ONE signal processing methods, it is characterised in that comprise the following steps：
(1) V-BY-ONE source images signals are received, the V-BY-ONE source images signal is parsed and is restored clock and picture number
According to；
(2) shear treatment is carried out to described image data according to control signal and obtains effective image data, and stored described effective
View data obtains data storage；
(3) data storage for specifying lane numbers is read according to output signal refresh rate, and will be read according to the recovered clock
The data storage taken is encoded to obtain V-BY-ONE picture signals according to V-BY-ONE agreements.
2. a kind of V-BY-ONE signal processing methods according to claim 1, it is characterised in that the control signal includes
Image cut pattern information, source images resolution information.
A kind of 3. V-BY-ONE signal processing methods according to claim 2, it is characterised in that described image shear mode
For cross shear pattern or vertical shear pattern.
A kind of 4. V-BY-ONE signal processing methods according to claim 3, it is characterised in that described image shear mode
Information includes effective image-region shearing instruction.
5. a kind of V-BY-ONE signal processing methods according to claim 4, it is characterised in that sheared described in step 2
Processing specifically includes：Described image data are sheared according to the effective image-region shearing instruction, obtain effective image
Data.
6. a kind of V-BY-ONE signal processing methods according to claim 1, it is characterised in that the control signal uses
Low-speed communication interface transmits.
A kind of 7. V-BY-ONE signal processing methods according to claim 6, it is characterised in that the low-speed communication interface
For IIC interfaces or UART interface.
A kind of 8. V-BY-ONE signal processing apparatus, it is characterised in that including an exterior storage medium and be arranged at one can
V-BY-ONE source images signal transmitting and receivings module, image cut module and the output of V-BY-ONE picture signals in programmed logic device
Module；Wherein,
The V-BY-ONE source images signal transmitting and receiving module is used to receive V-BY-ONE source images signals, and parses the V-BY-
ONE source images signals are restored clock and view data；
Described image shear module is used to obtain effective image number to described image data progress shear treatment according to control signal
According to；
The exterior storage medium obtains data storage for storing the effective image data；
The V-BY-ONE picture signals output module is used to deposit according to output signal refresh rate reads specified lane numbers
Data are stored up, and are encoded to obtain V-BY-ONE according to V-BY-ONE agreements by the data storage of reading according to the recovered clock
Picture signal.
9. a kind of V-BY-ONE signal processing apparatus according to claim 8, it is characterised in that also described including being arranged at
Buffer control module in PLD；Described image shear module will be described effective by the buffer control module
View data writes the exterior storage medium；The V-BY-ONE picture signals output module passes through the buffer control module
Read the data storage in the exterior storage medium.
10. a kind of V-BY-ONE signal processing apparatus according to claim 8, it is characterised in that the control signal is adopted
Transmitted with low-speed communication interface, the control signal includes effective image-region shearing instruction.
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| CN201610083873.2A CN105744202B9 (en) | 2016-02-05 | 2016-02-05 | V-BY-ONE signal processing method and device |
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| CN201610083873.2A CN105744202B9 (en) | 2016-02-05 | 2016-02-05 | V-BY-ONE signal processing method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106507017B (en) * | 2016-10-18 | 2021-06-04 | 海信视像科技股份有限公司 | FPGA chip for realizing V-BY-ONE and corresponding V-BY-ONE processing method |
| CN107071568B (en) * | 2017-04-10 | 2019-12-17 | 青岛海信电器股份有限公司 | transmitter and state control method |
| CN108206017B (en) * | 2018-01-25 | 2020-08-11 | 广州晶序达电子科技有限公司 | Method and system for improving screen jumping of liquid crystal panel |
| CN109410804B (en) * | 2018-09-14 | 2021-09-28 | 武汉帆茂电子科技有限公司 | V-by-one signal generation device and method based on FPGA |
| CN109448614B (en) * | 2018-09-14 | 2021-09-28 | 武汉帆茂电子科技有限公司 | FPGA-based Displayport signal generation device and method |
| CN115190330A (en) * | 2022-07-02 | 2022-10-14 | 海的电子科技(苏州)有限公司 | Image signal processing method and device |
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| CN105744202A (en) | 2016-07-06 |
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Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee after: WUHAN JINGCE ELECTRONIC GROUP Co.,Ltd. Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee before: WUHAN JINGCE ELECTRONIC TECHNOLOGY Co.,Ltd. |
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