CN105744202B9 - V-BY-ONE signal processing method and device - Google Patents
V-BY-ONE signal processing method and device Download PDFInfo
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- CN105744202B9 CN105744202B9 CN201610083873.2A CN201610083873A CN105744202B9 CN 105744202 B9 CN105744202 B9 CN 105744202B9 CN 201610083873 A CN201610083873 A CN 201610083873A CN 105744202 B9 CN105744202 B9 CN 105744202B9
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- 238000003860 storage Methods 0.000 claims abstract description 32
- 238000011084 recovery Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims description 53
- 238000010008 shearing Methods 0.000 claims description 16
- 238000004891 communication Methods 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 abstract description 2
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a V-BY-ONE signal processing method and a device, wherein the method comprises the following steps: (1) Receiving a V-BY-ONE source image signal, and analyzing the V-BY-ONE source image signal to obtain a recovery clock and image data; (2) Cutting the image data according to a control signal to obtain effective image data, and storing the effective image data to obtain storage data; (3) And reading the storage data according to the refresh rate of the output signal, and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain a V-BY-ONE image signal. The invention can cut and cache the V-BY-ONE source image signal, and uses the recovered clock as the reference clock of the output signal, and can convert the V-BY-ONE source image signal with low refresh rate and low Lane number into the V-BY-ONE image signal with high refresh rate and high Lane number, thereby avoiding the adoption of external clock wires, reducing the wiring difficulty of PCB, and enhancing the anti-interference capability and the signal output quality of the signal.
Description
Technical Field
The invention relates to the technical field of image signal processing, in particular to a V-BY-ONE signal processing method and device.
Background
With the continuous development of display panel manufacturing technology, 4K resolution display devices have been popular in large scale, and 8K and 10K ultra-high resolution display modules are expected to appear in the market in the next few years. The signal source of the ultra-high resolution display module generally adopts a V-BY-ONE signal, the 8K resolution display module generally adopts a 32-Lane (data channel) or 64-Lane V-BY-ONE signal due to high resolution and large image data volume, and the 10K resolution display module generally adopts a 64-Lane V-BY-ONE signal.
The ultra-high resolution display module can adopt a V-BY-ONE image signal source with a static picture point screen function to detect the picture display quality in various links such as research, development, production and the like. In the prior art, the V-BY-ONE image source is generally realized based on an FPGA architecture, and due to the limitation of the performance of an FPGA chip, the single FPGA chip can output 24-lane V-BY-ONE signals at most at present, so that the single FPGA chip scheme is unrealistic when the ultra-high resolution display module is subjected to screen pointing; when the multi-FPGA chip scheme is used, ONE FPGA chip outputs 16-Lane V-BY-ONE signals, and then 2 (4) FPGA chips output 32-Lane (64-Lane) V-BY-ONE signals together. For the scheme of multiple FPGA chips, because the homology of the reference clocks of the Lane V-BY-ONE signals is required, an external clock line is used, otherwise, abnormal phenomena such as picture flickering and the like can occur to the display module. The external clock line can seriously influence the design of the PCB, so that the wiring difficulty is increased, and meanwhile, the external clock line has poor anti-interference capability, and the transmission length and the signal quality of the cable can be influenced.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention discloses a V-BY-ONE signal processing method and a V-BY-ONE signal processing device, which are used for carrying out shearing processing and high-speed caching on a V-BY-ONE source image signal, using a recovered clock as a reference clock of an output signal, and converting the V-BY-ONE source image signal with low refresh rate and low Lane number into the V-BY-ONE image signal with high refresh rate and high Lane number, thereby avoiding adopting an external clock line, reducing the wiring difficulty of a PCB and enhancing the anti-interference capability and the signal output quality of the signal.
The technical scheme adopted for realizing the purpose of the invention is as follows: a V-BY-ONE signal processing method, the method comprising:
(1) Receiving a V-BY-ONE source image signal, and analyzing the V-BY-ONE source image signal to obtain a recovery clock and image data;
(2) Cutting the image data according to a control signal to obtain effective image data, and storing the effective image data to obtain storage data;
(3) And reading the storage data according to the refresh rate of the output signal, and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain a V-BY-ONE image signal.
Preferably, the control signal includes image clipping mode information and source image resolution information.
Preferably, the image cropping mode information includes an effective image area cropping instruction.
In addition, the invention also provides a V-BY-ONE signal processing device, which comprises an external storage medium, a V-BY-ONE source image signal receiving and transmitting module, an image shearing module and a V-BY-ONE image signal output module, wherein the V-BY-ONE source image signal receiving and transmitting module, the image shearing module and the V-BY-ONE image signal output module are arranged in a programmable logic device;
the V-BY-ONE source image signal receiving and transmitting module is used for receiving the V-BY-ONE source image signal and analyzing the V-BY-ONE source image signal to obtain a recovered clock and image data;
the image shearing module is used for shearing the image data according to the control signal to obtain effective image data;
the external storage medium is used for storing the effective image data to obtain storage data;
the V-BY-ONE image signal output module is used for reading the storage data according to the refresh rate of the output signal and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain the V-BY-ONE image signal.
Preferably, the device of the present invention further comprises a cache control module disposed in the programmable logic device; the image shearing module writes the effective image data into the external storage medium through the cache control module; and the V-BY-ONE image signal output module reads the storage data in the external storage medium through the cache control module.
The invention has the following advantages:
(1) The invention carries out high-speed buffer memory processing to the effective image data of the V-BY-ONE source image signal, and can convert the V-BY-ONE source image signal with low refresh rate and low Lane number into the V-BY-ONE image signal with high refresh rate and high Lane number.
(2) The device of the invention is adopted to process signals in parallel, and the recovered clock is used as the reference clock of the output signals, so that the reference clocks of the output signals of the devices are homologous, the adoption of external clock wires is avoided, the wiring difficulty of a PCB is reduced, and the anti-interference capability and the signal output quality of the signals are enhanced
Drawings
Fig. 1 is a block diagram of a V-BY-ONE signal processing apparatus according to the present invention.
Fig. 2 is a diagram showing an architecture of the V-BY-ONE signal processing apparatus of the present invention applied to high resolution module detection.
Fig. 3 is a schematic diagram showing an embodiment of the V-BY-ONE signal processing apparatus of the present invention applied to 10K module detection.
Fig. 4 is a diagram showing an embodiment of the V-BY-ONE signal processing apparatus applied to 8K module detection.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
As shown in fig. 1, the V-BY-ONE signal processing apparatus disclosed in the present invention includes a V-BY-ONE source image signal transceiver module, an image clipping module, a buffer control module, and a V-BY-ONE image signal output module, which are disposed in a programmable logic device, and an external storage medium electrically connected to the buffer control module.
In the above embodiment, the V-BY-ONE source image signal transceiver module is configured to receive a V-BY-ONE source image signal, and parse the V-BY-ONE source image signal to obtain a recovered clock and image data; the image shearing module is used for shearing the image data according to the control signal to obtain effective image data; the external storage medium is used for storing the effective image data to obtain storage data; the cache control module is used for realizing the reading and writing of data to the external storage medium; the V-BY-ONE image signal output module is used for reading the storage data according to the refresh rate of the output signal, and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain the V-BY-ONE image signal.
In the above embodiment, the programmable logic device is an FPGA chip; the external storage medium adopts a DDR cache chip; the control signal is transmitted by adopting a low-speed communication interface such as an IIC interface or a UART interface and the like.
In the above embodiment, the control signal includes image clipping mode information and source image resolution information, wherein the image clipping mode is classified into a cross clipping mode or a vertical clipping mode.
As shown in FIG. 2, when a low resolution, low refresh rate, low-Lane number V-BY-ONE signal source is used to detect a high resolution V-BY-ONE module, multiple devices of the invention can be used to operate in parallel to form a detection system. For the convenience of further explanation of the present invention, the inventive apparatus will hereinafter be referred to as a V-BY-ONE signal processing apparatus.
10K module detection embodiment:
as shown in fig. 3, a V-BY-ONE signal source with a resolution of 5120x2160 and a 4-lane signal interface is used for providing an image detection signal for a V-BY-ONE module with a resolution of 10240x4320 and a 64-lane signal interface, and 4V-BY-ONE signal processing devices can be used for processing the V-BY-ONE image signal in parallel.
In the above embodiment, the V-BY-ONE signal source is a 4-lane V-BY-ONE source image signal respectively allocated to the 4V-BY-ONE signal processing apparatuses, and the IIC interface is a 4-V-BY-ONE signal processing apparatus respectively allocated control signals. After the V-BY-ONE signal processing device is powered on, the V-BY-ONE signal source respectively initializes 4V-BY-ONE signal processing devices according to module information of the V-BY-ONE module and issues control information, wherein the control information comprises a resolution 10240x4320, a refresh rate 60Hz, a cross shearing mode and an effective image area, the effective image area of the V-BY-ONE signal processing device 1 corresponds to an area No. 1 in the drawing, the effective image area of the V-BY-ONE signal processing device 2 corresponds to an area No. 2 in the drawing, the effective image area of the V-BY-ONE signal processing device 3 corresponds to an area No. 3 in the drawing, and the effective image area of the V-BY-ONE signal processing device 4 corresponds to an area No. 4 in the drawing.
In the above embodiment, the signal processing process after the initialization of the V-BY-ONE signal processing device is completed is as follows:
(1) The V-BY-ONE signal source is that 4V-BY-ONE signal processing devices respectively send 4Lane 5K V-BY-ONE source image signals;
(2) The 4V-BY-ONE signal processing devices respectively analyze the V-BY-ONE source image signals to generate a recovery clock and image data;
(3) The 4V-BY-ONE signal processing devices respectively shear the image data according to the control information to obtain the image data corresponding to the effective image area;
(4) The 4V-BY-ONE signal processing devices respectively send the image data of the effective image area into the DDR cache chip for cache;
(5) The 4V-BY-ONE signal processing devices respectively read 16-lane image data from the DDR cache at a refresh rate of 60 Hz;
(6) The 4V-BY-ONE signal processing devices respectively encode the read 16-Lane image data according to the V-BY-ONE protocol according to the recovery clock to obtain a total of 64-Lane V-BY-ONE image signals.
In the above embodiment, since each V-BY-ONE signal processing apparatus performs V-BY-ONE encoding using the recovered clock as the reference clock, the reference clocks of the V-BY-ONE image signals generated BY each V-BY-ONE signal processing apparatus are homologous.
8K Module detection embodiment:
as shown in fig. 4, a V-BY-ONE signal source with a resolution of 3840x4320 and a 4-lane signal interface is used for providing an image detection signal for a V-BY-ONE module with a resolution of 7680x4320 and a 32-lane signal interface, and 2V-BY-ONE signal processing devices can be used for processing the V-BY-ONE image signal in parallel.
In the above embodiment, the V-BY-ONE source image signals of 4lane are respectively allocated to the 2V-BY-ONE signal processing apparatuses, and the IIC interface is used to respectively allocate control signals to the 2V-BY-ONE signal processing apparatuses. After the V-BY-ONE signal processing device is powered on, the V-BY-ONE signal source respectively initializes 2V-BY-ONE signal processing devices according to module information of the V-BY-ONE module and issues control information, wherein the control information comprises resolution 7680x4320, refresh rate 60Hz, vertical shearing mode and effective image area, the effective image area of the V-BY-ONE signal processing device 1 corresponds to the No. 1 area in the attached drawing, and the effective image area of the V-BY-ONE signal processing device 2 corresponds to the No. 2 area in the attached drawing.
In the above embodiment, the signal processing process after the initialization of the V-BY-ONE signal processing device is completed is as follows:
(1) The V-BY-ONE signal source is that 2V-BY-ONE signal processing devices respectively send V-BY-ONE source image signals of 4Lane 4K;
(2) The 2V-BY-ONE signal processing devices respectively analyze the V-BY-ONE source image signals to generate a recovery clock and image data;
(3) The 2V-BY-ONE signal processing devices respectively shear the image data according to the control information to obtain the image data corresponding to the effective image area;
(4) The 2V-BY-ONE signal processing devices respectively send the image data of the effective image area into the DDR cache chip for cache;
(5) 2V-BY-ONE signal processing devices respectively read 16-lane image data from the DDR cache at a refresh rate of 60 Hz;
(6) The 2V-BY-ONE signal processing devices respectively encode the read 16-Lane image data according to the V-BY-ONE protocol according to the recovery clock to obtain a total of 32-Lane V-BY-ONE image signals.
Also, in the above-described embodiments, since each V-BY-ONE signal processing apparatus performs V-BY-ONE encoding using the recovered clock as a reference clock, the reference clocks of the V-BY-ONE image signals generated BY each V-BY-ONE signal processing apparatus are homologous.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The V-BY-ONE signal processing method is characterized BY comprising the following steps of:
(1) Receiving a V-BY-ONE source image signal, and analyzing the V-BY-ONE source image signal to obtain a recovery clock and image data;
(2) Cutting the image data according to a control signal to obtain effective image data, and storing the effective image data to obtain storage data;
(3) And reading the storage data with the designated Lane number according to the refresh rate of the output signal, and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain a V-BY-ONE image signal.
2. The V-BY-ONE signal processing method of claim 1, wherein the control signal comprises image clipping mode information, source image resolution information.
3. The V-BY-ONE signal processing method of claim 2, wherein the image clipping mode is a cross clipping mode or a vertical clipping mode.
4. A V-BY-ONE signal processing method according to claim 3, wherein said image cropping pattern information comprises an effective image area cropping instruction.
5. The method for processing V-BY-ONE signals according to claim 4, wherein said shearing in step 2 comprises: and cutting the image data according to the effective image area cutting instruction to obtain effective image data.
6. The V-BY-ONE signal processing method of claim 1, wherein the control signal is transmitted using a low-speed communication interface.
7. The method of claim 6, wherein the low-speed communication interface is an IIC interface or a UART interface.
8. The V-BY-ONE signal processing device is characterized BY comprising an external storage medium, a V-BY-ONE source image signal receiving and transmitting module, an image shearing module and a V-BY-ONE image signal output module, wherein the V-BY-ONE source image signal receiving and transmitting module, the image shearing module and the V-BY-ONE image signal output module are arranged in a programmable logic device; wherein,
the V-BY-ONE source image signal receiving and transmitting module is used for receiving the V-BY-ONE source image signal and analyzing the V-BY-ONE source image signal to obtain a recovered clock and image data;
the image shearing module is used for shearing the image data according to the control signal to obtain effective image data;
the external storage medium is used for storing the effective image data to obtain storage data;
the V-BY-ONE image signal output module is used for reading the storage data with the designated Lane number according to the refresh rate of the output signal, and encoding the read storage data according to the V-BY-ONE protocol according to the recovery clock to obtain the V-BY-ONE image signal.
9. The V-BY-ONE signal processing apparatus of claim 8, further comprising a cache control module disposed in the programmable logic device; the image shearing module writes the effective image data into the external storage medium through the cache control module; and the V-BY-ONE image signal output module reads the storage data in the external storage medium through the cache control module.
10. The V-BY-ONE signal processing apparatus of claim 8, wherein said control signal is transmitted using a low speed communication interface, said control signal comprising an active image area clipping command.
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| CN106507017B (en) * | 2016-10-18 | 2021-06-04 | 海信视像科技股份有限公司 | FPGA chip for realizing V-BY-ONE and corresponding V-BY-ONE processing method |
| CN107071568B (en) * | 2017-04-10 | 2019-12-17 | 青岛海信电器股份有限公司 | transmitter and state control method |
| CN108206017B (en) * | 2018-01-25 | 2020-08-11 | 广州晶序达电子科技有限公司 | Method and system for improving screen jumping of liquid crystal panel |
| CN109410804B (en) * | 2018-09-14 | 2021-09-28 | 武汉帆茂电子科技有限公司 | V-by-one signal generation device and method based on FPGA |
| CN109448614B (en) * | 2018-09-14 | 2021-09-28 | 武汉帆茂电子科技有限公司 | FPGA-based Displayport signal generation device and method |
| CN115190330A (en) * | 2022-07-02 | 2022-10-14 | 海的电子科技(苏州)有限公司 | Image signal processing method and device |
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