CN105743489A - Level switching circuit without static power consumption - Google Patents
Level switching circuit without static power consumption Download PDFInfo
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- CN105743489A CN105743489A CN201610181913.7A CN201610181913A CN105743489A CN 105743489 A CN105743489 A CN 105743489A CN 201610181913 A CN201610181913 A CN 201610181913A CN 105743489 A CN105743489 A CN 105743489A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
- H03K19/018571—Coupling arrangements; Impedance matching circuits of complementary type, e.g. CMOS
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Abstract
The invention discloses a level switching circuit without static power consumption. The circuit comprises an inverter circuit, a converting circuit, a switching circuit and an outputting circuit. The level switching circuit without static power consumption provided by the invention can achieve the switching between different levels, after the switching is completed, no direct current channel exists in the whole circuit, and therefore, the circuit does not generate static power consumption after the level switching is completed.
Description
Technical field
The invention belongs to technical field of circuit design, particularly to a kind of level shifting circuit without quiescent dissipation.
Background technology
In design of electronic circuits, internal system usually there will be input and the inharmonic problem of output logic, adds the complexity of system design.Such as: when the digital circuit of 1.8V communicates with the analog circuit being operated in 3.3V, it is necessary to solving the transfer problem of two kinds of level, this circuit carrying out level conversion is exactly level translator.
Along with the continuing to bring out of digital IC of different operating voltage, the necessity of logic level transition is more prominent, and level conversion mode changes also with logic voltage, the form of data/address bus and the difference of message transmission rate.Although logic chip can realize the conversion (as by 5V level conversion to 3V level) to relatively low logic level of the higher logic level, but logic circuit chip is just much more difficult when relatively low logic level transition becomes higher logic level (as by 3V logical transition to 5V logic)；Although can also realizing with the combination of transistor even resistance and diode, but because of the impact by parasitic capacitance, these methods greatly limit the transfer rate of data, and also there is quiescent dissipation.
Summary of the invention
It is an object of the invention to provide a kind of level shifting circuit without quiescent dissipation.
For this, technical solution of the present invention is as follows:
A kind of level shifting circuit without quiescent dissipation, including inverter circuit, change-over circuit, on-off circuit and output circuit；
Inverter circuit includes the first CMOS inverter, the second CMOS inverter and the 3rd CMOS inverter；First CMOS inverter includes transistor M1 and transistor M2；The grid of transistor M1 and transistor M2 is all connected to input Vin, the source ground of transistor M1, and the drain electrode of transistor M2 is received in the drain electrode of transistor M1, and the source electrode of transistor M2 meets low-voltage starting voltage Vdd-low；Second CMOS inverter includes transistor M3 and transistor M4；The grid of transistor M3 receives the drain electrode of transistor M2, the source ground of transistor M3, and the drain electrode of transistor M4 is received in the drain electrode of transistor M3, and the grid of transistor M4 receives the grid of transistor M3, and the source electrode of transistor M4 meets low-voltage starting voltage Vdd-low；3rd CMOS inverter includes transistor M5 and transistor M6；The grid of transistor M6 receives the drain electrode of transistor M4, and the source class of transistor M6 receives low-voltage starting voltage Vdd-low, and the drain electrode of transistor M5 is received in the drain electrode of transistor M6, and the grid of transistor M5 receives the grid of transistor M6, the source class ground connection of transistor M5；
Change-over circuit includes transistor M7, transistor M8, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2；The source class of transistor M13 receives low-voltage starting voltage Vdd-low；One end of resistance R1 receives the source class of transistor M13, and the other end of resistance R1 receives the drain electrode of transistor M13；One end of electric capacity C1 receives the drain electrode of transistor M13, and the other end of electric capacity C1 receives the drain electrode of transistor M5；The grid of transistor M8 receives the drain electrode of transistor M2, and the source class of transistor M8 receives low-voltage starting voltage Vdd-low, and the drain of transistor M8 receives the drain electrode of transistor M7；The grid of transistor M7 receives the grid of transistor M8；Resistance R2 mono-end receives the source class of transistor M14, and the other end of resistance R2 receives the drain electrode of transistor M14；One end of electric capacity C2 receives the drain electrode of transistor M14, and the other end of electric capacity C2 receives the drain electrode of transistor M7；The grid of transistor M14 meets output end vo ut, and the source class of transistor M14 receives the source class of transistor M8, and the drain electrode of transistor M12 is received in the drain electrode of transistor M14；The source class of transistor M12 receives the source electrode of transistor M11, and the grid of transistor M12 receives the grid of transistor M13；The grid of transistor M11 meets output end vo ut, and the drain electrode of transistor M13 is received in the drain electrode of transistor M11；The grid of transistor M15 receives the source class of transistor M12, and the drain electrode of transistor M17 is received in the drain electrode of transistor M15, and the source class of transistor M15 receives the drain electrode of transistor M9；The grid of transistor M9 receives the grid of transistor M5, the source class ground connection of transistor M9；One end of resistance R3 receives the source class of transistor M17, and the other end of resistance R3 receives the drain electrode of transistor M17；The source class of transistor M17 meets high voltage starting voltage Vdd-high, and the grid of transistor M17 receives the drain electrode of transistor M18；The source class of transistor M18 receives high voltage starting voltage Vdd-high, and the grid of transistor M18 receives the drain electrode of transistor M17, and the drain electrode of transistor M16 is received in the drain electrode of transistor M18；The grid of transistor M16 receives the grid of transistor M15, and the source class of transistor M16 receives the drain electrode of transistor M10；The grid of transistor M10 receives the grid of transistor M8, the source class ground connection of transistor M10；One end of resistance R4 receives the source class of transistor M18, and the other end of resistance R4 receives the drain electrode of transistor M18；
On-off circuit includes NAND gate NAND1 and NAND gate NAND2；NAND gate NAND1 includes two inputs, an Enable Pin EN and an outfan；NAND gate NAND2 includes two inputs and an outfan；One of them input of NAND gate NAND1 receives the drain electrode of transistor M18 in change-over circuit, and another input of NAND gate NAND1 receives the outfan of NAND gate NAND2；One of them input of NAND gate NAND2 receives the grid of transistor M18, and another input of NAND gate NAND2 receives the outfan of not gate NAND1；
Output circuit includes transistor M19, transistor M20, transistor M21, transistor M22；The grid of transistor M19 receives the outfan of NAND gate NAND2 in on-off circuit, and the source class ground connection of transistor M19, the drain electrode of transistor M21 is received in the drain electrode of transistor M19；The source class of transistor M21 receives high voltage starting voltage Vdd-high, and the grid of transistor M21 receives the drain electrode of transistor M22, and the grid of transistor M13 in change-over circuit is received in the drain electrode of transistor M21；The source class of transistor M22 receives high voltage starting voltage Vdd-high, and the grid of transistor M22 receives the drain electrode of transistor M21, and the drain electrode of transistor M20 is received in the drain electrode of transistor M22；Output end vo ut is received in the drain electrode of transistor M20, and the grid of transistor M20 receives the outfan of the NAND gate NAND1 in on-off circuit, the source class ground connection of transistor M20.
Described transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, transistor M8, transistor M9, transistor M10 are low threshold voltage and low breakdown voltage device；Transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, transistor M19, transistor M20, transistor M21, transistor M22 are high threshold voltage and high breakdown voltage device.
Described transistor M1, transistor M3, transistor M5, transistor M7, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M19, transistor M20 are enhancement mode NMOS tube；Transistor M2, transistor M4, transistor M6, transistor M8, transistor M17, transistor M18, transistor M21, transistor M22 are enhancement mode PMOS.
Compared with prior art, the level shifting circuit without quiescent dissipation provided by the invention can realize the conversion between varying level and after level conversion, is absent from DC channel, will not produce without quiescent dissipation in circuit.
Accompanying drawing explanation
Fig. 1 is the level shifting circuit figure without quiescent dissipation provided by the invention.
Detailed description of the invention
Below in conjunction with drawings and the specific embodiments, the present invention is described further, but the present invention is had absolutely not any restriction by following embodiment.
As it is shown in figure 1, this is without the level shifting circuit of quiescent dissipation, including inverter circuit, change-over circuit, on-off circuit and output circuit；
Inverter circuit includes the first CMOS inverter, the second CMOS inverter and the 3rd CMOS inverter；First CMOS inverter includes transistor M1 and transistor M2；The grid of transistor M1 and transistor M2 is all connected to input Vin, the source ground of transistor M1, and the drain electrode of transistor M2 is received in the drain electrode of transistor M1, and the source electrode of transistor M2 meets low-voltage starting voltage Vdd-low；Second CMOS inverter includes transistor M3 and transistor M4；The grid of transistor M3 receives the drain electrode of transistor M2, the source ground of transistor M3, and the drain electrode of transistor M4 is received in the drain electrode of transistor M3, and the grid of transistor M4 receives the grid of transistor M3, and the source electrode of transistor M4 meets low-voltage starting voltage Vdd-low；3rd CMOS inverter includes transistor M5 and transistor M6；The grid of transistor M6 receives the drain electrode of transistor M4, and the source class of transistor M6 receives low-voltage starting voltage Vdd-low, and the drain electrode of transistor M5 is received in the drain electrode of transistor M6, and the grid of transistor M5 receives the grid of transistor M6, the source class ground connection of transistor M5；
Change-over circuit includes transistor M7, transistor M8, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2；The source class of transistor M13 receives low-voltage starting voltage Vdd-low；One end of resistance R1 receives the source class of transistor M13, and the other end of resistance R1 receives the drain electrode of transistor M13；One end of electric capacity C1 receives the drain electrode of transistor M13, and the other end of electric capacity C1 receives the drain electrode of transistor M5；The grid of transistor M8 receives the drain electrode of transistor M2, and the source class of transistor M8 receives low-voltage starting voltage Vdd-low, and the drain of transistor M8 receives the drain electrode of transistor M7；The grid of transistor M7 receives the grid of transistor M8；Resistance R2 mono-end receives the source class of transistor M14, and the other end of resistance R2 receives the drain electrode of transistor M14；One end of electric capacity C2 receives the drain electrode of transistor M14, and the other end of electric capacity C2 receives the drain electrode of transistor M7；The grid of transistor M14 meets output end vo ut, and the source class of transistor M14 receives the source class of transistor M8, and the drain electrode of transistor M12 is received in the drain electrode of transistor M14；The source class of transistor M12 receives the source electrode of transistor M11, and the grid of transistor M12 receives the grid of transistor M13；The grid of transistor M11 meets output end vo ut, and the drain electrode of transistor M13 is received in the drain electrode of transistor M11；The grid of transistor M15 receives the source class of transistor M12, and the drain electrode of transistor M17 is received in the drain electrode of transistor M15, and the source class of transistor M15 receives the drain electrode of transistor M9；The grid of transistor M9 receives the grid of transistor M5, the source class ground connection of transistor M9；One end of resistance R3 receives the source class of transistor M17, and the other end of resistance R3 receives the drain electrode of transistor M17；The source class of transistor M17 meets high voltage starting voltage Vdd-high, and the grid of transistor M17 receives the drain electrode of transistor M18；The source class of transistor M18 receives high voltage starting voltage Vdd-high, and the grid of transistor M18 receives the drain electrode of transistor M17, and the drain electrode of transistor M16 is received in the drain electrode of transistor M18；The grid of transistor M16 receives the grid of transistor M15, and the source class of transistor M16 receives the drain electrode of transistor M10；The grid of transistor M10 receives the grid of transistor M8, the source class ground connection of transistor M10；One end of resistance R4 receives the source class of transistor M18, and the other end of resistance R4 receives the drain electrode of transistor M18；
On-off circuit includes NAND gate NAND1 and NAND gate NAND2；NAND gate NAND1 includes two inputs, an Enable Pin EN and an outfan；NAND gate NAND2 includes two inputs and an outfan；One of them input of NAND gate NAND1 receives the drain electrode of transistor M18 in change-over circuit, and another input of NAND gate NAND1 receives the outfan of NAND gate NAND2；One of them input of NAND gate NAND2 receives the grid of transistor M18, and another input of NAND gate NAND2 receives the outfan of not gate NAND1；
Output circuit includes transistor M19, transistor M20, transistor M21, transistor M22；The grid of transistor M19 receives the outfan of NAND gate NAND2 in on-off circuit, and the source class ground connection of transistor M19, the drain electrode of transistor M21 is received in the drain electrode of transistor M19；The source class of transistor M21 receives high voltage starting voltage Vdd-high, and the grid of transistor M21 receives the drain electrode of transistor M22, and the grid of transistor M13 in change-over circuit is received in the drain electrode of transistor M21；The source class of transistor M22 receives high voltage starting voltage Vdd-high, and the grid of transistor M22 receives the drain electrode of transistor M21, and the drain electrode of transistor M20 is received in the drain electrode of transistor M22；Output end vo ut is received in the drain electrode of transistor M20, and the grid of transistor M20 receives the outfan of the NAND gate NAND1 in on-off circuit, the source class ground connection of transistor M20.
Described transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, transistor M8, transistor M9, transistor M10 are low threshold voltage and low breakdown voltage device；Transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, transistor M19, transistor M20, transistor M21, transistor M22 are high threshold voltage and high breakdown voltage device.
Described transistor M1, transistor M3, transistor M5, transistor M7, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M19, transistor M20 are enhancement mode NMOS tube；Transistor M2, transistor M4, transistor M6, transistor M8, transistor M17, transistor M18, transistor M21, transistor M22 are enhancement mode PMOS.
Operation principle without the level shifting circuit of quiescent dissipation provided by the invention is as follows:
When high voltage starting voltage Vdd-high is 3.3V, low-voltage starting voltage Vdd-low is 0.5V, and the threshold voltage of low threshold voltage device is 0.3V, when the threshold voltage of high threshold voltage devices is 0.7V；
(1) as the Enable Pin EN=0 of NAND gate NAND1, the outfan of NAND gate NAND1 is 1, in output circuit, transistor M20, transistor M21 open, transistor M19, transistor M22 end, now no matter how input Vin changes, and output end vo ut is always 0, and whole circuit is closed；
(2) when the Enable Pin EN=0 of NAND gate NAND1 and input Vin are set to 0:
In inverter circuit, transistor M1, transistor M4, transistor M5 end, and transistor M2, transistor M3, transistor M6 turn on；
In change-over circuit, transistor M8, transistor M9, transistor M11, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18 end, and transistor M7, transistor M10, transistor M12, transistor M13 turn on；All not in the closed circuit, the pressure reduction at the pressure reduction at resistance R1 two ends and resistance R2 two ends is zero to resistance R1 and resistance R2, and due to transistor M6 conducting in inverter circuit, the voltage between electric capacity C1 two-plate is zero；Owing to transistor M7 turns on, transistor M8 ends, and the voltage between electric capacity C2 two-plate is 0.5V；
In on-off circuit, NAND gate NAND1 is output as 1, and NAND gate NAND2 is output as 0；
In output circuit, transistor M19, transistor M22 end, and transistor M20, transistor M21 turn on, and output end vo ut is 0；
(3) the Enable Pin EN=1 of NAND gate NAND1, input Vin are set when changing from logical zero to logic 1 (0.5V):
In inverter circuit, transistor M2, transistor M3, transistor M6 end, and transistor M1, transistor M4, transistor M5 turn on；
In change-over circuit, owing to the voltage of output end vo ut will not instantaneous mutation, therefore transistor M11, transistor M12, transistor M13, transistor M14 are still maintained at the Enable Pin EN=0 and output end vo ut of NAND gate NAND1 is state when 0, i.e. transistor M11, transistor M14 cut-off, transistor M12, transistor M13 turn on；Transistor M6 cut-off in inverter circuit, transistor M5 conducting, the bottom crown ground connection of electric capacity C1, transistor M13 provides bigger momentary charge electric current to electric capacity C1；Owing to transistor M7 ends, transistor M8 turns on, the voltage of electric capacity C2 bottom crown is 0.5V, owing to the pressure reduction between electric capacity C2 two-plate is 0.5V, so now the voltage of the top crown of electric capacity C2 becomes 1.0V, the grid voltage of transistor M15 and transistor M16 becomes 1.0V, now transistor M9 conducting, the source voltage of transistor M15 is 0, and the grid source pressure reduction of transistor M15 is 1V, and transistor M15 turns on；Owing to transistor M10 ends, therefore transistor M16 cut-off；Owing to transistor M15 turns on, the voltage of node Q3 drops to zero from 3.3V；
In on-off circuit, the output of NAND gate NAND2 becomes 1, and the output of NAND gate NAND1 becomes 0；
In output circuit, transistor M19, transistor M22 turn on, and transistor M20, transistor M21 end, and output end vo ut becomes 3.3V；
nullOnce output end vo ut becomes 3.3V，Transistor M11、Transistor M14 turns on，Transistor M12、Transistor M13 ends，Resistance R1 continues to electric capacity C1 charging or supplements electric leakage，Make the voltage swing at node Q1 place equal to 0.5V，Meanwhile，The grid voltage size of transistor M15 and transistor M16 drops to 0.5V，Transistor M16、Transistor M15 is again at cut-off state，The voltage of node Q3 is pulled upward to 3.3V by resistance R3，The now output of NAND gate NAND2 is determined by the output of NAND gate NAND1，Namely the output of NAND gate NAND2 is maintained at logic high，The output valve of output end vo ut remains unchanged，Remain as 3.3V，In any case now input Vin voltage change，The output of output end vo ut is always 3.3V；
(4) when the Enable Pin EN=0 of NAND gate NAND1 and input Vin are set to 1:
In inverter circuit, transistor M1, transistor M4, transistor M5 turn on, and transistor M2, transistor M3, transistor M6 end；
In change-over circuit, transistor M10, transistor M11, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18 end, and transistor M8, transistor M9, transistor M12, transistor M13 turn on；All not in the closed circuit, the pressure reduction at the pressure reduction at resistance R1 two ends and resistance R2 two ends is zero to resistance R1 and resistance R2, and the voltage of electric capacity C1 top crown is 0.5V, and due to transistor M5 conducting in inverter circuit, the voltage of electric capacity C1 bottom crown is zero；Owing to transistor M7 ends, transistor M8 turns on, and the voltage between electric capacity C2 two-plate is zero；
In on-off circuit, NAND gate NAND1 is output as 1, and NAND gate NAND2 is output as 0；
In output circuit, transistor M19, transistor M22 end, and transistor M20, transistor M21 turn on, and output end vo ut is 0；
(5) the Enable Pin EN=1 of NAND gate NAND1 is set, when input Vin changes from logic 1 to logical zero:
In inverter circuit, transistor M2, transistor M3, transistor M6 turn on, and transistor M1, transistor M4, transistor M5 end；
In change-over circuit, owing to the voltage of output end vo ut will not instantaneous mutation, therefore transistor M11, transistor M12, transistor M13, transistor M14 are still maintained at the Enable Pin EN=0 and output end vo ut of NAND gate NAND1 is state when 0, i.e. transistor M11, transistor M14 cut-off, transistor M12, transistor M13 turn on；Due to transistor M6 conducting in inverter circuit, transistor M5 cut-off, it is zero that electric capacity C1 makes the voltage between electric capacity C1 two-plate by discharging；Owing to transistor M7 turns on, transistor M8 ends, and the voltage of electric capacity C2 bottom crown is zero, and the voltage swing of electric capacity C2 top crown is equal to 0.5V；Owing to transistor M12 turns on, the grid voltage of transistor M15 and transistor M16 is 0.5V, transistor M15 and transistor M16 cut-off, meanwhile, and transistor M17 and transistor M18 cut-off；
In on-off circuit, the output of NAND gate NAND2 is determined by the output of NAND gate NAND1, therefore the output of NAND gate NAND2 becomes 0, and NAND gate NAND1 is output as 1；
In output circuit, transistor M19, transistor M22 turn on, and transistor M20, transistor M21 end, and output end vo ut is 0；
Once output end vo ut is 0, i.e. transistor M11, transistor M14 cut-off, transistor M12, transistor M13 turn on, in any case now input Vin change, the output of output end vo ut is always 0.
Claims (3)
1. the level shifting circuit without quiescent dissipation, it is characterised in that the described level shifting circuit without quiescent dissipation includes inverter circuit, change-over circuit, on-off circuit and output circuit；
Inverter circuit includes the first CMOS inverter, the second CMOS inverter and the 3rd CMOS inverter；First CMOS inverter includes transistor M1 and transistor M2；The grid of transistor M1 and transistor M2 is all connected to input Vin, the source ground of transistor M1, and the drain electrode of transistor M2 is received in the drain electrode of transistor M1, and the source electrode of transistor M2 meets low-voltage starting voltage Vdd-low；Second CMOS inverter includes transistor M3 and transistor M4；The grid of transistor M3 receives the drain electrode of transistor M2, the source ground of transistor M3, and the drain electrode of transistor M4 is received in the drain electrode of transistor M3, and the grid of transistor M4 receives the grid of transistor M3, and the source electrode of transistor M4 meets low-voltage starting voltage Vdd-low；3rd CMOS inverter includes transistor M5 and transistor M6；The grid of transistor M6 receives the drain electrode of transistor M4, and the source class of transistor M6 receives low-voltage starting voltage Vdd-low, and the drain electrode of transistor M5 is received in the drain electrode of transistor M6, and the grid of transistor M5 receives the grid of transistor M6, the source class ground connection of transistor M5；
Change-over circuit includes transistor M7, transistor M8, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2；The source class of transistor M13 receives low-voltage starting voltage Vdd-low；One end of resistance R1 receives the source class of transistor M13, and the other end of resistance R1 receives the drain electrode of transistor M13；One end of electric capacity C1 receives the drain electrode of transistor M13, and the other end of electric capacity C1 receives the drain electrode of transistor M5；The grid of transistor M8 receives the drain electrode of transistor M2, and the source class of transistor M8 receives low-voltage starting voltage Vdd-low, and the drain of transistor M8 receives the drain electrode of transistor M7；The grid of transistor M7 receives the grid of transistor M8；Resistance R2 mono-end receives the source class of transistor M14, and the other end of resistance R2 receives the drain electrode of transistor M14；One end of electric capacity C2 receives the drain electrode of transistor M14, and the other end of electric capacity C2 receives the drain electrode of transistor M7；The grid of transistor M14 meets output end vo ut, and the source class of transistor M14 receives the source class of transistor M8, and the drain electrode of transistor M12 is received in the drain electrode of transistor M14；The source class of transistor M12 receives the source electrode of transistor M11, and the grid of transistor M12 receives the grid of transistor M13；The grid of transistor M11 meets output end vo ut, and the drain electrode of transistor M13 is received in the drain electrode of transistor M11；The grid of transistor M15 receives the source class of transistor M12, and the drain electrode of transistor M17 is received in the drain electrode of transistor M15, and the source class of transistor M15 receives the drain electrode of transistor M9；The grid of transistor M9 receives the grid of transistor M5, the source class ground connection of transistor M9；One end of resistance R3 receives the source class of transistor M17, and the other end of resistance R3 receives the drain electrode of transistor M17；The source class of transistor M17 meets high voltage starting voltage Vdd-high, and the grid of transistor M17 receives the drain electrode of transistor M18；The source class of transistor M18 receives high voltage starting voltage Vdd-high, and the grid of transistor M18 receives the drain electrode of transistor M17, and the drain electrode of transistor M16 is received in the drain electrode of transistor M18；The grid of transistor M16 receives the grid of transistor M15, and the source class of transistor M16 receives the drain electrode of transistor M10；The grid of transistor M10 receives the grid of transistor M8, the source class ground connection of transistor M10；One end of resistance R4 receives the source class of transistor M18, and the other end of resistance R4 receives the drain electrode of transistor M18；
On-off circuit includes NAND gate NAND1 and NAND gate NAND2；NAND gate NAND1 includes two inputs, an Enable Pin EN and an outfan；NAND gate NAND2 includes two inputs and an outfan；One of them input of NAND gate NAND1 receives the drain electrode of transistor M18 in change-over circuit, and another input of NAND gate NAND1 receives the outfan of NAND gate NAND2；One of them input of NAND gate NAND2 receives the grid of transistor M18, and another input of NAND gate NAND2 receives the outfan of not gate NAND1；
Output circuit includes transistor M19, transistor M20, transistor M21, transistor M22；The grid of transistor M19 receives the outfan of NAND gate NAND2 in on-off circuit, and the source class ground connection of transistor M19, the drain electrode of transistor M21 is received in the drain electrode of transistor M19；The source class of transistor M21 receives high voltage starting voltage Vdd-high, and the grid of transistor M21 receives the drain electrode of transistor M22, and the grid of transistor M13 in change-over circuit is received in the drain electrode of transistor M21；The source class of transistor M22 receives high voltage starting voltage Vdd-high, and the grid of transistor M22 receives the drain electrode of transistor M21, and the drain electrode of transistor M20 is received in the drain electrode of transistor M22；Output end vo ut is received in the drain electrode of transistor M20, and the grid of transistor M20 receives the outfan of the NAND gate NAND1 in on-off circuit, the source class ground connection of transistor M20.
2. the level shifting circuit without quiescent dissipation according to claim 1, it is characterized in that, described transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, transistor M8, transistor M9, transistor M10 are low threshold voltage and low breakdown voltage device；Transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M17, transistor M18, transistor M19, transistor M20, transistor M21, transistor M22 are high threshold voltage and high breakdown voltage device.
3. the level shifting circuit without quiescent dissipation according to claim 1, it is characterized in that, described transistor M1, transistor M3, transistor M5, transistor M7, transistor M9, transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, transistor M19, transistor M20 are enhancement mode NMOS tube；Transistor M2, transistor M4, transistor M6, transistor M8, transistor M17, transistor M18, transistor M21, transistor M22 are enhancement mode PMOS.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1165435A (en) * | 1996-03-21 | 1997-11-19 | 冲电气工业株式会社 | Output buffer circuit |
| KR20020076622A (en) * | 2001-03-29 | 2002-10-11 | 주식회사 하이닉스반도체 | Circuit for Clocked Level Shifter |
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
| CN105144584A (en) * | 2013-04-18 | 2015-12-09 | 夏普株式会社 | Level shift circuit |
-
2016
- 2016-03-28 CN CN201610181913.7A patent/CN105743489B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1165435A (en) * | 1996-03-21 | 1997-11-19 | 冲电气工业株式会社 | Output buffer circuit |
| KR20020076622A (en) * | 2001-03-29 | 2002-10-11 | 주식회사 하이닉스반도체 | Circuit for Clocked Level Shifter |
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
| CN105144584A (en) * | 2013-04-18 | 2015-12-09 | 夏普株式会社 | Level shift circuit |
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| CN105743489B (en) | 2018-07-27 |
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