KR20020076622A - Circuit for Clocked Level Shifter - Google Patents

Abstract

PURPOSE: A clocked level shifter is provided to reduce an access time and output normally data according to a command by applying a clock signal of a clock level shifter to a level shifter portion, directly. CONSTITUTION: A clock signal portion(400) is formed with a NOR gate and the first inverter(NV1). The NOR gate receives a clock signal(clk) and a latch disable signal(dis_latch) and performs a logical operation for the clock signal(clk) and the latch disable signal(dis_latch). The first inverter(NV1) inverts an output of the NOR gate(NOR) and outputs a latch bar signal(/latch). A data signal portion(500) is formed with a NAND gate(NAND). The NAND gate(NAND) performs a logical operation for a data signal and an enable signal and outputs a data bar signal(/data). A level shifter(600) is formed with the first NMOS transistor(NM1), the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor(NM4), the first PMOS transistor(PM1), and the second PMOS transistor(PM2). A latch portion(700) is formed with the second inverter(NV2) and the third inverter(NV3).

Description

Circuit for Clocked Level Shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clocked level shifter. In particular, the clock signal of the clock level shifter is directly applied to the level shifter to speed up the access time tAC, and the data output according to the command is output to the clock. The present invention relates to a clocked level shifter that is synchronized and operates normally.

The level shifter is a circuit used when a voltage output larger than an input voltage signal is required in a driver section or word line. That is, a circuit for drawing a power supply voltage or a substrate voltage to an output terminal in response to a predetermined voltage signal having a small potential difference between a high level signal and a low level signal.

In general, a clocked level shifter is a level shifter used in synchronous dynamic random access memory (SDRAM) and refers to a level shifter that outputs a voltage shifted to a power supply voltage or a substrate voltage when synchronized with a clock.

Hereinafter, a conventional clocked level shifter will be described in detail with reference to the accompanying drawings.

The conventional clocked level shifter includes a controller 100, a level shifter 200, and an inverter 300.

The controller 100 may include a NOR gate NOR for performing a logic operation on a clock signal clk and a latch disable signal dis_latch applied externally, and a first inverter for inverting an output of the NOR gate NOR. NV1), a NAND gate NAND for performing a logic operation on an externally applied data signal and an enable signal, and an output of the NOR gate NOR to a PMOS transistor to the first inverter NV1. ) Is applied to the NMOS transistor to invert the output of the NAND gate (NAND), the first clock inverter (CNV1), and the second inverter (NV2) to invert the output of the first clock inverter (CNV1); The output of the first inverter NV1 is applied to the PMOS transistor and the output of the NOR gate NOR is applied to the NMOS transistor, thereby inverting the output of the second inverter NV2 and again the first clock inverter CNV1. ) And the second furnace (NV2) connection furnace The second clock inverter CNV2 is applied to the drawing.

The first clock inverter CNV1 or the second clock inverter CNV2 are selectively driven according to the output of the NOR gate NOR and the first inverter NV1 of the controller 100. That is, when the output of the NOR gate NOR is at a high level (that is, the output of the first inverter is at a low level), the output of the NOR gate NOR is at a low level by responding to the second clock inverter CNV2. If the output of the first inverter is a high level), the result of the controller 100 is output by responding to the first clock inverter CNV1.

The controller 100 determines the output signal of the controller 100 by calculating a data signal and an enable signal (data, enable) according to selection of the first and second clock inverters CNV1 and CNV2.

That is, when the output of the NOR gate NOR is at a low level, the first clock inverter CNV1 is driven, and therefore, the output of the NAND gate NAND passes through two inverters, so that the output signal of the controller 100 is generated. The output of the NAND gate is applied as it is.

In addition, when the output of the NOR gate NOR is at a high level, the second clock inverter CNV2 is driven, and since the first clock inverter CNV1 is turned off, the result of the NAND gate NAND is controlled by the controller ( 100) Can not affect the output.

At this time, the second clock inverter CNV2 and the second inverter NV2 have a form in which the inverters are circulated and connected to each other to serve as a latch. Therefore, the output (out) of the clocked level shifter is kept at the previous output (out0).

That is, the controller 100 determines whether to latch according to a result of the NOR gate NOR that logically computes the clock signal clk and the latch disable signal dis_latch. The output of the controller 100 changed according to the result of the NAND gate NAND having the enable signals data and enable is applied to the level shifter 200.

The level shifter 200 includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a power supply voltage Vdd connected in series between a power supply voltage Vdd and an output terminal N1 of the controller. ) And a second PMOS transistor PM2 and a second NMOS transistor NM2 connected in series between the ground voltage Vss and the first and second PMOS transistors PM1 and PM2, respectively. It has a cross coupled structure in which gates are connected to drains of each other.

In addition, the first NMOS transistor NM1 is controlled by a power supply voltage Vdd, and the second NMOS transistor NM2 is connected to and controlled by an output terminal N1 of the controller.

As described above, the result of the output terminal N1 of the control unit 100 maintains the previous state when it is in the latched state, and otherwise logically computes the data signal and the enable signal. It is controlled by the result of the NAND gate.

That is, when the node N1 is at the low level (the result of the NAND gate is low level), since the first NMOS transistor NM1 is always turned on, the first and second PMOS transistors PM1 and PM2 are connected to each other. The state of the connection node N2 goes low. Accordingly, the second PMOS transistor PM2 is turned on, and the connection node N3 of the second PMOS transistor and the second NMOS transistors PM2 and NM2 is at a high level. At this time, the first PMOS transistor PM1 is turned off, and the output of the level shifter 200 becomes a high level as a result of the node N3.

On the contrary, when node N1 is at a high level, the first and second NMOS transistors NM1 and NM2 are turned on. Thus, the state of node N3 is at a low level, and the state of node N2 is at a high level. That is, the output of the level shifter 200 is maintained at a low level.

The inverting unit 300 includes one third inverter NV3 that inverts the output (state of node N3) of the level shifter 200. In this way, the value output through the third inverter NV3 is the level shifting signal out.

The operation of the entire clocked level shifter is controlled according to the output of the controller 100. When the result of the controller 100 is a high level, a low level is output through the level shifter 200, and the inverted level is outputted. The high level is output through the third inverter NV3.

On the other hand, when the output of the controller 100 is at a low level, the low level is output through the level shifter 200 and the inverter 300.

As a result, the conventional clocked level shifter assumes that the enable signal is a high level signal, and when the latch disable signal dis_latch is high, the level shifting voltage of the data signal data regardless of the clock signal clk ( out), and when the latch disable signal dis_latch is in a low state, the level shifting voltage out of the data signal data is output in synchronization with the clock signal clk.

However, the conventional clocked level shifter as described above has the following problems.

First, the controller of the conventional clocked level shifter selectively applies a data signal by determining whether the latch is in a latch state by applying a clock and a latch disable signal. When the data signal is applied after the determination of the latch is completed during this process, a delay time is generated, and subsequent level shifting operations do not occur in synchronization with the clock.

Second, since the level shifter part of the conventional clocked level shifter is always turned on, if the signal applied from the controller is in a floating state, the output end also cannot output a stable signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the clock signal of the clock level shifter is directly applied to the level shifter to speed up the access time tAC, and the data output according to the command is synchronized with the clock to be normal. It is an object to provide a clocked level shifter to operate.

1 is a circuit diagram showing a conventional clocked level shifter

2 is a circuit diagram illustrating a clocked level shifter of the present invention.

Description of the main parts of the drawing

clk: Clock signal dis_latch: Latch disable signal

data: Data signal enable: Enable signal

/ latch: latch bar signal / data: data bar signal

out: Clock level shifting signal

Clocked level shifter of the present invention for achieving the above object is a clock signal portion for outputting the latch bar signal in response to the clock signal and the latch disable signal applied from the outside, and the data signal and enable applied from the outside A data signal portion outputting a data bar signal in response to the signal, a level shifter portion directly controlled by the latch bar signal to output a level shifting signal of the data bar signal, and a clock level shifting signal by inverting the level shifting signal. And an inverting unit for outputting the signal and applying the clock level shifting signal to the output terminal of the level shifter unit to perform a latch function.

Hereinafter, the clocked level shifter of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a clocked level shifter of the present invention.

As shown in FIG. 2, the clocked level shifter of the present invention includes a clock signal unit 400, a data signal unit 500, a level shifter unit 600, and a latch unit 700.

The clock signal unit 400 inverts the output of the NOR gate NOR and the NOR gate NOR, which are negatively input by inputting a clock signal clk and a latch disable signal dis_latch, respectively, applied from the outside. The first inverter NV1 outputs the latch bar signal / latch.

The data signal unit 500 includes a data signal data applied from the outside and a NAND gate NAND for outputting a data bar signal / data by performing a negative logic on an enable signal.

The level shifter unit 600 includes a first NMOS transistor NM1 applying the latch bar signal / latch to a gate (N1), and applying a ground voltage Vss to a source, and the data bar signal. a second NMOS transistor NM2 having (/ data) applied to a gate (N2) and having a drain N3 output of the first NMOS transistor NM1 connected to a source, and the latch bar signal / latch Is applied to the gate (N1), the data bar signal (/ data) is applied to the source (N2) of the third NMOS transistor (NM3) and the drain (N4 (of the second NMOS transistor (NM2)) A fourth NMOS transistor NM4 having an output applied to the gate, a ground voltage Vss applied to the source, and connected to a drain N5 of the third NMOS transistor NM3 and its own drain; The output of the drain N5 of the 2 NMOS transistor NM2 is applied to the gate, and the power supply voltage Vdd is applied to the source. The first PMOS transistor PM1 connected to the drain N5 of the fourth NMOS transistors NM3 and NM4 and the drain thereof and the first PMOS transistor PM2 are cross-coupled with each other to form the third and fourth transistors. The output of the drain N5 of the NMOS transistors NM3 and NM4 is applied to the gate, the power supply voltage Vdd is applied to the source, and is connected to the drain N4 of the second NMOS transistor NM2 to level shift. The second PMOS transistor PM2 outputs a voltage to the drain.

The latch unit 700 receives a level shifting voltage that is an output of the level shifter 600, inverts the level shifting voltage, and outputs a clock level shifting voltage out to the latch inverter 700. And a third inverter NV3 connected to NV2 to be applied to the output terminal N4 of the level shifter 600 again to maintain the clock level shifting voltage out until the next clock application.

The conventional control unit is divided into a clock signal unit 400 and a data signal unit 500 of the present invention.

As described above, the output of the level shifter 600 is controlled according to the output of the clock signal 400 and the data signal 500. The level shifter 600 is a kind of inverting buffer type voltage level shifter.

The clock signal clk is applied to output the voltage shifted in synchronization with the clock signal clk.

The latch disable signal dis_latch is a kind of control signal. When the latch disable signal dis_latch is a high level, the clocked level shifter of the present invention does not achieve a latch state, and accordingly to the clock level shifting voltage out according to the enabled data signal data. At the low level, the output state is determined in synchronization with the clock signal clk.

The data signal data refers to data to be read from the outside at the time of a read command.

The enable signal at this time is a signal that allows the data signal data to be applied to the level shifter 600. That is, when the enable signal is at a high level, the data signal data is applied to the level shifter 600.

The operation of the present invention after the level shifter 600 according to the output (/ latch) change of the clock signal unit 400 will be described in detail as follows.

First, when the latch bar signal / latch which is the output of the clock signal unit 400 is at the low level, the first and third NMOS transistors receiving the output (/ latch) of the clock signal unit 400 are applied. NM1 and NM3 are turned on, that is, the connection state of the node N4 and the second NMOS transistor NM2 and the connection state of the node N5 and the third NMOS transistor NM3 are disconnected. Accordingly, the second and third inverters NV2 and NV3 are in a latched state and maintain all signals.

Second, when the latch bar signal / latch is at a high level, the third NMOS transistor NM3 receiving the latch bar signal / latch is turned on so that the signal / data of the node N2 is applied to the drain terminal N5 as it is. do. In addition, the first NMOS transistor NM1 is also turned on to apply a low level signal to the node N3.

At this time, when the data bar signal / data, which is the output of the data signal unit 500, is at a high level, a high level is applied to the node N2, and the node N5 is also at a high level. Thus, the second PMOS transistor PM2 is turned off. The second NMOS transistor NM2 also receives a high level signal and applies a low level signal, which is an output of the node N3, to the drain terminal node N4. Thus, the output of the level shifter 600 is in a low level state.

On the other hand, when the data bar signal / data is at the low level, a low level is applied to the node N2, and the node N5 is also at a low level. Accordingly, the second PMOS transistor PM2 is turned on, whereby the high voltage signal Vdd is applied to the node N4.

That is, the level shifter 600 is controlled by the latch bar signal / latch to output a signal of the inverted level to the data bar signal / data which is the output of the data signal unit 500.

The latch unit 700 first inverts the output (level shifting signal) of the node N4 and outputs it as a clock level shifting signal out which is the entire output of the clocked level shifter of the present invention. Then, it is inverted again and applied to the node N4, thereby maintaining the output until the next clock signal is applied. That is, the latch state is achieved until the next clock signal is applied.

The clocked level shifter of the present invention outputs the clock level shifting voltage out of the applied data signal data regardless of the clock signal clk when the latch disable signal dis_latch is high, and disables the latch. When the signal dis_latch is in a low state, the clock level shifting voltage out of the data signal data is output in synchronization with the clock signal clk.

In the overall circuit, when the latch bar signal / latch is at a high level through the clock signal unit 400, the data bar signal / data from the data signal unit 500 is directly transferred to the level shifter 600. A signal having the same level as the data bar signal / data is applied to the output of the entire clock level shifter through the inversion unit 700.

The total output out of the clock level shifter is a level inverted output in terms of the data signal that is the input signal of the clock level shifter (assuming that the enable signal is high level).

The clocked level shifter of the present invention is a method for improving output data access time from tlk (tAC) according to clock speed, and reduces the number of elements in the conventional control unit and the clock signal unit so that the data output according to the command is synchronized with the clock. It was configured to be applied directly to the level shifter.

The clocked level shifter as described above has the following effects.

First, compared to the conventional clocked level shifter, the number of logic elements can be reduced to prevent delay in voltage output. That is, the access time (tAC: Output Data Access Time From Clk) can be reduced.

Second, the control unit is dualized into a clock signal unit and a data signal unit so that the clock signal unit directly controls the level shifter unit. This can directly output a clock level shifting signal that is completely synchronized with the clock signal by directly applying a clock signal to the level shifter and outputting a level shifted signal. In this way, when the voltage is supplied in synchronization with the clock signal, unnecessary power consumption can be prevented.

Third, the latch function can be implemented more stably and simply by transferring the latch function to the level shifter and the inverter.

Fourth, by connecting a transistor having a source connected to a ground voltage to an input terminal of the level shifter, a stable value can be output compared to a conventional node in a floating state.

Fifth, the output of the level shifter is inverted through the inverter to come out as a clock level shifting output. In this case, an inverter may be added to the inverter to add a latch function to output data with a stable value for a predetermined time.

Claims (6)

A clock signal unit configured to output a latch bar signal in response to the clock signal and a latch disable signal applied from the outside; A data signal unit configured to output a data bar signal in response to an externally applied data signal and an enable signal; A level shifter unit which is directly controlled by the latch bar signal and outputs a level shifting signal of the data bar signal; And an inverting unit for inverting the level shifting signal to output a clock level shifting signal and applying the clock level shifting signal to an output terminal of the level shifter unit to perform a latch function. The method of claim 1, wherein the clock signal unit, And a first inverter configured to output a latch bar signal by inverting an output of the NOR gate by inputting a clock signal and a latch disable signal applied externally, and inverting an output of the NOR gate. The method of claim 1, wherein the data signal unit, And a NAND gate configured to output a data bar signal by negatively multiplying an externally applied data signal and an enable signal. The method of claim 1, wherein the level shifter unit, And the latch bar signal is driven when the latch bar signal is at a high level, and performs a latch operation when the latch bar signal is at a high level. The method of claim 1, wherein the level shifter unit, A first NMOS transistor applying the latch bar signal to a gate and applying a ground voltage to a source; A second NMOS transistor configured to apply the data bar signal to a gate and connect a drain output of the first NMOS transistor to a source; A third NMOS transistor applying the latch bar signal to a gate and applying the data bar signal to a source; A fourth NMOS transistor which applies a drain output of the second NMOS transistor to a gate, applies a ground voltage to a source, and connects the drain of the third NMOS transistor to its drain; A first PMOS transistor applying a drain output of the second NMOS transistor to a gate, a power supply voltage to a source, and a drain of the third and fourth NMOS transistors connected to a drain thereof; A voltage cross-coupled with the second PMOS transistor to apply a drain output of the third and fourth NMOS transistors to a gate, apply a power supply voltage to a source, and shift the voltage connected to the drain of the second NMOS transistor And a second PMOS transistor for outputting the drain to the drain. The method of claim 1, wherein the latch unit, A second inverter receiving the level shifting signal and inverting the level shifting signal to output a clock level shifting signal; and inverting the clock level shifting signal and applying the level shifting signal to an output terminal of the level shifting signal again, and applying the level shifting signal to a next clock signal. And a third inverter for holding until applied.