CN105743466B - A kind of adjustable hysteresis comparator applied to wireless charging control chip - Google Patents
A kind of adjustable hysteresis comparator applied to wireless charging control chip Download PDFInfo
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- CN105743466B CN105743466B CN201610069798.4A CN201610069798A CN105743466B CN 105743466 B CN105743466 B CN 105743466B CN 201610069798 A CN201610069798 A CN 201610069798A CN 105743466 B CN105743466 B CN 105743466B
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- nmos tube
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- source electrode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
Abstract
The present invention discloses a kind of adjustable hysteresis comparator applied to wireless charging control chip,It includes PMOS tube P0,PMOS tube P1,PMOS tube P2,PMOS tube P3,PMOS tube P4,NMOS tube N0,NMOS tube N1,NMOS tube N2,NMOS tube N3,NMOS tube N4,NMOS tube N5,NMOS tube N6,NMOS tube N7,NMOS tube N8,NMOS tube N9,NMOS tube N10,NMOS tube N11,NMOS tube N12,NMOS tube N13,First operational amplifier,Second operational amplifier,Comparator,Resistance R0,Resistance R1,Switch K0,Switch K1,Switch K2,Switch K3 and wireless charging control chip,Wherein switch K0,K1,K2,K3 is closed or is disconnected by the Logic control module control of wireless charging control chip.
Description
Technical field
The invention belongs to electronic circuit technology fields, and in particular to a kind of hysteresis comparator.
Background technology
Existing hysteresis comparator generally realizes magnetic hysteresis using modes such as feedback signal short-circuit resistance, electric current positive and negative feedbacks
Function, but variation of ambient temperature or technique imbalance, easily cause hysteresis voltage drift, are not suitable for accurate magnetic hysteresis and compare.
Invention content
Therefore, for above-mentioned problem, the present invention proposes a kind of adjustable magnetic hysteresis ratio applied to wireless charging control chip
Compared with device, existing hysteresis comparator is improved, using temperature-compensating, technique offset compensation and adjustable hysteresis voltage technology,
So that the comparison threshold value of hysteresis comparator is realized can quantify to adjust, while not achieved accurate magnetic by temperature, technique offset influence
Stagnant comparison.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is that one kind being applied to wireless charging and controls
The adjustable hysteresis comparator of chip, including PMOS tube P0, PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube
N0, NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7, NMOS tube N8,
NMOS tube N9, NMOS tube N10, NMOS tube N11, NMOS tube N12, NMOS tube N13, the first operational amplifier, the second operation amplifier
Device, comparator, resistance R0, resistance R1, switch K0, switch K1, switch K2, switch K3 and wireless charging control chip, wherein opening
It closes K0, K1, K2, K3 to be closed or disconnect by the Logic control module control of wireless charging control chip, connection relation is as follows：
The positive input terminal of first operational amplifier connects power supply Vref, the source electrode of negative input end and NMOS tube N0, the first of resistance R0 defeated
Enter end connection, output end connects the grid of NMOS tube N0；The second input end grounding of resistance R0, the drain electrode connection of NMOS tube N0
The grid of PMOS tube P0 and drain electrode, the source electrode of PMOS tube P0, the source electrode of PMOS tube P1, the source electrode of PMOS tube P2, PMOS tube P3
The source electrode of source electrode and PMOS tube P4 are connected to power supply Vdd；The grid of PMOS tube P1 is connected with the grid of PMOS tube P0,
The grid of the drain electrode connection NMOS tube N1 of PMOS tube P1 and drain electrode, the grid of the source electrode connection NMOS tube N2 of NMOS tube N1 and leakage
Pole, the source electrode ground connection of NMOS tube N2；The grid of the grid connection NMOS tube N1 of NMOS tube N3, the grid of NMOS tube N5, NMOS tube
The grid of the grid and NMOS tube N9 of N7, the drain electrode of the source electrode connection NMOS tube N4 of NMOS tube N3, the drain electrode connection of NMOS tube N3
The drain electrode of NMOS tube N5, the drain electrode of NMOS tube N7, the drain electrode of NMOS tube N9, the drain and gate of PMOS tube P2, PMOS tube P3
The grid of grid and PMOS tube P4, the grid of the grid connection NMOS tube N2 of NMOS tube N4, grid, the NMOS tube N8 of NMOS tube N6
Grid and NMOS tube N10 grid, the source electrode of NMOS tube N4, the source electrode of NMOS tube N6, NMOS tube N8 source electrode and NMOS tube
The source electrode of N10 is grounded, the source electrode of the drain electrode connection NMOS tube N5 of NMOS tube N6, the source of the drain electrode connection NMOS tube N7 of NMOS tube N8
Pole, the source electrode of the drain electrode connection NMOS tube N9 of NMOS tube N10；The drain and gate of the drain electrode connection NMOS tube N11 of PMOS tube P3,
The grid of NMOS tube N13；The source electrode of NMOS tube N11 and the source electrode ground connection of NMOS tube N13, the drain electrode of NMOS tube N13 connect NMOS
The source electrode of pipe N12, drain electrode, the first input end of resistance R1 and the bearing for comparator of the drain electrode connection PMOS tube P5 of NMOS tube N12
Input terminal, the grid of the grid connection PMOS tube P5 of NMOS tube N12, the drain electrode of the source electrode connection PMOS tube P4 of PMOS tube P5；Electricity
Hinder the negative input end and output end of the second input terminal connection second operational amplifier of R1, the positive input terminal of second operational amplifier
Connect power supply Vref；The output of comparator is terminated at the grid of PMOS tube P5；Switch K0 is connected to the source of power supply Vdd and NMOS tube N3
Between pole, switch K1 is connected between power supply Vdd and the source electrode of NMOS tube N5, and switch K2 is connected to the source of power supply Vdd and NMOS tube N7
Between pole, switch K3 is connected between power supply Vdd and the source electrode of NMOS tube N9.
In foregoing circuit, R0=R1 namely resistance R0 are identical with resistance R1, are specifically identical size, mutually similar
The resistance of type, temperature coefficient having the same, if temperature change, the influence that temperature causes change in resistance to generate will be cancelled；Electricity
The resistance R0 and resistance R1 influences that change in resistance generates caused by technique is lacked of proper care can be also cancelled.
The present invention through the above scheme, using temperature-compensating, technique offset compensation and adjustable hysteresis voltage technology, makes magnetic hysteresis
The comparison threshold value realization of comparator can quantify to adjust, while not compared relative to common magnetic hysteresis by temperature, technique offset influence
Device has accurately, not by temperature and the advantage of technique offset influence.Applied to wireless charging control chip, to demodulated signal into
Line sampling is adjudicated, and input voltage can be accurately compared, and by being programmed to wireless charging chip internal control registers, can adjust
Magnetic hysteresis compares turn threshold voltage.
Description of the drawings
Fig. 1 is one specific embodiment of adjustable hysteresis comparator of the present invention；
Fig. 2 is the oscillogram of the input voltage and output voltage of the adjustable hysteresis comparator of the present invention.
Specific implementation mode
In conjunction with the drawings and specific embodiments, the present invention is further described.
The present invention provides a kind of adjustable hysteresis comparator applied to wireless charging control chip.It is specific real as one
Example is applied, referring to Fig. 1, this is adjustable, and hysteresis comparator includes PMOS tube P0, PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube
P4, NMOS tube N0, NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7,
NMOS tube N8, NMOS tube N9, NMOS tube N10, NMOS tube N11, NMOS tube N12, NMOS tube N13, the first operational amplifier, second
Operational amplifier, comparator, resistance R0, resistance R1, switch K0, switch K1, switch K2, switch K3 and wireless charging control core
Piece, wherein switch K0, K1, K2, K3 are closed or are disconnected by the Logic control module control of wireless charging control chip, connection
Relationship is as follows：The positive input terminal of first operational amplifier connects power supply Vref, source electrode, the resistance R0 of negative input end and NMOS tube N0
First input end connection, output end connects the grid of NMOS tube N0；The second input end grounding of resistance R0, the leakage of NMOS tube N0
Pole connects grid and the drain electrode of PMOS tube P0, the source electrode of PMOS tube P0, the source electrode of PMOS tube P1, PMOS tube P2 source electrode, PMOS
The source electrode of pipe P3 and the source electrode of PMOS tube P4 are connected to power supply Vdd；The grid of PMOS tube P1 and the grid of PMOS tube P0 connect
Connect, the grid of the drain electrode connection NMOS tube N1 of PMOS tube P1 and drain electrode, the grid of the source electrode connection NMOS tube N2 of NMOS tube N1 and
Drain electrode, the source electrode ground connection of NMOS tube N2；The grid of the grid connection NMOS tube N1 of NMOS tube N3, grid, the NMOS of NMOS tube N5
The grid of the grid and NMOS tube N9 of pipe N7, the drain electrode of the source electrode connection NMOS tube N4 of NMOS tube N3, the drain electrode of NMOS tube N3 connect
Meet the drain electrode of NMOS tube N5, the drain electrode of NMOS tube N7, the drain electrode of NMOS tube N9, the drain and gate of PMOS tube P2, PMOS tube P3
Grid and PMOS tube P4 grid, the grid of the grid connection NMOS tube N2 of NMOS tube N4, the grid of NMOS tube N6, NMOS tube
The grid of the grid and NMOS tube N10 of N8, the source electrode of NMOS tube N4, the source electrode of NMOS tube N6, NMOS tube N8 source electrode and NMOS
The source electrode of pipe N10 is grounded, the source electrode of the drain electrode connection NMOS tube N5 of NMOS tube N6, the drain electrode connection NMOS tube N7's of NMOS tube N8
Source electrode, the source electrode of the drain electrode connection NMOS tube N9 of NMOS tube N10；The drain electrode of the drain electrode connection NMOS tube N11 of PMOS tube P3 and grid
Pole, NMOS tube N13 grid；The source electrode of NMOS tube N11 and the source electrode ground connection of NMOS tube N13, the drain electrode connection of NMOS tube N13
The source electrode of NMOS tube N12, the drain electrode of the drain electrode connection PMOS tube P5 of NMOS tube N12, the first input end and comparator of resistance R1
Negative input end, the grid of the grid connection PMOS tube P5 of NMOS tube N12, the leakage of the source electrode connection PMOS tube P4 of PMOS tube P5
Pole；The negative input end and output end of the second input terminal connection second operational amplifier of resistance R1, second operational amplifier is just
Input terminal connects power supply Vref；The output of comparator is terminated at the grid of PMOS tube P5；Switch K0 is connected to power supply Vdd and NMOS tube
Between the source electrode of N3, switch K1 is connected between power supply Vdd and the source electrode of NMOS tube N5, and switch K2 is connected to power supply Vdd and NMOS tube
Between the source electrode of N7, switch K3 is connected between power supply Vdd and the source electrode of NMOS tube N9.
In Fig. 1, P0, P1, P2, P3, P4 is PMOS tube；N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11,
N12, N13 are NMOS tube；100 be the first operational amplifier, and 101 be second operational amplifier；102 be comparator；R0, R1 are
Resistance；K0, K1, K2, K3 are that switch (enables K=0, is closed；K=1, open circuit)；Remember (W/L)N(n-1)For the breadth length ratio of n-th of NMOS,
(n=1,2,3 ...)；Remember (W/L)P(n-1)For the breadth length ratio of n-th of PMOS, (n=1,2,3 ...).
Following breadth length ratio is set：
(W/L)P0=16* (W/L)P1
(W/L)N1=16* (W/L)N3=16* (W/L)N5=16* (W/L)N7=16* (W/L)N9
(W/L)N2=16* (W/L)N4=16* (W/L)N6=16* (W/L)N8=16* (W/L)N10
(W/L)P2=(W/L)P3=(W/L)P4
(W/L)N11=(W/L)N13
It can be obtained by circuit：
IR0=Vref/R0,
IP1=IP0/ 16,
IP2=IP3=IN11,
Work as Hysout=0, IP4=IP2,VHysinn=Vref+IP4*R1=Vref+IP2*R1
Work as Hysout=1, IN13=IN11=IP3=IP2,VHysinn=Vref-IN13*R1=Vref-IP2*R1
If R0=R1, then：
(1) when switch K0, K1, K2, K3 are all closed
K0+K1+K2+K3=0, IP2=0；
(2) when wherein three closures of switch K0, K1, K2, K3, a disconnection
K0+K1+K2+K3=1, IP2=IN1* (1/16)=IP1* (1/16)=(IP0/16)*(1/16)
=(IR0/16)*(1/16)IR0=(Vref/R0)*(1/256)；
(3) when switch K0, K1, K2, K3 two of which closure, two disconnections
K0+K1+K2+K3=2, IP2=IN1* (2/16)=IP1* (2/16)=(IP0/16)*(2/16)
=(IR0/16)*(2/16)IR0=(Vref/R0)*(2/256)；
(4) it is closed when switch K0, K1, K2, K3 are one of, three disconnections
K0+K1+K2+K3=3, IP2=IN1* (3/16)=IP1* (3/16)=(IP0/16)*(3/16)
=(IR0/16)*(3/16)IR0=(Vref/R0)*(3/256)；
(5) when switch K0, K1, K2, K3 are wherein all off
K0+K1+K2+K3=4, IP2=IN1* (4/16)=IP1* (4/16)=(IP0/16)*(4/16)
=(IR0/16)*(4/16)IR0=(Vref/R0)*(4/256)；
So obtain following relational expression：
(1) when comparator 102 exports low level
Hysout=L,
K0+K1+K2+K3=0, VHysinn=Vref；
K0+K1+K2+K3=1, VHysinn=Vref*(1+1/256)；
K0+K1+K2+K3=2, VHysinn=Vref*(1+2/256)；
K0+K1+K2+K3=3, VHysinn=Vref*(1+3/256)；
K0+K1+K2+K3=4, VHysinn=Vref*(1+4/256)；
(2) when comparator 102 exports high level
Hysout=H,
K0+K1+K2+K3=0, VHysinn=Vref；
K0+K1+K2+K3=1, VHysinn=Vref*(1-1/256)；
K0+K1+K2+K3=2, VHysinn=Vref*(1-2/256)；
K0+K1+K2+K3=3, VHysinn=Vref*(1-3/256)；
K0+K1+K2+K3=4, VHysinn=Vref*(1-4/256)；
Then it is described as follows with table：
(1) when comparator 102 exports low level, i.e. Hysout=L
| K0+K1+K2+K3 | 0 | 1 | 2 | 3 | 4 |
| VHysinn | Vref | Vref*(1+1/256) | Vref*(1+2/256) | Vref*(1+2/256) | Vref*(1+4/256) |
(2) when comparator 102 exports high level, i.e. Hysout=H
| K0+K1+K2+K3 | 0 | 1 | 2 | 3 | 4 |
| VHysinn | Vref | Vref*(1-1/256) | Vref*(1-2/256) | Vref*(1-3/256) | Vref*(1-4/256) |
As shown in Fig. 2, original state, 102 positive input terminal voltage V of comparatorHysinp=0, comparator 102 negative input end electricity
Press VHysinn=Vref* (1+k/256), (k=K0+K1+K2+K3), 102 output end voltage V of comparatorHysout=L (low level)；
102 positive input terminal voltage V of comparatorHysinpConstantly increase, when 102 positive input terminal voltage of comparator is more than negative input
Terminal voltage, that is, VHysinp>VHysinn, VHysinp>Vref* (1+k/256), then 102 output end V of comparatorHysout=H (high level), than
Compared with 102 negative input end V of deviceHysinnBecome Vref* (1-k/256), (k=K0+K1+K2+K3), i.e. VHysinn1=Vref*(1-k/
256), (k=K0+K1+K2+K3)；
102 positive input terminal voltage of comparator is more than negative input end voltage, that is, VHysinp>VHysinnLater, comparator 102 is just defeated
Enter to hold VHysinpConstantly reduce, works as VHysinp<VHysinn1That is VHysinp<Vref* (1-k/256), then 102 output end V of comparatorHysout
=L (low level), 102 negative input end V of comparatorHhysinnBecome Vref* (1+k/256), (k=K0+K1+K2+K3), i.e. VHysinn2
=Vref* (1+k/256), (k=K0+K1+K2+K3)；It exports schematic diagram referring to Fig. 2.
102 negative input end hysteresis voltage Δ V of comparatorHys=VHysinn2-VHysinn1=2*Vref*(k/256)。
In foregoing circuit, resistance R0 and the resistance that resistance R1 is identical size, same type, temperature system having the same
Number, if temperature change, the influence that temperature causes change in resistance to generate will be cancelled；Resistance R0 and resistance R1 causes because of technique imbalance
Change in resistance generate influence can also be cancelled.
The present invention controls the closure of K0, K1, K2, K3 switch by the Logic control module of wireless charging control chip or breaks
It opens, hysteresis voltage can be adjusted in real time.
This patent uses temperature-compensating, technique offset compensation and adjustable hysteresis voltage technology, makes the comparison of hysteresis comparator
Threshold value realization can quantify to adjust, while not had accurately, no relative to common hysteresis comparator by temperature, technique offset influence
By temperature and the advantage of technique offset influence.
Although specifically showing and describing the present invention in conjunction with preferred embodiment, those skilled in the art should be bright
In vain, it is not departing from the spirit and scope of the present invention defined by the appended claims, it in the form and details can be right
The present invention makes a variety of changes, and is protection scope of the present invention.
Claims (3)
1. a kind of adjustable hysteresis comparator applied to wireless charging control chip, it is characterised in that：Including PMOS tube P0, PMOS
Pipe P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube N0, NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4,
NMOS tube N5, NMOS tube N6, NMOS tube N7, NMOS tube N8, NMOS tube N9, NMOS tube N10, NMOS tube N11, NMOS tube N12,
NMOS tube N13, the first operational amplifier, second operational amplifier, comparator, resistance R0, resistance R1, switch K0, switch K1 are opened
K2, switch K3 and wireless charging control chip are closed, wherein the logic control that switch K0, K1, K2, K3 pass through wireless charging control chip
The control of molding block is closed or disconnects, and connection relation is as follows：The positive input terminal of first operational amplifier connects power supply Vref, bears defeated
Enter end to connect with the first input end of the source electrode of NMOS tube N0, resistance R0, output end connects the grid of NMOS tube N0；Resistance R0's
Second input end grounding, the grid of the drain electrode connection PMOS tube P0 of NMOS tube N0 and drain electrode, source electrode, the PMOS tube P1 of PMOS tube P0
Source electrode, the source electrode of PMOS tube P2, the source electrode of PMOS tube P3 and PMOS tube P4 source electrode be connected to power supply Vdd；PMOS tube
The grid of P1 is connected with the grid of PMOS tube P0, the grid of the drain electrode connection NMOS tube N1 of PMOS tube P1 and drain electrode, NMOS tube N1
Source electrode connection NMOS tube N2 grid and drain electrode, the source electrode ground connection of NMOS tube N2；The grid connection NMOS tube N1 of NMOS tube N3
Grid, the grid of NMOS tube N5, NMOS tube N7 grid and NMOS tube N9 grid, the source electrode of NMOS tube N3 connects NMOS tube
The drain electrode of N4, the drain electrode of the drain electrode connection NMOS tube N5 of NMOS tube N3, the drain electrode of NMOS tube N7, the drain electrode of NMOS tube N9, PMOS
The grid of the drain and gate of pipe P2, the grid and PMOS tube P4 of PMOS tube P3, the grid connection NMOS tube N2's of NMOS tube N4
The grid of grid, the grid of NMOS tube N6, the grid of NMOS tube N8 and NMOS tube N10, the source electrode of NMOS tube N4, NMOS tube N6
The source electrode of source electrode, the source electrode of NMOS tube N8 and NMOS tube N10 is grounded, the source electrode of the drain electrode connection NMOS tube N5 of NMOS tube N6,
The source electrode of the drain electrode connection NMOS tube N7 of NMOS tube N8, the source electrode of the drain electrode connection NMOS tube N9 of NMOS tube N10；PMOS tube P3's
The drain and gate of drain electrode connection NMOS tube N11, the grid of NMOS tube N13；The source of the source electrode and NMOS tube N13 of NMOS tube N11
Pole is grounded, the source electrode of the drain electrode connection NMOS tube N12 of NMOS tube N13, the drain electrode of the drain electrode connection PMOS tube P5 of NMOS tube N12,
The first input end of resistance R1 and the negative input end of comparator, the grid of the grid connection PMOS tube P5 of NMOS tube N12, PMOS tube
The drain electrode of the source electrode connection PMOS tube P4 of P5；The second input terminal connection negative input end of second operational amplifier of resistance R1 and defeated
Outlet, the positive input terminal connection power supply Vref of second operational amplifier；The output of comparator is terminated at the grid of PMOS tube P5；It opens
It closes K0 to be connected between power supply Vdd and the source electrode of NMOS tube N3, switch K1 is connected between power supply Vdd and the source electrode of NMOS tube N5, is opened
It closes K2 to be connected between power supply Vdd and the source electrode of NMOS tube N7, switch K3 is connected between power supply Vdd and the source electrode of NMOS tube N9.
2. adjustable hysteresis comparator according to claim 1, it is characterised in that：R0=R1, the R0=R1 refer to resistance
R0 is identical with resistance R1, is specifically the resistance of identical size, same type, temperature coefficient having the same.
3. adjustable hysteresis comparator according to claim 1 or 2, it is characterised in that：Remember (W/L)N(n-1)For n-th of NMOS
Breadth length ratio, n=1,2,3 ...；Remember (W/L)P(n-1)For the breadth length ratio of n-th of PMOS, n=1,2,3 ..., it is described (W/L)N(n-1)In
N refer to NMOS, it is described (W/L)P(n-1)In P refer to PMOS, then its breadth length ratio is arranged as follows：
(W/L)P0=16* (W/L)P1；
(W/L)N1=16* (W/L)N3=16* (W/L)N5=16* (W/L)N7=16* (W/L)N9；
(W/L)N2=16* (W/L)N4=16* (W/L)N6=16* (W/L)N8=16* (W/L)N10；
(W/L)P2=(W/L)P3=(W/L)P4；
(W/L)N11=(W/L)N13。
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610069798.4A CN105743466B (en) | 2016-02-01 | 2016-02-01 | A kind of adjustable hysteresis comparator applied to wireless charging control chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610069798.4A CN105743466B (en) | 2016-02-01 | 2016-02-01 | A kind of adjustable hysteresis comparator applied to wireless charging control chip |
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| CN105743466B true CN105743466B (en) | 2018-08-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1909369A (en) * | 2005-08-02 | 2007-02-07 | 三星电机株式会社 | Voltage comparator having hysteresis characteristics |
| US7973569B1 (en) * | 2010-03-17 | 2011-07-05 | Microchip Technology Incorporated | Offset calibration and precision hysteresis for a rail-rail comparator with large dynamic range |
| CN102386895A (en) * | 2010-08-26 | 2012-03-21 | 株式会社东芝 | Hysteresis comparator |
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2016
- 2016-02-01 CN CN201610069798.4A patent/CN105743466B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1909369A (en) * | 2005-08-02 | 2007-02-07 | 三星电机株式会社 | Voltage comparator having hysteresis characteristics |
| US7973569B1 (en) * | 2010-03-17 | 2011-07-05 | Microchip Technology Incorporated | Offset calibration and precision hysteresis for a rail-rail comparator with large dynamic range |
| CN102386895A (en) * | 2010-08-26 | 2012-03-21 | 株式会社东芝 | Hysteresis comparator |
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