CN105742281A - High-voltage electronic static discharge (ESD) protection device with positive-negative (PN) junction auxiliary trigger silicon controlled rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS) structure - Google Patents
High-voltage electronic static discharge (ESD) protection device with positive-negative (PN) junction auxiliary trigger silicon controlled rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS) structure Download PDFInfo
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- CN105742281A CN105742281A CN201610189737.1A CN201610189737A CN105742281A CN 105742281 A CN105742281 A CN 105742281A CN 201610189737 A CN201610189737 A CN 201610189737A CN 105742281 A CN105742281 A CN 105742281A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 16
- 239000010703 silicon Substances 0.000 title claims abstract description 16
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000003068 static effect Effects 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000000694 effects Effects 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 7
- 238000012913 prioritisation Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a high-voltage electronic static discharge (ESD) protection device with a positive-negative (PN) junction auxiliary trigger silicon controlled rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS) structure. The high-voltage ESD protection device comprises a P-type substrate, wherein a buried oxygen layer is arranged on the P-type substrate, a shift region is arranged on the buried oxygen layer, an N-buffer region, a P region and a P-body region are sequentially arranged on the shift region from left to right, a first drain heavily-doping N+ region and a first drain heavily-doping P+ region are sequentially arranged in the N-buffer region from left to right, a second source heavily-doping N+ region, a second source heavily-doping P+ region and a third source heavily-doping P+ region are sequentially arranged in the P-body region from left to right, and the P region and the second source heavily-doping P+ region are connected through a wire. When a drain of the ESD protection device encounters a positive ESD pulse, a reverse bias PN junction is used for helping improving the hole carrier concentration before trigger starting, and a trigger voltage V<t1> is reduced; and moreover, with the introduction of the reverse bias PN junction into the device, the positive and negative feedback effect of a parasitic SCR can be effectively prevented, thus, the maintaining voltage V<h> of the device can be effectively increased, and the latch-up effect of the device is prevented.
Description
Technical field
The present invention relates to electronic technology field, the high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure.
Background technology
Thyristor (Silicon Controlled Rectifier, SCR) receives significant attention because having stronger robustness in terms of ESD protection.But the LDMOS structure (SCR-LDMOS) being embedded into SCR structure also exists some fatal problem:
1, unlatching trigger voltage V of SCR-LDMOS devicet1The highest.SCR is by low-doped N trap and p-well avalanche breakdown, trigger voltage Vt1It is relatively higher than the grid oxide layer breakdown voltage of pin internal components, is unsatisfactory for the ESD protection requirement of device.
2, owing to there is NPN and PNP positive feedback effect in SCR-LDMOS device, maintains voltage VhThe lowest, the most only about 5V.Low maintenance voltage VhThe power consumption turned on when releasing ESD electric current can be reduced, but be used as the ESD protection of power pin, except requiring trigger voltage Vt1Outside higher than power vd D, maintain voltage VhNeed too higher than VDD.If maintaining voltage VhLess than chip VDD, the most easily produce latch phenomenon.
Summary of the invention
The technical problem to be solved is to overcome the deficiencies in the prior art to provide the high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure, and the PN junction auxiliary triggering SCR-LDMOS structure entirety ESD protection capability of the present invention is greatly improved.
The present invention solves above-mentioned technical problem by the following technical solutions:
High-voltage ESD protective device according to a kind of PN junction auxiliary triggering SCR-LDMOS structure that the present invention proposes; including P-type silicon substrate; described P-type silicon substrate is provided with oxygen buried layer, and oxygen buried layer is provided with drift region, and the top of drift region is from left to right sequentially provided with N-buffer district, P district, P-body district；Described N-buffer district is from left to right sequentially provided with the first drain electrode heavy doping N+ district and the first drain electrode heavy doping P+ district；Described P-body district is from left to right sequentially provided with the second source electrode heavy doping N+ district, the second source electrode heavy doping P+ district and the 3rd source electrode heavy doping P+ district；It is provided with the first thin oxide layer between first drain electrode heavy doping P+ district and P district, the second thin oxide layer it is provided with between P district and P-body district, it is provided with the 3rd thin oxide layer between second source electrode heavy doping N+ district and the second source electrode heavy doping P+ district, between the second source electrode heavy doping P+ district and the 3rd source electrode heavy doping P+ district, is provided with the 4th thin oxide layer；Be provided with channel region between P-body district and the second source electrode heavy doping N+ district, channel region be arranged over polysilicon gate, and polysilicon gate extends to the upper surface of the second thin oxide layer；First drain electrode heavy doping N+ district is connected by wire with the first drain electrode heavy doping P+ district；P district is connected by wire with the second source electrode heavy doping P+ district；Polysilicon gate, the second source electrode heavy doping N+ district, the 3rd equal ground connection in source electrode heavy doping P+ district.
As the further prioritization scheme of high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure of the present invention, described P-type silicon substrate is SOI silicon substrate.
As the further prioritization scheme of high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure of the present invention, polysilicon gate, the second source electrode heavy doping N+ district, the 3rd source electrode heavy doping P+ district are all connected ground connection by wire.
As the further prioritization scheme of high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure of the present invention, the concentration in described P district and the concentration in P-body district are equal.
As the further prioritization scheme of high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure of the present invention, described P district is adjustable with the distance in P-body district.
The present invention uses above technical scheme compared with prior art, has following technical effect that the PN junction auxiliary triggering SCR-LDMOS structure entirety ESD protection capability of the present invention is greatly improved；Be mainly reflected in following some: first, trigger voltage Vt1Than conventional scr-LDMOS structure trigger voltage Vt1Reduce by 44.8%；Second, maintain voltage VhAlso twice is increased substantially many；3rd, secondary breakdown current It2It is greatly improved, is effectively improved the ESD robustness of device；4th, when protection between power supply and ground applied by device, the latch-up that chip causes can be avoided when normal work.
Accompanying drawing explanation
Fig. 1 is the high-voltage ESD protective device of conventional scr-LDMOS structure.
Fig. 2 is the high-voltage ESD protective device of the PN junction auxiliary triggering SCR-LDMOS structure of the present invention.
Reference in figure is construed to: 1-P type silicon substrate, 2-oxygen buried layer, 3-drift region, 5-N-buffer district, 4-P district, 8-P-body district, 7-first drains heavy doping N+ district, and 6-first drains heavy doping P+ district, 9-the second source electrode heavy doping N+ district, 10-the second source electrode heavy doping P+ district, 11-the 3rd source electrode heavy doping P+ district, 13-the first thin oxide layer, 14-the second thin oxide layer, 18-the 3rd thin oxide layer, 19-the 4th thin oxide layer, 16-channel region, 15-polysilicon gate, 12-the first wire, 17-the second wire, 20-privates.
Detailed description of the invention
Below in conjunction with the accompanying drawings technical scheme is described in further detail:
It is the high-voltage ESD protective device of PN junction auxiliary triggering SCR-LDMOS structure as shown in Figure 2; including P-type silicon substrate 1; described P-type silicon substrate is provided with oxygen buried layer 2, and oxygen buried layer is provided with drift region 3, and the top of drift region is from left to right sequentially provided with N-buffer district 5, P district 4, P-body district 8；Described N-buffer district 5 is from left to right sequentially provided with the first drain electrode heavy doping N+ district 7 and the first drain electrode heavy doping P+ district 6；Described P-body district 8 is from left to right sequentially provided with the second the 9, second source electrode heavy doping P+ district of source electrode heavy doping N+ district 10 and the 3rd source electrode heavy doping P+ district 11；It is provided with the first thin oxide layer 13 between first drain electrode district 4 of heavy doping P+ district 6 and P, the second thin oxide layer 14 it is provided with between district 8 of P district 4 and P-body, it is provided with the 3rd thin oxide layer 18 between second source electrode heavy doping N+ district 9 and the second source electrode heavy doping P+ district 10, between the second source electrode heavy doping P+ district 10 and the 3rd source electrode heavy doping P+ district 11, is provided with the 4th thin oxide layer 19；Be provided with channel region 16 between P-body district 8 and the second source electrode heavy doping N+ district 9, channel region 16 be arranged over polysilicon gate 15, and polysilicon gate 15 extends to the upper surface of the second thin oxide layer 14；First drain electrode heavy doping N+ district 7 is connected by the first wire 12 with the first drain electrode heavy doping P+ district 6；P district 4 is connected by the second wire 17 with the second source electrode heavy doping P+ district 10；Source electrode heavy doping P+ district of polysilicon gate the 15, second source electrode heavy doping N+ district the 9, the 3rd 11 is all by privates 20 ground connection.
N-buffer district, N relief area is N relief area, and P district 4 is adjustable with distance S in P-body district 8；Described P-type silicon substrate is SOI silicon substrate.Polysilicon gate, the second source electrode heavy doping N+ district, the 3rd source electrode heavy doping P+ district are all connected ground connection by wire.The concentration in described P district and the concentration in P-body district are equal.
Compared with the high-voltage ESD protective device of conventional SCR-LDMOS structure, innovation of the present invention is newly inserted P district, and is connected with source electrode P+ district wire.In conventional SCR-LDMOS structure, as shown in Figure 1, after drain electrode is by forward esd pulse, relying on horizontal reverse-biased N-epi/P-body and bind up one's hair to trigger after raw avalanche breakdown and open internal BJT, hole current is derived only from the holoe carrier that N-epi/P-body knot avalanche breakdown produces.And new device also has an other path producing holoe carrier except the holoe carrier that N-epi/P-body reverse biased junction produces.N-epi and the P district being newly introduced has equally constituted a back biased diode, there is big electric field in N-epi and P district depletion layer too and undertake portion voltage fall, and depletion layer internal electric field is higher, ionization coefficient is very big, so being more prone in the reverse-biased depletion layer in N-epi and P district avalanche breakdown.Afterwards, the holoe carrier that snowslide produces flows through P-body by the P+ being connected with P district and releases, and the pressure drop of P-body dead resistance can be promoted to be rapidly achieved NPN(and be made up of N-epi, P-body, source electrode N+) conducting voltage, accelerate device inside BJT and open.In other words, Novel SCR-LDMOS can produce more holoe carrier than conventional scr-LDMOS, produces higher pressure drop so that the electromotive force of base is higher, thus new device has only to lower V in P-body dead resistancet1Just can trigger unlatching endophyte BJT.
It is that the collector-base of NPN or the collector-base of PNP are maintained a relatively high magnitude of voltage that the another one advantage of this inventive structure is embodied in the another one effect of parasitic reverse-biased PN diode, can effectively suppress the positive feedback effect of parasitic SCR, thus the maintenance voltage V of device can be effectively improvedh, it is to avoid chip is used as, when power pin is protected, latch phenomenon occurs.
This inventive structure effectively reduces trigger voltage V compared with conventional scr-LDMOS structuret1, and maintain voltage VhAlso twice is improved many；The fully on rear multipath of device architecture is released ESD electric current, can be effectively improved the secondary breakdown current I of devicet2, strengthen the ESD robustness of device.
Structure in above-described embodiment, step, numerical value etc. are signal, and on the premise of not violating inventive concept, one of ordinary skill in the art can be replaced on an equal basis, it is also possible to makes some deformation and improvement, and these broadly fall into protection scope of the present invention.
Claims (5)
1. the high-voltage ESD protective device of a PN junction auxiliary triggering SCR-LDMOS structure; it is characterized in that, including P-type silicon substrate, described P-type silicon substrate is provided with oxygen buried layer; oxygen buried layer is provided with drift region, and the top of drift region is from left to right sequentially provided with N-buffer district, P district, P-body district；Described N-buffer district is from left to right sequentially provided with the first drain electrode heavy doping N+ district and the first drain electrode heavy doping P+ district；Described P-body district is from left to right sequentially provided with the second source electrode heavy doping N+ district, the second source electrode heavy doping P+ district and the 3rd source electrode heavy doping P+ district；It is provided with the first thin oxide layer between first drain electrode heavy doping P+ district and P district, the second thin oxide layer it is provided with between P district and P-body district, it is provided with the 3rd thin oxide layer between second source electrode heavy doping N+ district and the second source electrode heavy doping P+ district, between the second source electrode heavy doping P+ district and the 3rd source electrode heavy doping P+ district, is provided with the 4th thin oxide layer；Be provided with channel region between P-body district and the second source electrode heavy doping N+ district, channel region be arranged over polysilicon gate, and polysilicon gate extends to the upper surface of the second thin oxide layer；First drain electrode heavy doping N+ district is connected by wire with the first drain electrode heavy doping P+ district；P district is connected by wire with the second source electrode heavy doping P+ district；Polysilicon gate, the second source electrode heavy doping N+ district, the 3rd equal ground connection in source electrode heavy doping P+ district.
The high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure the most according to claim 1, it is characterised in that described P-type silicon substrate is SOI silicon substrate.
The high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure the most according to claim 1, it is characterised in that polysilicon gate, the second source electrode heavy doping N+ district, the 3rd source electrode heavy doping P+ district are all connected ground connection by wire.
The high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure the most according to claim 1, it is characterised in that the concentration in described P district and the concentration in P-body district are equal.
The high-voltage ESD protective device of a kind of PN junction auxiliary triggering SCR-LDMOS structure the most according to claim 1, it is characterised in that described P district is adjustable with the distance in P-body district.
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| CN201610189737.1A CN105742281B (en) | 2016-03-30 | 2016-03-30 | A kind of high-voltage ESD protective device of PN junction auxiliary triggering SCR-LDMOS structures |
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| CN201610189737.1A CN105742281B (en) | 2016-03-30 | 2016-03-30 | A kind of high-voltage ESD protective device of PN junction auxiliary triggering SCR-LDMOS structures |
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Cited By (6)
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| CN107946296A (en) * | 2017-10-23 | 2018-04-20 | 深圳震有科技股份有限公司 | A kind of electrostatic protection LEMDS_SCR devices |
| CN108649028A (en) * | 2018-05-22 | 2018-10-12 | 湖南大学 | electrostatic protection device |
| CN108766964A (en) * | 2018-05-18 | 2018-11-06 | 湖南大学 | LDMOS electrostatic protection devices |
| CN109244068A (en) * | 2018-08-29 | 2019-01-18 | 南京邮电大学 | A kind of LIGBT type high-voltage ESD protective device |
| CN109599395A (en) * | 2017-10-02 | 2019-04-09 | 新加坡商格罗方德半导体私人有限公司 | Esd protection circuit and its manufacturing method |
| CN111261627A (en) * | 2018-12-02 | 2020-06-09 | 南亚科技股份有限公司 | Semiconductor structure |
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| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN104637934A (en) * | 2013-11-08 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | ESD (electrostatic discharge) protection device |
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| CN103258814A (en) * | 2013-05-15 | 2013-08-21 | 电子科技大学 | LDMOS SCR for protection against integrated circuit chip ESD |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109599395A (en) * | 2017-10-02 | 2019-04-09 | 新加坡商格罗方德半导体私人有限公司 | Esd protection circuit and its manufacturing method |
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| CN107946296A (en) * | 2017-10-23 | 2018-04-20 | 深圳震有科技股份有限公司 | A kind of electrostatic protection LEMDS_SCR devices |
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| CN109244068A (en) * | 2018-08-29 | 2019-01-18 | 南京邮电大学 | A kind of LIGBT type high-voltage ESD protective device |
| CN109244068B (en) * | 2018-08-29 | 2020-11-03 | 南京邮电大学 | LIGBT type high-voltage ESD protection device |
| CN111261627A (en) * | 2018-12-02 | 2020-06-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN111261627B (en) * | 2018-12-02 | 2022-05-13 | 南亚科技股份有限公司 | Semiconductor structure |
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Inventor after: Cheng Jianbing Inventor after: Teng Guobing Inventor after: Chen Xudong Inventor after: Guo Houdong Inventor before: Teng Guobing Inventor before: Cheng Jianbing Inventor before: Chen Xudong Inventor before: Guo Houdong |
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Effective date of registration: 20190910 Address after: 243000 Pujian Standardized Factory Building, Zhengpugang New Area, Ma'anshan City, Anhui Province Patentee after: Anhui Longxin Micro Technology Co., Ltd. Address before: 210023 Jiangsu city of Nanjing province Ya Dong new Yuen Road No. 9 Patentee before: Nanjing Post & Telecommunication Univ. |