CN105742264A - Lead frame structure and semiconductor package thereof - Google Patents
Lead frame structure and semiconductor package thereof Download PDFInfo
- Publication number
- CN105742264A CN105742264A CN201410766780.0A CN201410766780A CN105742264A CN 105742264 A CN105742264 A CN 105742264A CN 201410766780 A CN201410766780 A CN 201410766780A CN 105742264 A CN105742264 A CN 105742264A
- Authority
- CN
- China
- Prior art keywords
- lead foot
- lead
- conductive platform
- frame structure
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 210000002683 foot Anatomy 0.000 claims description 117
- 239000000084 colloidal system Substances 0.000 claims description 6
- 238000012856 packing Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001737 promoting effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A lead frame structure and semiconductor package thereof, the lead frame structure includes a chip seat, a plurality of leads arranged around the chip seat, and a conductive platform arranged between the chip seat and the leads, for the semiconductor chip to connect on the chip seat and to be electrically connected to the leads and the conductive platform through bonding wires, and the conductive platform is electrically connected to a lead, so that the conductive platform replaces a plurality of power leads of the traditional lead frame structure.
Description
Technical field
The present invention relates to a kind of semiconductor package part, espespecially one wire-frame type semiconductor package part and conducting wire frame structure thereof.
Background technology
Existing wire-frame type semiconductor package part, by arranging a chip carrier (diepad) in the central authorities of lead frame, and it is arranged around multiple lead foot at this chip carrier, it is arranged on this chip carrier for semiconductor chip by the adhesion layer of such as elargol, followed by multiple bonding wires, semiconductor chip is electrically connected to the lead foot of this lead frame, it is coated with a part for this semiconductor chip, bonding wire, chip carrier and lead foot again with packing colloid, and removes unnecessary structure.So, the semiconductor chip after encapsulation can be electrically connected to the external world via bonding wire and lead foot.
Referring to Fig. 1, it is existing lead frame schematic diagram, and this lead frame 10 includes a chip carrier 11 and multiple lead foot 12 being located at around this chip carrier 11, and wherein those lead foots 12 can divide into again signal lead foot 121 and power supply lead foot 122.For promoting the electrical functionality of semiconductor package part, power supply lead foot quantity certainly will be set up, illustrate the lead foot B of Fig. 1, D, G, I are power supply lead foot (drawing the lead foot of oblique line in figure), and reality is as the outer contact of signal of semiconductor chip, namely signal lead foot, only surplus lead foot A, C, E, F, H.
But, too much power supply lead foot is arranged, by this signal lead foot quantity of reduction, and then the outer contact of signal of the I/O number of restriction semiconductor chip and semiconductor package part, this also makes the productive setization development of semiconductor chip and semiconductor package part be restricted.
Therefore, how to overcome the variety of problems of above-mentioned prior art, become the problem desiring most ardently solution at present in fact.
Summary of the invention
In view of the disappearance of above-mentioned prior art, the present invention provides a kind of conducting wire frame structure and semiconductor package part thereof, arranges through conductive platform, so that it replaces multiple power supply lead foots of conventional wires shelf structure.
The conducting wire frame structure of the present invention, including: a chip carrier, this chip carrier is used for connecing puts at least one semiconductor chip；Multiple lead foots, this lead foot is located at around this chip carrier, is electrically connected to this lead foot for semiconductor chip through bonding wire, and makes this semiconductor chip be electrically connected with the external world via bonding wire and lead foot；And at least one conductive platform, this conductive platform is located between this chip carrier and this lead foot, and this conductive platform has at least one protuberance, and this protruding parts is between adjacent two lead foots, and this protuberance is for being electrically connected with at least one lead foot.
The present invention also provides for a kind of semiconductor package part, including: a conducting wire frame structure；At least one semiconductor chip；And multiple bonding wire.
This conducting wire frame structure includes a chip carrier, multiple lead foot and at least one conductive platform.This lead foot is located at around this chip carrier；This conductive platform is located between this chip carrier and this lead foot, and this conductive platform has at least one protuberance, and this protruding parts is between adjacent two lead foots, and this protuberance is electrically connected to a lead foot through bonding wire.
This semiconductor chip is arranged on this chip carrier, and utilizes multiple bonding wire to be electrically connected to this lead foot and conductive platform, and wherein this conductive platform and its lead foot being electrically connected are the common power supply lead foot as conducting wire frame structure.Relatively can make in this conducting wire frame structure that most of lead foots are as signal lead foot, to meet the productive set purpose of semiconductor chip and semiconductor package part.
Additionally, the conducting wire frame structure of the present invention and semiconductor package part thereof also apply be applicable to Chip-on-Lead (COL) packaging part of centreless bar, through such as pi (Polyimide, semiconductor chip is engaged in lead foot by resin adhesive tape PI), then is electrically connected this semiconductor chip and this lead foot and conductive platform with bonding wire.
As from the foregoing, the conducting wire frame structure of the present invention and semiconductor package part thereof, arrange through conductive platform, and this conductive platform is electrically connected to a lead foot through bonding wire, so that this conductive platform replaces existing multiple power supply lead foots, and then make most of lead foots in lead frame all must as signal lead foot, the outer number of connections of signal to promote semiconductor chip and semiconductor package part, productive setization in order to semiconductor chip and semiconductor package part develops, and also must pass through this conductive platform and arrange the electrical quality promoting semiconductor chip and semiconductor package part.
Accompanying drawing explanation
Fig. 1 is the part plan schematic diagram of existing conducting wire frame structure；
Fig. 2 is the part plan schematic diagram of the conducting wire frame structure of the present invention；
Fig. 3 is the part plan schematic diagram of the semiconductor package part of the present invention；And
Fig. 4 is the generalized section of the conducting wire frame structure of the present invention and semiconductor package part thereof.
Primary clustering symbol description
10 lead frames
11 chip carriers
12 lead foots
121 signal lead foots
122 power supply lead foots
20 conducting wire frame structures
21 chip carriers
22 lead foots
23 conductive platform
230 protuberances
35 semiconductor chips
361 first bonding wires
362 second bonding wires
363 the 3rd bonding wires
42 lead foots
43 conductive platform
45 semiconductor chips
461 first bonding wires
462 second bonding wires
47 packing colloids.
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention being described below, those skilled in the art can be understood further advantage and effect of the present invention easily by content disclosed in the present specification.
Notice, the structure that illustrates in this specification institute accompanying drawings, ratio, size etc., all only it is used for the content coordinating description disclosed, understanding and reading for those skilled in the art, it is not intended to limit the enforceable qualifications of the present invention, so not having technical essential meaning, the adjustment of the modification of any structure, the change of proportionate relationship or size, under not affecting effect that the present invention can be generated by and the purpose that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification cited as " on ", " first ", " second ", the term such as " top " and " end ", it is also only and is easy to understanding of narration, not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, changing under technology contents without essence, when being also considered as the enforceable category of the present invention.
Referring to Fig. 2, it is the conducting wire frame structure part plan schematic diagram of the present invention.This conducting wire frame structure 20 includes a chip carrier 21, multiple lead foot 22 and at least one conductive platform 23.
This chip carrier 21 is used for connecing puts at least one semiconductor chip.
This lead foot 22 is located at around this chip carrier 21, so that semiconductor chip can be electrically connected to the external world via this lead foot.
This conductive platform 23 is located between this chip carrier 21 and this lead foot 22, and this conductive platform 23 has at least one protuberance 230, and this protuberance 230 is positioned between adjacent two lead foots 22, in the present embodiment, is illustrate with two protuberances, but is not limited.And this protuberance 230 is connected to a lead foot 22 for electron-donating.
Illustrate, in the conducting wire frame structure 20 of Fig. 2 embodiment, side lead foot 22 in chip carrier 21, total lead foot A～lead foot I, and the protuberance 230 of this conductive platform 23 is used for being electrically connected to lead foot I, and then make this conductive platform 23 and its lead foot I being electrically connected power supply lead foot (such as figure bend part) as this conducting wire frame structure, relatively can make most of lead foots in this conducting wire frame structure, if lead foot A～lead foot H is as signal lead foot, so only have lead foot A compared in the existing conducting wire frame structure of Fig. 1 as signal lead foot part, C, E, F, H, the conducting wire frame structure of the present invention can be effectively increased signal lead foot quantity really, and then the outer contact of signal promoting semiconductor chip.
Referring to Fig. 3, it is the semiconductor package part part plan schematic diagram of application of aforementioned conducting wire frame structure.
This semiconductor package part includes a conducting wire frame structure 20, at least one semiconductor chip 35 and multiple bonding wire 361,362,363.
As it was previously stated, this conducting wire frame structure 20 includes a chip carrier 21, multiple lead foot 22 and at least one conductive platform 23.This lead foot 22 is located at around this chip carrier 21.This conductive platform 23 is located between this chip carrier 21 and this lead foot 22, and this conductive platform 23 is provided with at least one protuberance 230, and this protuberance 230 is positioned between adjacent two lead foots 22, and this protuberance 230 is connected to a lead foot 22 for electron-donating.
nullThis semiconductor chip 35 is arranged on this chip carrier 21，And this semiconductor chip 35 and those lead foots 22 (those lead foots are signal lead foot) it are electrically connected through multiple first bonding wires 361，And this semiconductor chip 35 and this conductive platform 23 it is electrically connected through multiple second bonding wires 362，Wherein this first bonding wire 361 is signal bond wires，This second bonding wire 362 is power supply bonding wire，The protuberance 230 of this conductive platform 23 another is electrically connected to lead foot I through the 3rd bonding wire 363，Wherein this conductive platform 23 and its lead foot I being electrically connected power supply lead foot (such as figure bend part) as conducting wire frame structure，Relatively can make most of lead foots in this conducting wire frame structure，If lead foot A to lead foot H is as signal lead foot，To meet the productive set purpose of semiconductor chip and semiconductor package part.Pass through the power supply contact that the setting of this conductive platform also can provide semiconductor chip enough simultaneously, promote the electrical quality of semiconductor chip.
Additionally, this semiconductor package part also includes a packing colloid (not shown), for being coated with this semiconductor chip 35, bonding wire 361,362,363, a part for chip carrier 21, conductive platform 23 and lead foot 22, this semiconductor package part so can be made to be electrically connected to external device (ED) through the lead foot part exposing outside packing colloid, such as circuit board, wherein the signal lead foot of this conducting wire frame structure is electrically connected to the signal pad (signalpad) of circuit board, so that the signal of semiconductor chip outwards can transmit via bonding wire and signal lead foot；And for the lead foot with conductive platform electric connection in this conducting wire frame structure, namely as power supply lead foot, then it is electrically connected to the power source pad (powerpad) of circuit board, to promote the electrical quality of semiconductor package part.
Referring to Fig. 4, it is the generalized section of the conducting wire frame structure of the present invention and semiconductor package part the second embodiment thereof.
Conducting wire frame structure and the semiconductor package part thereof of the present embodiment are roughly the same with previous embodiment, Main Differences is in that the lead frame of the present embodiment also can not need to arrange chip carrier to be applied to Chip-on-Lead (COL) encapsulation architecture, first pass through such as pi (Polyimide, semiconductor chip 45 is engaged in lead foot 42 and conductive platform 43 by resin adhesive tape (non-icon) PI), this semiconductor chip 45 and this lead foot 42 it is electrically connected again through the first bonding wire 461, and this semiconductor chip 45 and this conductive platform 43 it is electrically connected through the second bonding wire 462, and it is electrically connected this conductive platform and at least one lead foot through the 3rd bonding wire (not shown).Then the packing colloid 47 being coated with this semiconductor chip, bonding wire, conductive platform and part lead foot is formed again.
Known through preceding description, the conducting wire frame structure of the present invention and semiconductor package part thereof, for arranging through conductive platform, and this conductive platform is electrically connected to a lead foot through bonding wire, so that this conductive platform replaces existing multiple power supply lead foots, and then make most of lead foots in lead frame all must as signal lead foot, the outer number of connections of signal to promote semiconductor chip and semiconductor package part, productive setization in order to semiconductor chip and semiconductor package part develops, and also must pass through this conductive platform and arrange the electrical quality promoting semiconductor chip and semiconductor package part.
Above-described embodiment is only for illustrative principles of the invention and effect thereof, not for the restriction present invention.Above-described embodiment all under the spirit and category of the present invention, can be modified by any those skilled in the art.Therefore the scope of the present invention, should as listed by claims.
Claims (15)
1. a conducting wire frame structure, is characterized by, this structure includes:
Multiple lead foots；And
At least one conductive platform, this conductive platform has at least one protuberance being located between adjacent two lead foots.
2. conducting wire frame structure according to claim 1, is characterized by, this conductive platform protuberance is connected to a lead foot for electron-donating.
3. conducting wire frame structure according to claim 2, is characterized by, this conductive platform protuberance is electrically connected to a lead foot through bonding wire.
4. conducting wire frame structure according to claim 2, is characterized by, the lead foot should being electrically connected with conductive platform protuberance is power supply lead foot.
5. conducting wire frame structure according to claim 2, is characterized by, this lead foot not being electrically connected with conductive platform is signal lead foot.
6. conducting wire frame structure according to claim 1, is characterized by, this structure also includes a chip carrier, and wherein, the plurality of lead foot is located at around this chip carrier, and this conductive platform is located between this chip carrier and this lead foot.
7. a semiconductor package part, is characterized by, this semiconductor package part includes:
One conducting wire frame structure, this conducting wire frame structure includes multiple lead foot and at least one conductive platform, and this conductive platform has at least one protuberance being located between adjacent two lead foots；
At least one semiconductor chip, it is electrically connected to this lead foot and conductive platform；And
One packing colloid, it is coated with this lead frame and semiconductor chip, and exposes outside this lead foot part.
8. semiconductor package part according to claim 7, is characterized by, this conductive platform protuberance system is electrically connected to a lead foot.
9. semiconductor package part according to claim 8, is characterized by, this conductive platform protuberance is electrically connected to a lead foot through bonding wire.
10. semiconductor package part according to claim 8, is characterized by, the lead foot should being electrically connected with conductive platform protuberance is power supply lead foot.
11. semiconductor package part according to claim 8, it is characterized by, this lead foot not being electrically connected with conductive platform protuberance is signal lead foot.
12. semiconductor package part according to claim 7, it is characterized by, this semiconductor chip system is electrically connected to this lead foot and conductive platform through bonding wire.
13. semiconductor package part according to claim 7, it is characterized by, this semiconductor chip system connects and is placed in those lead foots.
14. semiconductor package part according to claim 7, it is characterized by, this conducting wire frame structure also includes a chip carrier, and the plurality of lead foot is located at around this chip carrier, and this conductive platform is located between this chip carrier and this lead foot.
15. semiconductor package part according to claim 14, it is characterized by, this semiconductor chip connects and is placed in this chip carrier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103141350 | 2014-11-28 | ||
| TW103141350A TWI566358B (en) | 2014-11-28 | 2014-11-28 | Leadframe structure and semiconductor package thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105742264A true CN105742264A (en) | 2016-07-06 |
Family
ID=56240929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410766780.0A Pending CN105742264A (en) | 2014-11-28 | 2014-12-12 | Lead frame structure and semiconductor package thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105742264A (en) |
| TW (1) | TWI566358B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573123B2 (en) * | 1999-09-07 | 2003-06-03 | Sai Man Li | Semiconductor chip package and manufacturing method thereof |
| CN101241863A (en) * | 2007-02-08 | 2008-08-13 | 百慕达南茂科技股份有限公司 | Chip package structure and its making method |
| CN103140923A (en) * | 2011-09-30 | 2013-06-05 | 联发科技股份有限公司 | Semiconductor package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI334182B (en) * | 2007-02-09 | 2010-12-01 | Chipmos Technologies Bermuda | Method of fabricating chip package structure |
-
2014
- 2014-11-28 TW TW103141350A patent/TWI566358B/en active
- 2014-12-12 CN CN201410766780.0A patent/CN105742264A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573123B2 (en) * | 1999-09-07 | 2003-06-03 | Sai Man Li | Semiconductor chip package and manufacturing method thereof |
| CN101241863A (en) * | 2007-02-08 | 2008-08-13 | 百慕达南茂科技股份有限公司 | Chip package structure and its making method |
| CN103140923A (en) * | 2011-09-30 | 2013-06-05 | 联发科技股份有限公司 | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201620104A (en) | 2016-06-01 |
| TWI566358B (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101506975B (en) | Stack die packages | |
| CN102044512A (en) | Integrated circuit and multi-chip module stacked in three dimensions | |
| CN104425417B (en) | Semiconductor device and method for fabricating the same | |
| CN105097752B (en) | A kind of semiconductor package | |
| TW432558B (en) | Dual-chip packaging process and method for forming the package | |
| US20030127719A1 (en) | Structure and process for packaging multi-chip | |
| CN104241240B (en) | Method for manufacturing semiconductor package | |
| US7256480B2 (en) | Lead frame package structure with high density of lead pins arrangement | |
| KR101123804B1 (en) | Semiconductor chip and stacked semiconductor package havng the same | |
| CN107154385A (en) | Stack package structure and its manufacture method | |
| CN109643706A (en) | The interconnection of embedded tube core | |
| CN104167403B (en) | Lead frame for multi-pin encapsulation | |
| CN106298709B (en) | Low cost is fanned out to formula encapsulating structure | |
| CN105742264A (en) | Lead frame structure and semiconductor package thereof | |
| CN102709199B (en) | Mold array process method for covering side edge of substrate | |
| CN205211727U (en) | Fingerprint identification multi -chip packaging structure | |
| US20140146497A1 (en) | Helix substrate and three-dimensional package with same | |
| CN106158808B (en) | Electronic packing piece and its preparation method | |
| CN110648991B (en) | Adapter plate bonding structure for frame packaged chip and processing method thereof | |
| CN100559582C (en) | Chip stack package structure and manufacture method thereof | |
| CN105590904A (en) | Fingerprint identification multi-chip package structure and preparation method thereof | |
| TW200631148A (en) | Chip type micro connector and method of packaging the sane | |
| CN204361080U (en) | Circuits System and chip package thereof | |
| US7781898B2 (en) | IC package reducing wiring layers on substrate and its chip carrier | |
| CN104103605A (en) | Semiconductor package and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160706 |
|
| RJ01 | Rejection of invention patent application after publication |