CN105742263A - 高频集成电路及其封装 - Google Patents

高频集成电路及其封装 Download PDF

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Publication number
CN105742263A
CN105742263A CN201511005820.0A CN201511005820A CN105742263A CN 105742263 A CN105742263 A CN 105742263A CN 201511005820 A CN201511005820 A CN 201511005820A CN 105742263 A CN105742263 A CN 105742263A
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bonding welding
signal
welding pad
integrated circuit
pad
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A·派
R·卡里略-拉姆利兹
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Analog Devices Inc
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Analog Devices Inc
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Abstract

本公开涉及高频集成电路及其封装。一种集成电路可包括在配置成提供返回路径的键合焊盘以及配置成提供信号键合焊盘的键合焊盘之间交替的一组键合焊盘。例如,五个键合焊盘可被配置成返回-信号-返回-信号-返回结构。集成电路还可被配置成接收或发送高频信号。

Description

高频集成电路及其封装
相关申请的交叉引用
本申请声明根据美国35U.S.C.第119条第(e)项而享有2014年12月30日提交的题为“高频集成电路及其封装(HIGHFREQUENCYINTEGRATEDCIRCUITANDPACKAGINGFORTHESAME)”的美国专利申请No.62/098034的优先权。该申请在此通过引用以其整体明确地并入本文。
技术领域
本申请涉及针对高频集成电路的封装,更具体地涉及信号及返回线路焊盘和键合引线的布置、以及包含这种布置的集成电路。
背景技术
在包括(但不限于)上变频器、低噪声放大器、检测器、合成器及其它应用在内的各种电子应用中,高频处理是必须的。期望通过降低通路损耗来改进信号传输。而且,期望改进高频的带宽或者宽带传输。
发明内容
例如,在一个实施例中,集成电路封装件包括具有电路以及电连接至电路的多个键合焊盘的集成电路。集成电路封装件还具有封装结构,该封装结构包括通过多个引线键合连接至该多个键合焊盘的多个引线。连接至引线的该多个键合焊盘的一组五个连续的键合焊盘包括两个信号键合焊盘和三个返回键合焊盘。这些返回键合焊盘中的一个处在两个信号键合焊盘之间,而且其它两个返回键合焊盘在该组的相对侧毗邻这两个信号键合焊盘。
在另一个实施例中,集成电路被配置用于接收和/或发送高频信号。集成电路包括配置成向或者从集成电路传递高频信号的一组五个连续的键合焊盘。键合焊盘中的三个是返回路径键合焊盘,键合焊盘中的两个是配置成负载相同信号的信号键合焊盘。三个返回路径键合焊盘和两个信号键合焊盘被布置成依次交替的结构。
在另一个实施例中,提供一种组装印制电路板的方法。集成电路被装配至封装结构。集成电路包括电连接至射频电路的多个键合焊盘。该多个键合焊盘包括一组五个连续的键合焊盘,连续的键合焊盘中的三个是返回键合焊盘,连续的键合焊盘中的两个是信号键合焊盘。五个连续的返回键合焊盘和信号键合焊盘被布置成依次交替的结构。该组五个连续的键合焊盘中的每个都被线接至封装结构的五个连续放置的引线中的相应一个。
在另一个实施例中,集成电路封装件包括具有电路以及电连接至电路的多个键合焊盘的集成电路。集成电路封装件还包括封装结构,该封装结构包括通过多个引线键合连接至多个键合焊盘的多个引线。连接至引线的该多个键合焊盘的一组三个连续的键合焊盘包括一个信号键合焊盘和两个返回键合焊盘。信号键合焊盘处于该两个返回键合焊盘之间,而且这两个返回键合焊盘被配置成仅仅为信号键合焊盘上负载的信号提供返回路径。
附图说明
根据结合示出了本发明示例实施例的附图而做出的下述详细说明,本发明的进一步的目的、特征和优势将变得明显,其中:
图1描绘了集成电路封装件的实施例的一部分的透视图,包括连接至引线框的单端集成电路,其中键合焊盘和引线被布置成接地-信号-接地-信号-接地(G-S-G-S-G)结构。
图2A描绘了利用G-S-G-S-G结构以及名义上的G-S结构连接至引线框的集成电路的频率和前向信号传输增益之间的示例关系。
图2B描绘了利用G-S-G-S-G结构以及名义上的G-S结构连接至引线框的集成电路的频率和反射系数之间的示例关系。
图3A描绘了裸片和封装件之间的接地-信号(G-S)结构的连接的俯视图。
图3B描绘了根据实施例的裸片和封装件之间的接地-信号-接地(G-S-G)结构的连接的俯视图。
图3C描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地(G-S-G)结构的连接的俯视图。
图3D描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图3E描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图3F描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图3G描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图3H描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图3I描绘了根据另一实施例的裸片和封装件之间的接地-信号-接地-信号-接地(G-S-G-S-G)结构的连接的俯视图。
图4描绘了根据实施例的连接至差动示例集成电路的引线框的俯视图。
具体实施方式
各种现代电子应用要求高频信号被传递进出封装的集成电路。这些高频信号对传输连接的物理形式敏感。例如,薄的键合引线表现出尤其在高频下可导致失配并导致损耗的相对高的电感。如此处讨论的那样,可能有利的是提供附加的连接来改进信号传输。而且,可能有利的是按照特定方式布置这些连接以改进传输特性,例如降低连接的电感。
在一些实施例中,添加更多的返回路径连接可改进传输特性。例如,提供更多的返回或接地连接可提供对各个引线的电磁性能的不同影响。这种电磁效应可能在特定情况下特别明显,例如其中将应用高频或宽带信号的情况。在这种情况下,可能期望使用附加的信号和返回线路(例如,接地连接)来改进特定导线/连接的性能。例如,并行布置多个信号导线可降低总电感。然而,并行导线的互感可能局限该优势。因此,如此处进一步讨论的那样,可能有利的是包括附加的返回/接地路径以及相应的键合引线,以及在一些实施例中包括附加的信号路径以及相应的键合引线,用于此处所述的那样或者下文参考实施例描述的那样在集成电路和封装结构之间传递高频信号。应该理解的是,“高频”是相对术语,而且此处指教的布置的优势部分地取决于相对于系统阻抗的IC键合和封装引线之间的连接(例如,键合引线)的阻抗,这继而又部分地取决于连接的物理尺寸和信号频率、以及系统对失配的敏感度。
图1描绘了封装件5的一部分的透视图,包括装配至封装结构的集成电路10的一部分。如图1所示,封装结构可以是引线框20,但是其它结构也可被用来将集成电路10物理连接或电连接至系统板9。将集成电路连接至板的其它封装结构的示例包括陶瓷基板、PCB基板或其它结构。引线框20可包括连接至诸如接地之类的电路径的诸如外围引线24以及裸片座26之类的多个引线。引线24可沿封装件5的外周布置。封装件5还可包括覆盖引线框20、集成电路10和引线键合32、34的封装物7。
集成电路10可提供潜在地用作混频器、乘法器、下变频器、放大器、合成器、检测器的各种模拟或数字功能中的一个或多个、这些功能的组合,或者提供其它功能。在一些实施例中,集成电路可被配置成在高频下接收或发送信号,例如1GHz以上,尤其是4GHz以上,例如处于20-60GHz的范围。这些信号可能对电失配或者可能受对集成电路(例如集成电路和引线框之间的)的连接影响的其它信号退化敏感。应该理解的是,“高频”是相对术语,而且此处指教的布置的优势部分地取决于相对于系统阻抗的IC键合和封装引线之间的连接(例如,键合引线)的阻抗,这继而又部分地取决于连接的物理尺寸和信号频率、以及系统对失配的敏感度。这些功能和能力的各种组合可被布置在集成电路10上。而且,虽然集成电路10可包括用于高频信号处理的电路和相关键合焊盘,但是集成电路10还可包括与高频信号或宽带处理无关的和/或对键合引线的阻抗不敏感的其它电路和相关键合焊盘。因此,用于高频或宽带信号处理的电路和相关键合焊盘可仅仅表示集成电路10上的电路的子集,而且类似地被裸片的键合焊盘、封装件的引脚/引线、和其它连接元件的子集访问。
如图1进一步所示,集成电路10可包括多个键合焊盘12、14以提供用于对引线框20(或者另一封装结构)的连接的场所。在图1中,出于简洁起见仅仅示出了五个连续的键合焊盘12、14。这些键合焊盘12、14可被用于特定目的,例如用于将高频信号传输进出集成电路10。应该理解的是,多于五个连续的键合焊盘可被用于其它实施例中,而且其它键合焊盘(未示出)可连接至集成电路10中的不同电路。而且,如所示,连续的导线32、34可通过引线键合(例如,球焊键合、楔形键合、一致键合或其它形式的键合)在连续的键合焊盘12、14处附接至集成电路10。导线可以是金的、铜的或现有技术中已知的其它材料。
图1中的导线32、34被引导至两个位置中的一个。导线32中的三个连接至引线框20的裸片座26,而且导线34中的两个连接至引线框的信号引线24。在所示实施例中,裸片座26可电连接至用于信号的返回路径,例如接地连接,以使得导线32可作为接地导线。因此,应该理解的是,附接至与基座26连接的导线32的键合焊盘12可以是接地键合焊盘。然而,在其它实施例中,接地导线32可通过诸如引线框上的接地引线(如下文进一步讨论的那样以及例如如图3所示)、多个基座或者可连接至印制电路板(PCB)上的接地或另一接地源的其它组件之类的其它结构连接至接地。在任一情况下,多个接地导线32可并行地将集成电路10接地。
虽然术语“接地”和速记形式“G”通常在本说明书中用来描述各种连接,但是应该理解的是,在其它实施例中,用于高频信号的返回路径并非必须是接地连接。
类似地,导线34可连接至引线24,引线24可向集成电路10提供或从集成电路10接收信号,因此引线可以是信号引线,到它的导线可以是信号导线,而且它们所连接的键合焊盘14可以是信号键合焊盘。尤其地,在所示实施例中,两个信号导线34可连接至单个信号引线24,由此负载相同的信号。然而,在其它实施例中,这两个信号导线34可连接至不同信号引线而且有可能负载不同的信号或者组合来负载相同信号。
而且,如图1所示,连续的接地导线32和信号导线34具有依次交替的结构。类似地,连续的接地键合焊盘12和信号键合焊盘14具有相应的依次交替的结构。虽然由于接地导线32连接至基座26而在此未示出,在实施例中使用单独的接地引线,接地引线和(多个)信号引线24也可具有依次交替的结构。利用三个接地特征(键合焊盘、导线和/或引线)和两个信号特征(键合焊盘、导线和/或引线),依次交替的结构可被表示为“G-S-G-S-G”设置。方便起见,这些设置的语境中的术语“(多个)接地特征”和“(多个)信号特征”可被用来描述将集成电路连接至封装结构的以及例如经由系统板9从封装结构至电子系统的信号和返回路径中的任意的键合焊盘、导线、引线或其它电子元件。
其它依次交替的结构也是可行的。例如,在一些实施例中,可使用G-S-G设置,包括两个接地特征和一个信号特征。在其它实施例中,可使用G-S-G-S-G-S-G设置(例如,具有七个接地/信号特征),包括四个接地特征和三个信号特征。其它实施例可包括5个接地特征和4个信号特征、6个接地特征和5个信号特征、7个接地特征和6个信号特征等依次交替的设置。在一些实施例中,优选地使得接地特征处于键合焊盘、导线和/或引线的设置的端部,以使得在依次交替的结构中接地特征比信号特征多一个,而且接地特征对称地布置在特征组的外部端部。
在其它实施例中,依次交替的设置可使得信号在端部,以使得信号比接地多一个,例如:S-G-S、S-G-S-G-S、S-G-S-G-S-G-S等。尤其,在设置是依次交替的而且信号比接地多一个(或者接地比信号多一个)时,设置可以是对称的。然而,在一些实施例中,依次交替的设置可以是不对称的而且具有相同数量的信号和接地,使得一个端部是信号而且另一个端部是接地,例如:S-G-S-G、S-G-S-G-S-G、S-G-S-G-S-G等。
设置内的信号可被配置成负载此处讨论的高频或其它信号类型,而且这些信号类型的传输可在设置中进行改进,下文将予以讨论。而且,在许多集成电路10中,附加的键合焊盘、导线和/或引线可被布置成毗邻上述设置。因此,例如,其中接地特征在端部的设置可在设置的两侧毗邻信号特征。在一些实施例中,设置内的信号特征可被配置成传输相同的电子信号,而不在设置中的信号特征可传输其它信号。
随着电子设备变得越来越小,增加对诸如集成电路之类的组件的连接的数量变得更加困难。这通常导致接地或信号返回连接的减少,因为多个接地连接可能被视为多余的。然而,在一些实施例中,可能期望包括更多的接地连接。尤其地,紧邻信号导线布置信号返回(例如,接地)导线可改进经由信号导线的传输。例如,接地和信号导线可产生减小了导线对的有效电感的互感,因为这两个导线可能具有基本相反的电流。减小的有效电感可降低来自向经由导线传输的信号(尤其是高频信号)引入的封装传输失配的损耗,从而拓展了带宽。
紧邻信号导线布置信号返回(例如,接地)导线还可增加两个导线之间的电容。由此,信号和返回路径键合焊盘与它们各自的封装引线(或接地的裸片焊盘)之间的连接可被布置成彼此毗邻,以使得对称的毗邻信号和返回路径作为传输线。类似于传输线,频带宽度可被显著拓宽而且转移阻抗可更好地匹配系统阻抗。而且,对称性可提供可减小连接间的变化的线间一致电容。因此,包括处于两端的接地的依次交替的设置在某些情况下尤其有优势。
在信号特征的两端布置接地特征可提供附加的优势。例如,这可提供降低了信号和接地周围的杂散电磁场的对称电学设计。尤其地,这种杂散电磁场可向传输的信号(尤其是高频信号)引入附加干扰。
对称性和互感还可通过使用来自连接至一个信号引线24的分开的信号焊盘14的两个信号导线34来进行改进,如图1所示。在所示实施例中,两个信号导线34负载相同的信号。而且,三个接地导线32可选择性地提供从集成电路10至接地基座26(或其它接地)的并行连接。因此,G-S-G-S-G设置可能在其物理连接的布置中是对称的,而且还提供对称电信号(“电对称”)。尤其地,对称性的这些优势还可存在于其中信号特征在相对两端(而且信号比接地多一个)的交替结构中。具有相等数量的信号特征和接地特征的设置(例如,G-S-G-S-G-S)可被看作是“部分对称的”,尤其是当每个信号特征传输相同的电信号时,即使设置不是完全对称的。这种结构可提供键合焊盘的无污染传输和经济性之间的唯一折中。
而且,通过使得各种导线、引线、键合焊盘和其它特征基本物理对称,可进一步改进对称性。例如,在G-S-G-S-G设置中,通过依次交替的信号和接地特征提供了对称性。然而,如果接地或信号特征中的一些具有不同的物理形状、尺寸、材料特性等,则对称性可能由于来自这些特征的电磁效应可能变化而降低。因此,在一些实施例中,设置可以基本上物理对称以进一步改进传输。
图2A和2B描绘了G-S-G-S-G结构相对于G-S结构的潜在优势。图2A描绘了与G-S结构比较而言的具有G-S-G-S-G结构的键合焊盘和键合引线组的集成电路封装件的频率和信号传输增益(S21)之间的建模的关系。如所示,相对于G-S-G-S-G设置,在G-S设置上,增益随着频率实质更快地下降。图2B描绘了针对反射(S11)的类似数据,尤其是高于大约4GHz。如所示,相对于G-S-G-S-G设置,针对G-S设置的反射实质更快地增大,尤其是高于大约4GHz。因此,依次交替的接地和信号结构看起来提供了更高频率下的有效值。在一些实施例中,此处描述的交替的设置可以与被配置成接收或发送等于或高于大约4GHz(尤其是等于或高于大约10GHz、20GHz、40GHz或更高)的信号的集成电路一起使用。
图3A-3I描绘了集成电路10和封装结构20(例如,引线框)之间的连接的设置的不同布置,其中类似特征标有类似参考标记。在图3A中,示出了S-G设置,包括处于集成电路10A的一部分和封装结构20A的一部分之间的一个信号连接和一个返回连接。标记为“S”的信号连接可包括信号通过导线连接至信号引线24A的键合焊盘14A。标记为“G”的返回连接(例如,用于“接地”)可包括通过导线连接至接地引线22A的接地键合焊盘12A。当返回连接作为总体的接地连接时,附加的电子连接可附接到它上面。在图3A-3I中,示出的对引线和键合焊盘进行连接的导线未被标记,以简化附图。
在图3B中,G-S-G设置包括依次交替的一个信号连接和两个返回连接。因此,信号连接被两个返回连接围绕。返回连接可包括接地键合焊盘12B和接地引线22B之间的导线连接。信号连接可包括信号键合焊盘14B和信号引线24B之间的导线连接。在一些实施例中,返回连接可例如通过并行连接,负载基本相同的传输,由此G-S-G设置是电对称的。
在图3C中,所示G-S-G设置可能基本上类似于图3B所示的设置。然而,图3C中的设置可包括向下键合,例如接地键合焊盘12C和基座26C之间的返回连接。基座26C可提供与参考图1讨论的接地/返回连接类似的接地/返回连接。在其它实施例中,这种总体的接地/返回连接可由封装结构20C上的其它导电元件或其它结构来提供。
尤其地,在一些实施例中,从接地键合焊盘12C至基座26C的导线可能不会提供与对接地引线的连接一样多的传输特性中的改进。例如,在一些实施例中,这些导线可能与信号导线的长度不是同延的。在这种情况下,它们仍可提供传输特性中的一些改进而不占据稀有的引线。在其它实施例中,接地(或返回)导线可与信号导线同延,或者甚至延伸得比信号导线更远。
图3D-3I描绘了与图3B-3C中示出的设置基本类似的G-S-G-S-G设置。例如,每个附图包括依次交替的信号和返回连接,其中返回连接要么连接至接地引线24要么连接至公共的集中接地的特征(例如接地基座26)。如上所述,多个返回连接可提供针对仅仅一个信号的返回路径,或者可提供针对多个信号的返回路径。例如,在图3D和3E中,返回的最上方的返回连接可能提供信号线S1专用的返回,而且最下方的返回连接可能提供信号线S2专用的返回,以使得返回连接专用于毗邻的信号连接。与两个信号连接(例如,集中的信号连接)相邻的返回连接可提供专用于S1或S2、专用于S1和S2两者的返回连接,或者提供针对其它传输的总体接地连接(包括S1和/或S2)。
图3D-3I中的连接可以是对称的,由此它们包括G-S-G-S-G结构(换言之,相对于信号和接地对称)。连接还可以是电学不对称的。例如,在图3D和3E中,信号线S1和S2可被配置成负载不同信号,使得电传递可以是不对称的。在图3F-3I中,两个信号连接可负载相同的电信号,使得设置可以是电学对称的。
图3F-3I中的连接可能在单个信号如何通过两个信号连接方面是不同的。如图3F和3G所示,单个电信号可通过信号键合焊盘14F或14G和信号引线24F或24G的两个设置进行传输。信号可分为集成电路10F或10G内的两个单独的并行信号连接,而且类似地用于封装结构20F或20G与系统板或其它外部信号载体之间的连接。如图3H和3I所示,它们还可分为封装结构20H或20I与集成电路10H或10I之间的接口处的并行连接。如所示,一个信号引线24H或24I可连接至两个键合焊盘14H或14I。因此,封装引线可具有G-S-G结构或S结构,同时相应的键合焊盘可具有G-S-G-S-G结构。尤其地,在这些布置中仍可保持对称性,如在其它实施例中讨论的那样。而且,在其它实施例中,多个信号引线可连接至集成电路中的单个信号键合焊盘,作为图3H、3I所示的实施例的反转。
图4描绘了封装件105,其包括装配至引线框120形式的封装结构的集成电路110,引线框120包括用于集成电路110中的各种电路的各种集成电路键合焊盘和封装引线组。如在其它实施例中讨论的那样,在封装处理中,在集成电路110被装配至封装结构之后,集成电路110上的键合焊盘112、114可被引线键合至封装结构。
部分140描绘了根据实施例的用于诸如其中较高的信号质量比较重要的高频电路之类的电路的一组键合焊盘112、114,引线122、124,以及键合引线。此处指教的针对封装引线、键合引线和/或集成电路键合焊盘和内部集成电路连接的对称的返回和信号交替,对于在封装引线和集成电路之间传输高频或宽带信号,是尤其有利的。最受益于这些特征的频率范围可取决于这些特征的形式,例如导线的长度、键合焊盘和引线的尺寸、以及其它特性。例如,部分140可提供射频(RF)信号(例如,大约4GHz至大约40GHz或更高)的接收和/或传输。集成电路110中的相应电路的示例包括上变频器(例如,在等于或高于大约4GHz下发送)、RF放大器、检测器、合成器以及此处讨论的其它宽带应用。如所示,在部分140中,G-S-G-S-G设置配置有接地(或其它返回路径)键合焊盘112和信号键合焊盘114、以及相应的接地(或其它返回路径)引线122和信号引线124(以及实线画出的在附图中为标记的相应键合引线)。而且,如所示,每个键合焊盘-引线对之间可能存在并行连接的两个导线。除了由于对称的接地-信号交替而产生的电感降低之外,在每个键合焊盘-引线对之间使用两个导线可进一步降低电感。键合焊盘112、114电连接至集成电路110内的高频处理电路。
部分142描绘了根据实施例的用于诸如基带和IQ(同相和正交)调制信号的接收和/或传输之类的应用的一组连接。在所示示例中,仅仅信号引线124被提供用于封装结构上的电路。接地和信号键合焊盘112、114的G-S-_-S-G模式被使用,从而形成中间具有虚设的键合焊盘的部分交替的对称设置。键合焊盘112、114可连接至具有部分交替的G-S-S-G结构的引线122、124。在这个部分交替的对称设置中,每个信号特征可毗邻仅仅一个接地特征,提供在此描述的优势中的一些优势,但是不一定像与两个接地特征毗邻的信号特征那样多地改进传输特性。尤其地,该结构也仍可提供物理对称性以使得来自反射的损耗最小化。而且,在一些实施例中,还可通过经由两个信号连接接收/发送公共信号,并且使得相应的接地连接负载相同的返回,来提供电对称性。
部分144和146分别描绘了根据实施例的用于诸如中频(IF)信号以及本地振荡器(LO)信号的接收和/或传输之类的应用的连接组。在这两个部分中,引线122、124和键合焊盘112、114可具有S-G-S结构,形成信号在端部的交替设置。
如图4中的实施例所示,信号和返回(例如,接地)特征的连接和布置的各种组可被布置在相同集成电路的封装件内。具体地,对于质量敏感的和高频的应用,部分140中的键合焊盘、或者键合焊盘和相应的封装引线的交替对称布置,例如G-S-G-S-G结构,可能是有利的。对于这种敏感的和高频的信号处理,多余的接地引线122表示封装件中的可用引线的牺牲物以保持高信号质量。例如,其中在接收或传输高频信号过程中应该以最小损耗保持信号质量的这种电路的示例包括混合器、倍频器、RF放大器、RF检测器以及RF合成器。
相反,特征的其它组可以与不接收或发送高频信号(例如,基带和IQ调制器或IF电路)的电路或者对其而言信号质量不重要的高频电路(例如,本地振荡器)通信。对于这种电路,封装引线通常不需要为了多余的接地连接而被牺牲。
如IQ部分142所示,半交替的键合焊盘和引线可以与交替接地的两个一组的信号一起使用。而且,如该部分142所示,虚设的键合焊盘可被布置在两个信号之间,而不是附加的接地/返回连接。如IF和LO部分144、146所示,可以使用引线和键合焊盘的S-G-S设置。而且,如图4的实施例所示,多个导线可将一个键合焊盘连接至一个引线。类似地,如图1所示,两个键合焊盘可被连接至一个引线。
此处描述的各种结构对于对阻抗失配敏感的电路和信号尤其有利,特别是对于在足够高的频率下操作以使得转移阻抗相对于系统阻抗比较明显(例如大于10%)的电路和信号。例如,1mm的键合引线可能具有大约1nH的电感。由于电抗正比于信号频率(电抗=2π(频率)(电感)),在IC和板之间传输信号时键合引线的相对阻抗将随着信号频率而变化。如果1GHz信号通过导线,预期的电抗可能大约是j6欧姆。如果系统的阻抗为50欧姆,导线的阻抗稍大于系统阻抗的10%,而且因此可开始使得信号传输衰退。对于对阻抗失配敏感的信号(例如,低噪声放大器的输入),此处描述的实施例可使得键合焊盘和引线之间的转移阻抗减小至小于系统阻抗的大约10%。
上述方法、系统和/或设备可被实现在集成电路中或者实现在各种电子装置中。例如,集成电路或者附接至封装结构(例如引线框)的集成电路可以物理方式或电子方式附接至印制电路板(PCB)。电子装置的示例可包括但不限于汽车部件、消费电子产品、消费电子产品的部件、电子测试设备等。电子产品中的集成电路的示例可包括放大器、整流器、可编程滤波器、衰减器、可变频率电路等。电子装置的示例还可包括存储器芯片、存储器模块、光网络或其它通信网络的电路、以及盘驱动器电路。电子产品可包括但不限于无线装置、移动电话(例如,智能手机)、蜂窝基站、电话、电视机、计算机监控器、计算机、手持计算机、平板计算机、个人数字助理(PDA)、微波炉、冰箱、立体音响系统、盒式记录器或播放器、DVD播放器、CD播放器、数字视频记录器(DVR)、VCR、MP3播放器、无线电、摄像录像机、相机、数字相机、便携存储器芯片、洗涤机、烘干机、洗涤机/烘干机、复印机、传真机、扫描器、多功能外围装置、手表、钟等。而且,电子装置可包括未制成产品。
除非语境明确地相反地要求,在说明书和权利要求中,词语“包含”、“包括”、“具有”、“含有”等将被解释为包罗的意义,不同于排他的或穷举的含义;也就是说是“包括但不限于”的意思。此外,词语“此处”、“以上”、“以下”以及具有类似含义的词语,在用于本申请时,应该指的是作为整体的本申请而不是本申请的任意特定部分。在语境允许的情况下,具体实施方式中的使用单数或多数的词语也可分别包括多数或单数。两个或更多项目的列表中引述的词语“或”旨在覆盖该词语的所有下述解释:该列表中的任意项目、该列表中的所有项目、以及该列表中的项目的任意组合。
而且,此处使用的条件语,例如“可”、“可能”、“可以”、“能够”、“例如”、“比如”、“诸如”等,除非特别地相反地指出,或者在使用的语境中被相反地理解,总体上旨在表示特定实施例包括而其它实施例不包括特定特征、元素和/或状态。因此,这种条件语并不表示特征、元素和/或状态以任何方式被要求用于一个或多个实施例或者一个或多个实施例必须包括用于决定是否具有设计者输入的逻辑或者提示是否这些特征、元素和/或状态被包含在任意特定实施例中或者在任意特定实施例中被执行。
此处提供的指教可被应用至其它系统,而不是必须是上述系统。上述各种实施例的元素和动作可组合来提供其它实施例。
虽然已经描述了具体实施例,但是这些实施例仅仅以示例的方式呈现,而不是旨在限制本发明的范围。实际上,此处描述的新颖的方法和系统可按照各种其它形式实现。而且,可以在不脱离本发明的精神的情况下做出此处描述的方法和系统的形式的各种省略、替换和改变。所附权利要求及其等效形式旨在覆盖落入本发明的范围和精神内的这些形式或修改。由此,本发明的范围仅仅通过参考所附权利要求来限定。

Claims (27)

1.一种集成电路封装件,包括:
集成电路,包括电路以及电连接至电路的多个键合焊盘;以及
封装结构,包括通过多个引线键合连接至多个键合焊盘的多个引线,
其中连接至引线的所述多个键合焊盘的一组五个连续的键合焊盘包括两个信号键合焊盘和三个返回键合焊盘,一个返回键合焊盘处于所述两个信号键合焊盘之间,而且其它两个返回键合焊盘在该组的相对侧毗邻所述两个信号键合焊盘。
2.根据权利要求1所述的集成电路封装件,其中所述多个引线包括至少一个裸片座。
3.根据权利要求1所述的集成电路封装件,其中所述封装结构包括引线框。
4.根据权利要求3所述的集成电路封装件,其中所述引线框包括通过引线键合连接至该组五个连续的键合焊盘的一组五个连续的引线。
5.根据权利要求4所述的集成电路封装件,其中所述五个连续的键合焊盘中的每个都通过至少两个引线键合连接至所述五个连续的引线中的一个。
6.根据权利要求1所述的集成电路封装件,其中所述至少两个信号键合焊盘以及至少三个接地键合焊盘被布置成物理对称。
7.根据权利要求1所述的集成电路封装件,其中所述至少两个信号键合焊盘和至少三个接地键合焊盘物理上足够靠近到能够提供互负电感。
8.根据权利要求1所述的集成电路封装件,其中所述电路被配置成通过所述两个信号键合焊盘发送或接收频率大于或等于大约1GHz的信号。
9.根据权利要求1所述的集成电路封装件,其中所述电路被配置成发送或接收频率大于或等于大约4GHz的信号。
10.根据权利要求1所述的集成电路封装件,其中该组五个连续的键合焊盘是一组七个连续的键合焊盘的一部分,该组七个连续的键合焊盘还包括处于该组五个连续的键合焊盘的每侧的一个附加的信号键合焊盘。
11.一种配置用于接收和/或发送高频信号的集成电路,所述集成电路包括:
配置成向或者从集成电路传递高频信号的一组五个连续的键合焊盘,键合焊盘中的三个是返回路径键合焊盘,键合焊盘中的两个是配置成负载相同信号的信号键合焊盘,
其中所述三个返回路径键合焊盘和所述两个信号键合焊盘被布置成依次交替的结构。
12.根据权利要求11所述的集成电路,其中所述三个返回路径键合焊盘和两个信号键合焊盘都被布置在集成电路的单侧上。
13.根据权利要求11所述的集成电路,其中所述两个信号键合焊盘被配置成负载模拟信号。
14.根据权利要求11所述的集成电路,其中所述两个信号键合焊盘被配置成负载数字信号。
15.根据权利要求11所述的集成电路,其中所述集成电路包括RF上变频器、RF下变频器、RF放大器、倍频器、RF合成器和RF检测器电路中的至少一个。
16.根据权利要求11所述的集成电路,其中所述集成电路被配置成通过所述两个信号键合焊盘接收或发送至少1GHz的信号。
17.根据权利要求11所述的集成电路,其中所述集成电路被配置成通过所述两个信号键合焊盘接收或发送至少10GHz的信号。
18.一种包括根据权利要求11所述的集成电路的封装件,还包括通过多个引线键合连接至集成电路的引线框,以使得所述五个连续的键合焊盘通过引线连接至引线框的五个连续的引线。
19.一种系统,包括安装在印制电路板上的根据权利要求18所述的封装件。
20.一种组装印制电路板的方法,包括:
将集成电路装配至封装结构,集成电路包括电连接至射频电路的多个键合焊盘,所述多个键合焊盘包括一组五个连续的键合焊盘,连续的键合焊盘中的三个是返回键合焊盘,连续的键合焊盘中的两个是信号键合焊盘,五个连续的返回键合焊盘和信号键合焊盘被布置成依次交替的结构;以及
将该组五个连续的键合焊盘中的每个都线接至封装结构的连续放置的引线中的相应一个。
21.一种集成电路封装件,包括:
集成电路,包括电路以及电连接至电路的多个键合焊盘;以及
封装结构,包括通过多个引线键合连接至多个键合焊盘的多个引线,
其中,连接至引线的所述多个键合焊盘的一组三个连续的键合焊盘包括一个信号键合焊盘和两个返回键合焊盘,信号键合焊盘处于所述两个返回键合焊盘之间,所述两个返回键合焊盘被配置成仅仅为信号键合焊盘上负载的信号提供返回路径。
22.根据权利要求21所述的集成电路封装件,其中所述多个引线包括至少一个基座。
23.根据权利要求21所述的集成电路封装件,其中所述封装结构包括引线框。
24.根据权利要求23所述的集成电路封装件,其中所述引线框包括通过引线键合连接至该组三个连续的键合焊盘的一组三个连续的外围引线。
25.根据权利要求1所述的集成电路封装件,其中该组三个连续的键合焊盘物理上足够靠近到能够提供互负电感。
26.根据权利要求1所述的集成电路封装件,其中所述电路被配置成通过所述信号键合焊盘发送或接收频率大于或等于大约1GHz的信号,而且键合焊盘和引线之间的转移阻抗小于所述电路的系统阻抗的10%。
27.根据权利要求26所述的集成电路封装件,其中所述电路被配置成发送或接收频率大于或等于大约20GHz的信号。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110459517A (zh) * 2018-05-08 2019-11-15 思通科技有限公司 倒装芯片集成电路器件
CN114631226A (zh) * 2019-10-29 2022-06-14 日本电信电话株式会社 高频线路连接结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11894322B2 (en) 2018-05-29 2024-02-06 Analog Devices, Inc. Launch structures for radio frequency integrated device packages
US11424196B2 (en) 2018-06-01 2022-08-23 Analog Devices, Inc. Matching circuit for integrated circuit die
US11417615B2 (en) 2018-11-27 2022-08-16 Analog Devices, Inc. Transition circuitry for integrated circuit die
US11350537B2 (en) 2019-05-21 2022-05-31 Analog Devices, Inc. Electrical feedthrough assembly
US11744021B2 (en) 2022-01-21 2023-08-29 Analog Devices, Inc. Electronic assembly

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030127711A1 (en) * 2002-01-09 2003-07-10 Matsushita Electric Industrial Co., Ltd. Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same
US20030160322A1 (en) * 2002-02-27 2003-08-28 Tsung-Ying Hsieh Monolithic microwave integrated circuit package having thermal via
US20070284724A1 (en) * 2006-06-09 2007-12-13 Robert Mark Englekirk Mounting integrated circuit dies for high frequency signal isolation
KR20080086042A (ko) * 2007-03-21 2008-09-25 삼성전자주식회사 커플링 노이즈가 감소된 반도체 칩 패키지
JP2013197517A (ja) * 2012-03-22 2013-09-30 Seiko Instruments Inc 半導体装置
CN103500736A (zh) * 2013-08-22 2014-01-08 上海宏力半导体制造有限公司 芯片封装结构和芯片封装方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828957A (en) * 1996-03-14 1998-10-27 Kroeger; Brian W. Satellite beam acquisition/crossover for a mobile terminal
US6675472B1 (en) 1999-04-29 2004-01-13 Unicap Electronics Industrial Corporation Process and structure for manufacturing plastic chip carrier
JP3596807B2 (ja) 2000-08-09 2004-12-02 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント配線板及びその製造方法
TW545697U (en) 2002-09-03 2003-08-01 Via Tech Inc Structure of chip package
US7002249B2 (en) * 2002-11-12 2006-02-21 Primarion, Inc. Microelectronic component with reduced parasitic inductance and method of fabricating
US6863548B1 (en) 2003-06-04 2005-03-08 Inphi Corporation Method and apparatus for improving the performance of edge launch adapters
US8436450B2 (en) * 2008-02-01 2013-05-07 Viasat, Inc. Differential internally matched wire-bond interface
JP2011049216A (ja) 2009-08-25 2011-03-10 Elpida Memory Inc 回路基板及びこれを備える半導体装置、メモリモジュール、メモリシステム、並びに、回路基板の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030127711A1 (en) * 2002-01-09 2003-07-10 Matsushita Electric Industrial Co., Ltd. Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same
US20030160322A1 (en) * 2002-02-27 2003-08-28 Tsung-Ying Hsieh Monolithic microwave integrated circuit package having thermal via
US20070284724A1 (en) * 2006-06-09 2007-12-13 Robert Mark Englekirk Mounting integrated circuit dies for high frequency signal isolation
KR20080086042A (ko) * 2007-03-21 2008-09-25 삼성전자주식회사 커플링 노이즈가 감소된 반도체 칩 패키지
JP2013197517A (ja) * 2012-03-22 2013-09-30 Seiko Instruments Inc 半導体装置
CN103500736A (zh) * 2013-08-22 2014-01-08 上海宏力半导体制造有限公司 芯片封装结构和芯片封装方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110459517A (zh) * 2018-05-08 2019-11-15 思通科技有限公司 倒装芯片集成电路器件
CN114631226A (zh) * 2019-10-29 2022-06-14 日本电信电话株式会社 高频线路连接结构
CN114631226B (zh) * 2019-10-29 2024-01-16 日本电信电话株式会社 高频线路连接结构

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