CN105718024B - 提供每内核电压和频率控制 - Google Patents

提供每内核电压和频率控制 Download PDF

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CN105718024B
CN105718024B CN201610029935.1A CN201610029935A CN105718024B CN 105718024 B CN105718024 B CN 105718024B CN 201610029935 A CN201610029935 A CN 201610029935A CN 105718024 B CN105718024 B CN 105718024B
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voltage
processor according
frequency
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CN105718024A (zh
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P·库马尔
H·源
C·L·霍顿
D·比尔曼
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

在一个实施例中，本发明包括：处理器，其具有控制逻辑和多个内核，所述控制逻辑用于独立于向所述多个内核的至少第二内核提供电压/频率，而控制向所述多个内核的第一内核提供电压/频率。在一些实施例中，可以从处理器的一个或多个内部电压调节器提供电压。描述并要求保护其它实施例。

Description

提供每内核电压和频率控制
本申请是2011年9月21日提交的申请号为201180055923.1的同名专利申请的分案申请。
背景技术
在基于计算机的系统的所有部分都需要考虑功率和热管理问题。虽然在服务器领域，电成本驱动对低功率系统的需要，但在移动系统中，电池寿命和热限制使得这些问题相关。优化系统使其以最小功耗获得最大性能，这通常是利用操作系统(OS)或系统软件控制硬件元件完成的。大部分现代OS使用高级配置和电源接口(ACPI)标准(例如，2006年10月10日公布的Rev.3.0b)来优化这些领域内的系统。ACPI实施允许处理器内核处于不同的省电状态(也称为低功率或空闲状态)，通常被称为所谓的C1到Cn状态。对于封装级别(package-level)的省电存在类似的封装C状态，但是不是OS可见的。
当内核是活跃的时，其在所谓的C0状态运行；当内核是空闲的时，其可以处于内核低功率状态，所谓的内核非零C状态。内核C1状态表示低功率状态，其具有最低的省电但是能立即进入和退出；而扩展深-低功率状态(例如，C3)表示静态功耗可忽略的功率状态，但是进入/退出该状态以及响应活动(即，返回到C0)的时间较长。
除了省电状态，在ACPI中也提供了性能状态或所谓的P状态。这些性能状态可以允许控制性能-功率级别，同时内核处于活跃状态(C0)。通常，多个P状态是可用的，即从P0-PN。一般而言，ACPI P状态控制算法将优化功耗而不影响性能。对应于P0的状态可以以用于内核的最大电压和频率组合操作内核，而每个P状态(例如P1-PN)以不同的电压和/或频率组合操作内核。这样，当处理器活跃时，基于处理器的使用可以发生性能和功耗的平衡。虽然在活跃模式期间可以使用不同的P状态，但是用于不同内核的独立P状态不能以多内核处理器的不同电压和频率操作，因此，由于最多所有的活跃内核能够以不同频率操作，但是它们必须都共享相同的电压，所以不能在获得优选的省电的同时达到期望的性能级别。
附图说明
图1为根据本发明的一个实施例的系统的框图。
图2为根据本发明的一个实施例的方法的流程图。
图3为根据本发明的另一实施例的方法的流程图。
图4为根据本发明的实施例的处理器的框图。
图5为根据本发明的实施例的处理器内核的框图。
图6为根据本发明的实施例的系统的框图。
具体实施方式
在各种实施例中，具有多内核结构的处理器可以例如根据ACPI规范提供每内核的功率-性能(P)状态的控制。这样，能够实现对功耗和性能的更好控制。例如，在多内核处理器中，仅能够使得少数内核在热约束环境下以较高内核频率运行，使得在执行期望的工作负载的同时能减少功耗以及因此降低温度。
因此，在各种实施例中，处理器内的多个内核的每一个都被控制以不同的电压和/或频率操作。这样，可以在多个内核上执行非对称的工作负载，以提供确定的性能。但是本发明的范围并不局限于此，在一些实施例中，可以利用完全集成电压调节器(FIVR)实施来实现独立电压/频率控制，在所述FIVR实施中处理器内的每个内核均具有其自己的电压调节器。也就是说，包括多个内核的单个半导体管芯可以进一步包括多个独立的电压调节器，每个电压调节器与给定的内核相关联。此外，可以设置一个或多个额外的电压调节器，用于与处理器内的其它部件(例如，非内核逻辑、存储器控制逻辑、功率控制单元等)一起使用。自然，在一些实施例中，单个电压调节器可以与一个或多个内核和/或处理器的其它部件相关联。在一个实施例中，可以为处理器的非内核电路提供专用电压调节器，其将允许非内核以不同的电压和频率运行。对于计算中心工作负载，非内核能够以较低的电压和频率运行，导致向套接字级别的较高内核频率应用省电。对于存储器和IO密集工作负载，非内核能够以较高电压和频率运行，同时内核能够以较低电压/频率运行，补偿非内核中的较高功率。
在一些实施例中，ACPI表可以扩展为包括关于这些单个集成电压调节器的信息以使能每内核P状态控制。例如，可以使用4位字段来传递P状态信息并将其进行映射以控制用于每个调节器的电压逻辑。因此，利用本发明的实施例，可以控制每个内核以不同频率和/或电压操作用于不对称工作负载。作为一个例子，能够控制多个内核中的一个或几个以较高的频率和/或电压操作，同时控制剩余的内核以较低电压/频率组合操作，从而保留在给定的热设计功率(TDP)范围内。这样，对于给定的工作负载能够实现确定的且优选的性能功能选择。
例如，以第一方式寻求较高的性能级别来处理数据的内核能够以较高的电压/频率操作(这种内核可以执行例如数据处理使用(如，数据复制服务、数据分析、奇偶性计算等)的任务)，同时执行例如管理任务的内核能够以较低电压/频率运行以提供用于TDP约束环境的最优混合。因此，不同于在可能的(以所谓的加速模式)给定热或TDP预算时投机性地使所有内核以较高频率运行，实施例以单个内核为基础提供了确定性特性。
现在参照图1，示出了根据本发明实施例的系统的一部分的框图。如图1所示，系统100可以包括各种部件，包括处理器110，其在图中示出为多内核处理器。处理器110可以经由外部电压调节器160耦合到电源150，该外部电压调节器160可以执行第一电压转换来向处理器110提供初始调节的电压。
如图所示，处理器110可以是包括多个内核120a-120n的单模处理器。另外，每个内核可以与单个电压调节器125a-125n相关联。因此，可以提供完全集成电压调节器(FIVR)实施，从而允许对电压的细粒度控制以及对每个单个内核的功率和性能的细粒度控制。
仍参照图1，处理器内可以存在另外的部件，包括输入/输出接口132、另一接口134和集成存储器控制器136。如图所示，这些部件中的每个均可以由另一集成电压调节器125x供电。在一个实施例中，接口132可以遵照快速路径互连(QPI)协议，该协议提供包括多个层的高速缓存一致性协议中的点对点(PtP)链路，所述多个层包括物理层、链路层和协议层。接下来，接口134可以遵照高速外围设备互连(PCIeTM)规范，例如，PCI ExpressTMv2.0规范(2007年1月17日公布)。虽然为了便于图示而未示出，但是可以理解的是，在处理器110内可以存在另外的部件，例如非内核逻辑、功率控制单元，以及例如内部存储器的其它部件(如，一级或多级高速缓冲存储器分级结构等)。此外，虽然图1的实施中示出了集成电压调节器，但是实施例并不局限于此。
现在参照图2，示出了根据本发明一个实施例的方法的流程图。在一个实施例中，可以通过控制器执行方法200，所述控制器例如为处理器的集成功率控制单元(PCU)。然而，可以理解的是，本发明的范围并不局限于此，方法200可以由系统内例如管理引擎的其它控制器执行。
结合图2，方法200可以开始于在PCU中接收性能状态改变请求(方框210)。例如，在许多实现中，该请求可以接收自OS或系统软件。作为一个例子，该请求可以对应于改变用于一个或多个内核的P状态的请求。也就是说，在这种实现中，OS可以知道本发明实施例所提供的每内核P状态控制。在其它实施例中，即使当OS或系统软件不知道该特征时，如本文所讨论的也可以接收并处理性能状态改变请求。
在菱形220处，确定是否请求增加性能。也就是说，请求可以是更高性能级别的识别(例如，对应于低于当前P状态，如从P1状态进入到P0状态的请求)。还应注意的是，该确定还可以确认可以从当前状态改变P状态。如果是，则控制进行到方框230。在方框230处，可以做出关于选择一个或多个内核来独立于至少另一内核增加其电压的确定(方框230)。作为该决定的例子，基于依赖例如全部管芯电流、功率、温度和微架构活动(例如，加载/存储缓冲器、线程调度程序等)的各种因素的TDP余量，PCU可以确定增加电压和相关联的频率。例如，当确定多内核处理器的一部分为冷却器(并以较低电压/频率操作)时，该部分中的内核可被选择用于增加的电压和频率。
当确定选择一个或多个内核用于增加的电压时，控制进行到方框240，其中为所选择的内核计算新的电压和频率。这种计算可以至少一部分基于用于处理器的TDP规范、Icc净空(headroom)等。
仍参照图2，控制接着进行到方框250，其中可以将用于新电压的控制信号发送到与一个或多个内核相关联的电压调节器。作为一个例子，该控制信号可以是数字控制信号或者可以是模拟信号，从而使得电压调节器开始改变不同电压级别。因此，可以调整与内核相关联的FIVR，从而向内核输出更新后的电压。因此，控制进行到方框260，其中内核可以以所选择的电压操作。需要注意的是，因为在多个实施例中，电压调节器可以集成到处理器中，所以该调整可以伴随与片外调节器相比具有降低的延时而发生。
如果相反地在菱形220处确定请求降低性能，则控制进行到方框270。在方框270处，可以做出关于选择一个或多个内核独立于至少另一内核降低电压的确定(方框270)。这种决定可以基于如上所述的因素，并可以包括许可移动到不同P状态的确定。
当确定选择一个或多个内核用于降低的电压时，控制进行到方框275，在其中可以为所选择的内核计算新的电压和频率。控制接着进行到方框280，其中可以将用于新电压的控制信号发送到与一个或多个内核相关联的电压调节器，以使得与内核相关联的FIVR向内核输出降低的电压。因此，控制进行到方框290，其中内核可以以所选择的电压操作。虽然图2的实施例示出了该特定实现，但是可以理解的是，本发明的范围并不局限于此。例如，上述讨论假设PCU和内核是例如多内核处理器的同一半导体管芯的部分。在其它实施例中，内核可以在独立的管芯中但是在同一多芯片封装中。在又一实施例中，内核可以在分离的封装中但其电压/频率被例如使用协调电压调节器而共同控制。
一个可选实施例是处理器不包括集成调节器的一种实现。在这种处理器中，实施例仍能适应提供每内核P状态控制。为此，相反地在方框250或280处，能够例如直接向内核提供用于不同电压的控制信号，其中内核能够基于接收到的电压而提供电压调整。在又一实施例中，在方框250和280处，能够向外部电压调节器在片外提供用于改变的电压的控制信号。该控制信号可以在单个管脚或多个管脚上传输，其中多个管脚中的每一个与不同的电压级别相关联，以使得外部电压调节器提供多个电压中的一个。具体地在这种实现中，外部电压调节器可以输出多个电压信号，其能耦合到处理器并接着例如耦合到处理器的电压传输逻辑，该电压传输逻辑可以进一步从功率控制单元接收控制信号，以如由功率控制单元所确定地，能够将所选择的电压提供到相应的内核。
在另一实施例中，例如，在多个内核用于一个OS和不同数目的内核用于不同OS的多OS系统中，一个OS域内的每个内核能被静态设置为固定的(并且可能是不同的)V/F，同时在另一OS域内的内核在操作期间可以动态改变V/F。例如，一个OS域可以用于确定性操作(例如，用于系统的管理操作)并因而能得益于固定的V/F控制。相反地，根据本发明的实施例，在其中执行各种用户级别应用的OS域可以具有非确定性的工作负载，因而得益于动态独立V/F控制。
在一些实施例中，对于内核V/F的动态控制，取决于需要的负载需求，PCU能独立于OS而监视微架构活动，并确定是否能动态改变一个或多个内核的V/F以降低/增加功率。
现在参照图3，示出了根据本发明一个实施例的方法的流程图。如图3所示，方法300可以由处理器的功率控制单元执行。因而，当OS不知道由本发明的实施例所提供的每内核P状态能力时，方法300是适合的。在又一实施例中，在OS知道P状态能力的情况下，可以结合如上所述的方法200来执行方法300，以提供改善的内核P状态的动态控制。
如图3所示，方法300可以开始于监视一个或多个内核的微架构活动(方框310)。但是本发明的范围并不局限于此，这种活动可以包括确定在时间窗执行的大量指令、每时间窗的引退等。
响应于从微架构活动获得的信息，功率控制单元可以执行分析。更具体地，在方框320处，功率控制单元可以分析活动以及处理器的负载需求。例如，负载需求可以基于关于调度到内核的大量线程的信息和为其调度这些线程的处理器的类型。
然后控制进行到菱形330，其中功率控制单元可以确定动态调整用于一个或多个内核的至少一个电压/频率是否合适。例如，如果活动和负载需求指示在功率和性能之间发生合适的权衡，则功率控制单元可以选择不动态调整任何电压/频率组合。因此，方法300可以结束。
否则，如果确定调整用于给定内核的至少一对电压/频率，则控制替代地进行到方框340。这里，可以为所选择的内核计算新的电压和频率对。
仍参照图3，控制接着进行到方框350，其中可以将用于新电压的控制信号发送到与待以新电压更新的一个或多个内核相关联的电压调节器。这样，可以调整与内核相关联的FIVR，从而向内核输出更新后的电压。因此，控制进行到方框360，其中内核可以以所选择的电压进行操作。虽然在图3的实施例中示出该特定实现，但是可以理解，本发明的范围并不局限于此。
例如，在其它实施例中，不仅可以动态改变一个或多个内核的V/F，而且还可以改变非内核频率和电压，以支持要求的内核V/F需求。非内核频率对于OS是不可见的，但是有助于整个管芯省电。非内核省电可以应用于将导致增加内核性能的内核功率。类似地，可以应用内核省电以增加非内核电压/频率，来适应要求更高非内核频率的工作负载。在一些实现中，可以使用图3的方法300来执行该动态内核改变。
现在参照图4，示出了根据本发明实施例的处理器的框图。如图4所示，处理器400可以是包括多个内核410a-410n的多内核处理器。在一个实施例中，这种内核中的每一个可以被配置为以多个电压和/或频率进行操作。另外，可以独立地控制每个内核，使其如上所述以所选择的电压和/或频率进行操作。为此，每个内核可以与相应的电压调节器412a-412n相关联。可以经由互连415将各种内核耦合到包括各种部件的非内核420。如图所示，非内核420可以包括是最后一级高速缓存的共享高速缓存430。另外，非内核可以包括集成存储器控制器440、各种接口450和功率控制单元455。
在各种实施例中，功率控制单元455可以与OS功率管理代码进行通信。例如，基于从OS接收到的请求和关于内核所处理的工作负载的信息，功率控制单元455可以确定用于操作每个内核的电压和频率的适当组合，例如结合图2在以上所描述的。例如，功率控制单元455可以包括表，该表所具有的每个条目与每个内核以其正在执行的电压和频率相关联。另外，单元455可以包括具有关于TDP或其它热预算的信息的储存器。基于所有的该信息，功率控制单元455能够动态且独立地控制用于一个或多个内核的频率和/或电压，以能够进行确定性操作和提供给内核非对称的工作负载，同时保持在TDP预算以内，且进一步地不需要投机性的加速模式操作。因此，响应于这种计算，功率控制单元455可以生成多个控制信号，以使得电压调节器因而控制提供到相应内核的电压。
另外，如结合图3在以上所描述的，功率控制单元455可以独立地确定对于一个或多个内核改变电压/频率是合适的。在一些实现中，功率控制单元455所执行的分析可以至少部分地基于活动监视器逻辑所确定的预测信息，所述活动监视器逻辑可以是功率控制单元的一部分。该逻辑可以包括用于存储与操作内核相关联的信息的缓冲器。活动监视器可以从各种内核接收关于其当前活动级别的输入数据。可以以各种方式布置所述活动监视器的缓冲器。在一个实施例中，缓冲器可适用于为每个内核存储与每个功率状态改变事件相关联的时间戳的指示。因此，活动监视器拦截内核进入和离开给定活动状态的事件并对其标记时间戳。因而该受监视的数据可以包括时间戳数据以及活动状态，用于在存储间隔期间表明每个内核处于给定状态达多长时间，并且可以提供给例如功率控制单元的预测器，该预测器可以使用该信息来确定用于下一间隔的预测的内核状态，而该状态可以用于选择操作内核的独立频率和/或电压。
再参照图4，处理器400可以例如经由存储器总线与系统存储器460进行通信。另外，通过接口450，能够与各种片外部件(例如，外围设备、大容量储存器等)建立连接。虽然以图4的实施例示出了该特定实现，但是本发明的范围并不局限于此。
现在参照图5，示出了根据本发明的一个实施例的处理器内核的框图。如图5所示，处理器内核500可以是多级管线乱序处理器。如图5所示，内核500可以操作作为集成电压调节器509的结果的各种电压和频率。在各种实施例中，该调节器可以例如从外部电压调节器接收输入电压信号，并且还可以例如从耦合到内核500的非内核逻辑接收一个或多个控制信号。
如图5所示，内核500包括前端单元510，其可以用于获取待执行的指令，并使其在处理器中准备稍后使用。例如，前端单元510可以包括获取单元501、指令高速缓存503和指令解码器505。在一些实施中，前端单元510还可以包括踪迹高速缓存，以及微代码储存器和微操作储存器。获取单元501可以例如从存储器或指令高速缓存503处获取宏指令，并且将所述宏指令供应给指令解码器505以将其解码为由处理器执行的原语，即微操作。
耦合在前端单元510和执行单元520之间的是乱序(OOO)引擎515，其可以用于接收微指令并且将其准备用于执行。更具体地，OOO引擎515可以包括各种缓冲器，用于重新排序微指令流，并分配执行所需的各种资源，以及提供将逻辑寄存器重命名到各种寄存器文件(例如，寄存器文件530和扩展寄存器文件535)中的储存单元上。寄存器文件530可以包括用于整数或浮点数操作的分离的寄存器文件。扩展寄存器文件535可以提供用于向量大小(vector-sized)的单位的储存，例如每寄存器256或512比特。
在执行单元520中可以存在各种资源，例如包括：各种整数、浮点数、单指令多数据(SIMD)逻辑单元以及之外的其它专用硬件。例如，这种执行单元可以包括一个或多个算术逻辑单元(ALU)522，以及之外的其它这种执行单元。
可以将来自执行单元的结果提供至引退逻辑，即重排序缓冲器(ROB)540。更具体地，ROB 540可以包括各种阵列和逻辑，用于接收与执行的指令相关联的信息。然后该信息由ROB 540检查以确定是否能合理地引退指令并且将结果数据提交到处理器的架构状态，或者确定是否发生防止指令正确引退的一个或多个异常。自然，ROB 540可以处理与引退相关联的其它操作。
如图5所示，ROB 540耦合到高速缓存550，在一个实施例中该高速缓存550可以是低级别高速缓存(例如，L1高速缓存)，但是本发明的范围并不局限于此。另外，执行单元520能够直接耦合到高速缓存550。从高速缓存550，可以发生与更高级别高速缓存、系统存储器等的数据通信。虽然以图5的实施例示出该高级别，但是可以理解的是本发明的范围并不局限于此。例如，虽然图5的实施是关于例如所谓的x86指令集结构(ISA)的乱序机器，但是本发明的范围并不局限于此。也就是说，可以以有序处理器、精简指令集计算(RISC)处理器(例如基于ARM的处理器)，或者可以经由仿真引擎和相关联的逻辑电路仿真不同ISA的指令和操作的ISA的其它类型的处理器来实现其它实施例。
可以用不同的系统类型实现实施例。现在参照图6，示出了根据本发明的实施例的系统的框图。如图6所示，多处理器系统600是点对点互连系统，且包括经由点对点互连650耦合的第一处理器670和第二处理器680。如图6所示，处理器670和680的每一个可以是多内核处理器，包括第一和第二处理器内核(即，处理器内核674a和674b以及处理器内核684a和684b)，但是在处理器中可以潜在地存在更多的内核。利用存在于处理器内的多个独立的电压调节器(为了简化图6的实施例的图示而未示出)，每个内核可以以独立的电压/频率操作。
仍参照图6，第一处理器670还包括存储器控制中心(MCH)672和点对点(P-P)接口676和678。类似地，第二处理器680包括MCH 682和P-P接口686和688。如图6所示，MCH 672和682将处理器耦合到各自的存储器，即存储器632和存储器634，其可以是系统存储器(例如，DRAM)的本地附加到各自的处理器上的一部分。第一处理器670和第二处理器680可以分别经由P-P互连652和654耦合到芯片组690。如图6所示，芯片组690包括P-P接口694和698。
此外，芯片组690包括接口692，用于通过P-P互连639将芯片组690与高性能图形引擎638耦合。另外，芯片组690可以包括接口695，其可以是与储存器619接口的储存器控制器。接下来，芯片组690可以经由接口696耦合到第一总线616。如图6所示，各种输入/输出(I/O)设备614和总线桥618可以耦合到第一总线616，该总线桥618将第一总线616耦合到第二总线620。在一个实施例中，各种设备可以耦合到第二总线620，例如包括键盘/鼠标622、通信设备626和可以包括代码630的数据储存单元628(例如，磁盘驱动器或其它大容量储存设备)。此外，音频I/O 624可以耦合到第二总线620。实施例可以合并到包括移动设备(例如，智能蜂窝电话、平板电脑、上网本等)的其它类型的系统中。
实施例可以以代码实施，且存储在其上具有指令的存储介质上，所述指令用于对系统编程以执行指令。存储介质包括但不限于任意类型的非瞬态存储介质，例如磁盘，包括软盘、光盘、固态盘(SSD)、光盘只读存储器(CD-ROM)、可重写光盘(CD-RW)以及磁光盘；半导体设备，例如只读存储器(ROM)、诸如动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM)的随机存取存储器(RAM)、可擦除可编程只读存储器(EPROM)、闪速存储器、电可擦除可编程只读存储器(EEPROM)、磁卡或光卡，或适合于存储电子指令的任意其它类型的介质。
虽然已经结合有限数量的实施例描述了本发明，但是本领域的技术人员可以从中理解多种修改和变型。打算的是，随附权利要求覆盖落入本发明的真正精神和范围内的所有这种修改和变型。

Claims (20)

1.一种处理器，包括：
多个内核，所述多个内核中的至少一个内核包括用于对指令进行解码的解码器、用于执行所解码的指令的至少一个执行单元、以及至少一个包含在内核中的高速缓存，其中，所述多个内核中的该至少一个内核包括乱序管线；
共享高速缓存；
集成存储器控制器；以及
功率控制逻辑，用于控制独立于向所述多个内核中的至少第二内核提供电压/频率，而向所述多个内核中的第一内核提供电压/频率，其中，所述第一内核和所述第二内核执行非对称的工作负载，所述功率控制逻辑至少部分地基于所述处理器的工作负载、热设计功率(TDP)预算和温度来确定是否更新所述第一内核的电压/频率，并且响应于所述确定而更新提供给所述第一内核的电压/频率，其中，所述功率控制逻辑发送控制信号给电压调节器，以使所述电压调节器向所述第一内核提供更新后的电压。
2.根据权利要求1所述的处理器，其中，所述功率控制逻辑控制所述第一内核的电压/频率，而同时保持在热预算以内。
3.根据权利要求2所述的处理器，其中，所述温度包括所述第一内核的温度。
4.根据权利要求1所述的处理器，其中，所述多个内核和所述共享高速缓存被形成在单个半导体管芯上。
5.根据权利要求4所述的处理器，其中，所述电压调节器包括形成在所述单个半导体管芯上的集成电压调节器。
6.根据权利要求4所述的处理器，还包括形成在所述单个半导体管芯上的多个集成电压调节器。
7.根据权利要求6所述的处理器，其中，所述多个集成电压调节器与所述多个内核中的至少一个相关联。
8.根据权利要求6所述的处理器，其中，所述多个集成电压调节器向所述多个内核中的至少一个提供独立的电压。
9.根据权利要求1所述的处理器，其中，所述功率控制逻辑接收来自操作系统(OS)的用来在OS运行期间对所述多个内核中的一个或多个内核的电压/频率进行动态更新的性能状态改变请求。
10.根据权利要求1所述的处理器，其中，所述功率控制逻辑控制独立于向所述多个内核中的至少第二内核提供电压/频率，而向所述第一内核提供电压/频率。
11.根据权利要求1所述的处理器，其中，所述第一内核接收控制信息和第一电压，并且响应于所述控制信息而将所述第一电压调整为第二电压。
12.根据权利要求1所述的处理器，还包括非内核电路，所述非内核电路包括所述功率控制逻辑。
13.根据权利要求12所述的处理器，其中，所述非内核电路针对第一工作负载而运行在第一电压和第一频率，针对第二工作负载而运行在第二电压和第二频率。
14.根据权利要求1所述的处理器，其中，所述功率控制逻辑包括活动监视器，其监视所述多个内核的微架构活动，所述微架构活动包括指令执行信息。
15.根据权利要求14所述的处理器，其中，所述功率控制逻辑基于来自所述活动监视器的信息来预测所述第一内核在未来时期内的使用情况。
16.根据权利要求1所述的处理器，其中，所述电压调节器包括外部电压调节器。
17.根据权利要求16所述的处理器，其中，所述处理器还包括耦合到所述外部电压调节器的多个集成电压调节器，用于向所述多个内核中的至少一个提供独立的电压。
18.根据权利要求1所述的处理器，其中，所述功率控制逻辑调整第一组内核，使其独立于第二组内核而以增加的电压/频率来执行，从而维持所述处理器的热设计功率(TDP)预算。
19.根据权利要求1所述的处理器，其中，所述至少一个执行单元包括单指令多数据逻辑单元。
20.根据权利要求1所述的处理器，其中，所述多个内核中的至少一个包括精简指令集计算处理器。
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