CN105684141B - 到晶片中的异构沟道材料集成 - Google Patents

到晶片中的异构沟道材料集成 Download PDF

Info

Publication number
CN105684141B
CN105684141B CN201480058901.4A CN201480058901A CN105684141B CN 105684141 B CN105684141 B CN 105684141B CN 201480058901 A CN201480058901 A CN 201480058901A CN 105684141 B CN105684141 B CN 105684141B
Authority
CN
China
Prior art keywords
substrate
type device
thermal budget
semiconductor device
insulator layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480058901.4A
Other languages
English (en)
Other versions
CN105684141A (zh
Inventor
S·S·宋
C·F·耶普
Z·王
N·N·莫江德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105684141A publication Critical patent/CN105684141A/zh
Application granted granted Critical
Publication of CN105684141B publication Critical patent/CN105684141B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

用于将异构沟道材料集成到半导体器件中的方法，以及集成异构沟道材料的半导体器件。一种用于制造半导体器件的方法包括以第一热预算来处理第一材料的第一基板以制造p型器件。该方法进一步包括将第二材料的第二基板耦合到该第一基板。该方法还包括以小于该第一热预算的第二热预算处理该第二基板以制造n型器件。该p型器件和n型器件可以协作以形成互补器件。

Description

到晶片中的异构沟道材料集成
背景技术
领域
本公开的各方面涉及半导体器件，并且更具体而言涉及具有不同热预算的材料的异构沟道材料集成。
背景
半导体芯片级结合器件被用于多种消费者和商业应用。半导体器件通常是由单一类型的材料制作的。半导体器件也可以由基于晶格匹配和兼容晶体结构而生长到基板上的不同类型的材料制成。由复合材料(诸如III-V族材料)制造的半导体器件(即，该半导体结构多于一种材料)通常生长在砷化镓或者其他复合半导体基板上。因为硅和复合半导体材料的晶体结构之间晶格失配，所以这些器件难以与制造在硅上的电子器件集成。
概述
根据本公开一方面的用于制造器件的方法包括以第一热预算处理第一材料的第一基板以制造p型器件。此类方法进一步包括将第二材料的第二基板耦合到该第一基板。该方法还包括以小于该第一热预算的第二热预算处理第一基板以制造n型器件。该p型器件和n型器件可以协作以形成互补器件。
根据本公开另一方面的半导体器件包括具有第一热预算的第一材料的第一基板。该第一基板可包括p型器件。此类器件还包括耦合到该第一基板的具有第二热预算的第二材料的第二基板。该第二基板可包括n型器件。该p型器件和n型器件可以协作以形成互补器件。
根据本公开的一方面的另一半导体器件包括用于在具有第一热预算的第一材料的第一基板中传导第一载荷子类型的第一装置。此类器件还包括用于在第二基板中传导第二载荷子类型的第二装置。该第二基板可以是具有第二热预算的第二材料并且耦合到第一基板。该第一装置和第二装置可以协作以形成互补器件。
这已较宽泛地勾勒出本公开的特征和技术优势以便下面的详细描述可以被更好地理解。本公开的附加特征和优点将在下文描述。本领域技术人员应该领会，本公开可容易地被用作修改或设计用于实施与本公开相同的目的的其他结构的基础。本领域技术人员还应认识到，这样的等效构造并不脱离所附权利要求中所阐述的本公开的教导。被认为是本公开的特性的新颖特征在其组织和操作方法两方面连同进一步的目的和优点在结合附图来考虑以下描述时将被更好地理解。然而，要清楚理解的是，提供每一幅附图均仅用于解说和描述目的，且无意作为对本公开的限定的定义。
附图简述
为了更全面地理解本公开，现在结合附图参阅以下描述。
图1解说了本公开一方面中的半导体器件的侧视图。
图2解说了本公开一方面中的将复合半导体基板耦合到不同材料系统半导体器件。
图3解说了本公开一方面中的形成在不同材料系统半导体器件上的复合半导体器件的侧视图。
图4是解说根据本公开的一方面的制作谐振器的方法的工艺流程图。
图5是示出其中可有利地采用本公开的配置的示例性无线通信系统的框图。
图6是解说根据一种配置的用于半导体组件的电路、布局、以及逻辑设计的设计工作站的框图。
详细描述
以下结合附图阐述的详细描述旨在作为各种配置的描述，而无意表示可实践本文中所描述的概念的仅有的配置。本详细描述包括具体细节以便提供对各种概念的透彻理解。然而，对于本领域技术人员将显而易见的是，没有这些具体细节也可实践这些概念。在一些实例中，以框图形式示出众所周知的结构和组件以避免湮没此类概念。如本文所述的，术语“和/或”的使用旨在代表“可兼性或”，而术语“或”的使用旨在代表“排他性或”。
高迁移率传导沟道是高性能晶体管所期望的。此类晶体管通常使用III-V族材料制成。然而，III-V族材料的窄能量带隙可能不能提供1nA/μm以下的泄漏电流。对于低功率器件，硅沟道是期望的，因为硅沟道能够防止低泄漏电流，然而，这些器件可以具有比III-V族器件低的性能。
III-V族沟道到半导体晶片(例如，硅)中的异构沟道集成，或者III-V族器件与其他半导体材料系统到相同晶片中的集成是困难的。由于不同的材料、以及热应力和机械应力而复杂化的外延生长过程使得异构材料集成变复杂。由于一些材料系统的热预算(例如，硅>1000C)以及III-V族材料的热预算限制(<700C)，将单独的半导体材料系统与III-V族器件集成到单一晶片中是更为困难的。
本公开的一方面处理不同级或“层”中的不同半导体材料系统(例如，硅和III-V族)器件。本公开的一方面允许相同电路内的硅处理和III-V族处理而不影响先前的结构化过程步骤。
图1解说了本公开一方面中的半导体器件的侧视图。晶片100包括第一基板102、半导体器件104、界面层106和互连108。晶片100可包括许多集成电路，其可以通过将晶片100划片、分裂或切割成片来生产。由此，图1可解说晶片100或者作为晶片100的一部分的半导体芯片。
本公开的一方面使用半导体(例如，硅(Si))基板作为第一基板102。进一步，半导体器件104(其可以形成在第一基板102上(或中))可以是金属氧化物半导体场效应晶体管(MOSFET)。该半导体器件104还可以是隧穿场效应晶体管(TFET)。晶片100被处理以创建半导体器件104以及创建互连108。第一基板102被处理直到半导体器件104和互连已达到处理中的特定点。该点可以在任意期望的时间，但是可能至多到局部互连层(例如，中端(MOL))或者第一导电层(例如，金属一(M1))。
界面层106随后被耦合到第一基板102的绝缘体层110。界面层106可以是非晶态层(诸如二氧化硅(SiO2))、晶体层，或者有助于将另一材料结合或耦合到晶片100的任何其他层或材料，并且还提供基板102上的器件与后续处理的器件的电隔离。
图2解说了本公开一方面中的复合半导体基板到半导体器件(例如，硅)的耦合。耦合结构200示出了第二基板202被耦合到晶片100的界面层106。第二基板202的耦合可以是将第二基板202耦合到晶片100的结合或“智能切割”工艺。该耦合也可以是氧化-氧化过程。第二基板202的耦合也可以使用退火、等离子焊或将第二基板202耦合到晶片100的其他形式来执行。
第二基板202可以是III-V族材料、II-VI族材料或者具有与第一基板102不同的热预算的另一材料。作为示例，并且不作为限定，第一基板102可以是具有大于1000摄氏度的热预算的硅基板。第二基板202可以是具有小于700摄氏度的热预算的III-V族基板(例如，砷化镓(GaAs)基板)。规定该降低的热预算是因为复合III-V族材料的结晶键和/或共价键会在用于半导体处理的较高温度损坏。
第一基板102和第二基板202之间的热预算差可以大到足以允许处理第二基板202而不实质上影响先前在第一基板102上执行的处理。第二基板202可以直接耦合到界面层102，或者可以耦合到第一基板102的另一层。进一步地，在将第二基板耦合到晶片100之前或之后可以执行附加步骤(例如，使第二基板202变薄)。
图3解说了本公开一方面中的形成在半导体器件上的复合半导体器件300的侧视图。复合半导体器件300包括形成在第二基板202上(或中)的半导体器件302第二基板202可以被进一步处理以将互连108延伸通过第二基板202且通过耦合到第二基板202的附加处理层。在III-V族处理的情形(在小于700摄氏度执行)中，在形成半导体器件302之后，半导体器件104(可以是MOSFET)在电气性能上实质上并未改变。
在本公开一方面，半导体器件302还可以是MOSFET和/或TFET器件。在该配置中，半导体器件104和半导体器件302在它们各自的沟道中使用不同载荷子。半导体器件104和半导体器件302可以随后被组合以创建互补金属氧化物半导体(CMOS)器件。
高移动性传导沟道是高性能晶体管所期望的。当用硅制造时，取决于半导体器件104的掺杂物密度，电子迁移率在90和1500cm2/V-s之间变化，并且空穴迁移率在50和450cm2/V-s之间变化。在III-V族材料(诸如砷化镓)中，电子迁移率为～8500cm2/V-s，并且空穴迁移率相对恒定在～400cm2/V-s。
根据本公开的一方面，互补器件可以在半导体器件104中使用p型载子，以及在半导体器件302中使用n型器件以提供增加的载子迁移率。进一步地，因为半导体器件302的处理能够为单一电荷载荷子定制，所以在第二基板202中使用的III-V族材料的窄能量带隙可以被设计成辅助包含值低于1nA/μm的泄漏电流。替换地，半导体器件302可以用于其中泄漏电流不会使得总体电路功能降级的应用中。第二基板202的使用可以将复合半导体器件300的性能增加到仅由单基板材料制成的类似电路之上。
作为示例，并且不作为限定，半导体器件104可以是p型器件(PMOS器件)，并且半导体器件302可以是n型器件(NMOS器件)。半导体器件104和半导体器件302可以随后耦合在一起以创建互补器件(CMOS)。半导体器件104的处理和/或对用于第一基板102的材料的选择可以随后针对半导体器件104中的沟道中的特定载荷子改进或者甚至优化。类似地，半导体器件302的处理和/或对用于第二基板202的材料的选择可以随后针对半导体器件302中的沟道中的特定载荷子改进或者甚至优化。本公开允许通过使用第一基板102和第二基板202来定制沟道特征。进一步地，本公开允许选择沟道载荷子和器件性能，并且在当处理半导体器件302之时维持半导体器件104的性能。
在III-V族材料的情形中，用以创建半导体器件302的III-V族处理使用对用以创建半导体器件104的过程步骤具有可忽略的影响的温度。由此，创建半导体器件302对半导体器件104具有可忽略的影响。
在本公开的一方面内，半导体器件104还可以被指派特定的用途，而半导体器件302可以被指派不同的用途。例如，半导体器件104可以被用于采用复合半导体器件300的总体电路(诸如，调制解调器)的低功率部分。在本公开的此类一方面，半导体器件302可被用作电路(诸如中央处理单元(CPU))的高性能部分。
图4是解说根据本公开的一方面的制造集成电路的方法400的工艺流程图。在框402，第一材料的第一基板以第一热预算处理以制造p型器件。在框404，第二材料的第二基板被耦合到第一基板。在框406，第二基板被以小于该第一热预算的第二热预算处理从而制造n型器件。在一配置中，该p型器件和n型器件协作以形成互补器件。例如，半导体器件104可以是p型器件(PMOS器件)，并且半导体器件302可以是n型器件(NMOS器件)。如图3中所示，半导体器件104和半导体器件302可以随后耦合在一起以创建互补器件(CMOS)。
根据本公开的一方面，复合器件包括用于在具有第一热预算的第一材料的第一基板中传导第一载荷子类型的第一装置。在本公开的一方面中，第一装置可以是配置成执行该第一装置叙述的功能的半导体器件104和/或其他结构。复合半导体器件还包括用于在耦合到第一基板的具有第二热预算的第二材料的第二基板中传导第二载荷子类型的第二装置。该第一装置和第二装置可以协作以形成互补器件。在本公开的一方面中，第二装置可以是配置成执行该第二装置叙述的功能的半导体器件302和/或其他结构。在另一方面，前述装置可以是被配置成执行由前述装置所述的功能的任何模块或任何设备。
图5是示出其中可有利地采用本公开的一方面的示例性无线通信系统500的框图。出于解说目的，图6示出了三个远程单元520、530和550以及两个基站540。将认识到，无线通信系统可具有远多于此的远程单元和基站。远程单元520、530和550包括IC器件525A、525C和525B，这些IC器件包括所公开的器件。将认识到，其他设备(诸如基站、交换设备、和网络装备)也可以包括所公开的异构沟道材料。图5示出了从两个基站540到远程单元520、530和550的前向链路信号580，以及从远程单元520、530和550到两个基站540的反向链路信号590。
在图5中，远程单元520被示为移动电话，远程单元530被示为便携式计算机，而远程单元550被示为无线本地环路系统中的固定位置远程单元。例如，这些远程单元可以是移动电话、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数据助理)、启用GPS的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、位置固定的数据单元(诸如仪表读数装置)、或者存储或取回数据或计算机指令的其他设备、或者其组合。尽管图5解说了根据本公开的各方面的远程单元，但本公开并不被限定于所解说的这些示例性单元。本公开的各方面可以合适地在包括所公开的器件的许多设备中使用。
图6是解说用于半导体组件(诸如以上公开的器件)的电路、布局以及逻辑设计的设计工作站的框图。设计工作站600包括硬盘601，该硬盘601包含操作系统软件、支持文件、以及设计软件(诸如Cadence或OrCAD)。设计工作站600还包括促成对电路610或半导体组件612(诸如具有异构沟道材料的器件)的设计的显示器602。提供存储介质604以用于有形地存储电路610或半导体组件612的设计。电路610或半导体组件612的设计可以用文件格式(诸如GDSII或GERBER)存储在存储介质604上。存储介质604可以是CD-ROM、DVD、硬盘、闪存、或者其他合适的设备。此外，设计工作站600包括用于从存储介质604接受输入或者将输出写到存储介质604的驱动装置603。
存储介质604上记录的数据可指定逻辑电路配置、用于光刻掩模的图案数据、或者用于串写工具(诸如电子束光刻)的掩模图案数据。该数据可进一步包括与逻辑仿真相关联的逻辑验证数据，诸如时序图或网电路。在存储介质604上提供数据通过减少用于设计半导体晶片的工艺数目来促成电路610或半导体组件612的设计。
技术人员将进一步领会，结合本文的公开所描述的各种解说性逻辑框、模块、电路、和算法步骤可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这一可互换性，各种解说性组件、块、模块、电路、和步骤在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体系统的设计约束。技术人员可针对每种特定应用以不同方式来实现所描述的功能性，但此类实现决策不应被解读为致使脱离本公开的范围。
结合本文的公开所描述的各种解说性逻辑框、模块、以及电路可用设计成执行本文中描述的功能的通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其他可编程逻辑器件、分立的门或晶体管逻辑、分立的硬件组件、或其任何组合来实现或执行。通用处理器可以是微处理器，但在替换方案中，处理器可以是任何常规的处理器、控制器、微控制器、或状态机。处理器还可以被实现为计算设备的组合，例如DSP与微处理器的组合、多个微处理器、与DSP核心协作的一个或更多个微处理器、或任何其他此类配置。
结合本公开所描述的方法或算法的步骤可直接在硬件中、在由处理器执行的软件模块中、或在这两者的组合中体现。软件模块可驻留在RAM、闪存、ROM、EPROM、EEPROM、寄存器、硬盘、可移动盘、CD-ROM或本领域中所知的任何其他形式的存储介质中。示例性存储介质耦合到处理器以使得该处理器能从/向该存储介质读写信息。替换地，存储介质可以被整合到处理器。处理器和存储介质可驻留在ASIC中。ASIC可驻留在用户终端中。替换地，处理器和存储介质可作为分立组件驻留在用户终端中。
在一个或多个示例性设计中，所描述的功能可以在硬件、软件、固件、或其任何组合中实现。如果在软件中实现，则各功能可以作为一条或多条指令或代码存储在计算机可读介质上或藉其进行传送。计算机可读介质包括计算机存储介质和通信介质两者，其包括促成计算机程序从一地向另一地转移的任何介质。存储介质可以是可被通用或专用计算机访问的任何可用介质。作为示例而非限定，这样的计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储或其他磁存储设备、或能被用来携带或存储指令或数据结构形式的指定程序代码手段且能被通用或专用计算机、或者通用或专用处理器访问的任何其他介质。任何连接也被正当地称为计算机可读介质。例如，如果软件是使用同轴电缆、光纤电缆、双绞线、数字订户线(DSL)、或诸如红外、无线电、以及微波之类的无线技术从web网站、服务器、或其他远程源传送而来，则该同轴电缆、光纤电缆、双绞线、DSL、或诸如红外、无线电、以及微波之类的无线技术就被包括在介质的定义之中。如本文中所使用的盘(disk)和碟(disc)包括压缩碟(CD)、激光碟、光碟、数字多用碟(DVD)、软盘和蓝光碟，其中盘(disk)往往以磁的方式再现数据而碟(disc)用激光以光学方式再现数据。上述的组合应当也被包括在计算机可读介质的范围内。
提供对本公开的先前描述是为使得本领域任何技术人员皆能够制作或使用本公开。对本公开的各种修改对本领域技术人员来说都将是显而易见的，且本文中所定义的普适原理可被应用到其他变型而不会脱离本公开的精神或范围。由此，本公开并非旨在被限定于本文中所描述的示例和设计，而是应被授予与本文中所公开的原理和新颖性特征相一致的最广范围。

Claims (25)

1.一种用于制造半导体器件的方法，包括：
以第一热预算处理第一材料的第一基板以制造被所述第一基板上的绝缘体层包围的p型器件，其中所述p型器件形成在所述第一基板上或中；
在所述第一基板的所述绝缘体层上制造界面层以将所述p型器件与后续处理的器件电隔离；
将第二材料的第二基板直接耦合到所述第一基板上的所述界面层；以及
以小于所述第一热预算的第二热预算处理所述第二基板以制造n型器件，其中所述p型器件和所述n型器件协作以形成互补器件，所述第二基板包括所述n型器件，其中所述n型器件形成在所述第二基板上或中。
2.如权利要求1所述的方法，其特征在于，所述第一基板是硅基板。
3.如权利要求1所述的方法，其特征在于，所述第一热预算大于1000摄氏度。
4.如权利要求1所述的方法，其特征在于，以所述第二热预算处理所述第二基板基本保持了所述p型器件的性能。
5.如权利要求1所述的方法，其特征在于，所述第二基板是III-V族基板。
6.如权利要求1所述的方法，其特征在于，所述第二热预算小于700摄氏度。
7.如权利要求1所述的方法，其特征在于，进一步包括使用穿过所述绝缘体层的互连电耦合所述第一基板的所述p型器件和所述第二基板的所述n型器件，其中所述第二基板在所述第一基板上。
8.如权利要求1所述的方法，其特征在于，所述半导体器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统(PCS)单元、便携式数据单元、和/或位置固定的数据单元中。
9.一种用于制造半导体器件的方法，包括：
以第一热预算处理第一材料的第一基板以制造被所述第一基板上的绝缘体层包围的p型器件的步骤，其中所述p型器件形成在所述第一基板上或中；
在所述第一基板的所述绝缘体层上制造界面层以将所述p型器件与后续处理的器件电隔离的步骤；
将包括第二材料的第二基板直接耦合到所述第一基板上的所述界面层的步骤；以及
以低于所述第一热预算的第二热预算处理所述第二基板以制造n型器件的步骤，其中所述p型器件和所述n型器件协作以形成互补器件，所述第二基板包括所述n型器件，其中所述n型器件形成在所述第二基板上或中。
10.如权利要求9所述的方法，其特征在于，所述第一基板是硅基板。
11.如权利要求9所述的方法，其特征在于，所述第一热预算大于1000摄氏度。
12.如权利要求9所述的方法，其特征在于，以所述第二热预算处理所述第二基板的步骤基本保持了所述p型器件的性能。
13.如权利要求9所述的方法，其特征在于，所述第二基板是III-V族基板。
14.如权利要求9所述的方法，其特征在于，所述第二热预算小于700摄氏度。
15.如权利要求9所述的方法，其特征在于，进一步包括使用穿过所述绝缘体层的互连电耦合所述第一基板的所述p型器件和所述第二基板的所述n型器件的步骤，其中所述第二基板在所述第一基板上。
16.如权利要求9所述的方法，其特征在于，所述半导体器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统(PCS)单元、便携式数据单元、和/或位置固定的数据单元中。
17.一种半导体器件，包括：
具有第一热预算的第一材料的第一基板，所述第一基板包括被所述第一基板上的绝缘体层包围p型器件，其中所述p型器件形成在所述第一基板上或中；以及
所述第一基板的所述绝缘体层上的界面层，所述界面层被安排成将所述p型器件与后续处理的器件电隔离；
直接耦合到所述第一基板上的所述界面层的具有第二热预算的第二材料的第二基板，所述第二基板包括n型器件，其中所述n型器件形成在所述第二基板上或中；以及
穿过所述绝缘体层电耦合所述第一基板的所述p型器件和所述第二基板的所述n型器件的互连，其中所述p型器件和所述n型器件协作以形成互补器件。
18.如权利要求17所述的半导体器件，其特征在于，所述第一基板是硅基板，且所述第二基板是III-V族基板。
19.如权利要求17所述的半导体器件，特征在于，所述第一热预算大于1000摄氏度，以及所述第二热预算小于700摄氏度。
20.如权利要求17所述的半导体器件，其特征在于，所述半导体器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统(PCS)单元、便携式数据单元、和/或位置固定的数据单元中。
21.一种半导体器件，包括：
用于在具有第一热预算的第一材料的第一基板中传导第一载荷子类型且被所述第一基板上的绝缘体层包围的第一装置，其中所述第一装置形成在所述第一基板上或中；
在所述第一装置的所述第一基板的所述绝缘体层上的用于将所述第一装置与后续处理的器件电隔离的装置；以及
用于在直接耦合到所述第一基板上的所述用于将所述第一装置与后续处理的器件电隔离的装置的具有第二热预算的第二材料的第二基板中传导第二载荷子类型的第二装置，其中所述第一装置和所述第二装置协作以形成互补器件，所述第二基板包括所述第二装置，其中所述第二装置形成在所述第二基板上或中。
22.如权利要求21所述的半导体器件，其特征在于，所述第二基板在所述第一基板上，并且所述第一基板的第一装置使用穿过所述绝缘体层的互连电耦合到所述第二基板的第二装置。
23.如权利要求21所述的半导体器件，其特征在于，所述第一基板是硅基板，且所述第二基板是III-V族基板。
24.如权利要求21所述的半导体器件，特征在于，所述第一热预算大于1000摄氏度，以及所述第二热预算小于700摄氏度。
25.如权利要求21所述的半导体器件，其特征在于，所述半导体器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统(PCS)单元、便携式数据单元、和/或位置固定的数据单元中。
CN201480058901.4A 2013-10-28 2014-09-03 到晶片中的异构沟道材料集成 Expired - Fee Related CN105684141B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/064,944 2013-10-28
US14/064,944 US9257407B2 (en) 2013-10-28 2013-10-28 Heterogeneous channel material integration into wafer
PCT/US2014/053897 WO2015065582A1 (en) 2013-10-28 2014-09-03 Heterogeneous channel material integration into wafer

Publications (2)

Publication Number Publication Date
CN105684141A CN105684141A (zh) 2016-06-15
CN105684141B true CN105684141B (zh) 2020-09-11

Family

ID=51541366

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480058901.4A Expired - Fee Related CN105684141B (zh) 2013-10-28 2014-09-03 到晶片中的异构沟道材料集成

Country Status (5)

Country Link
US (1) US9257407B2 (zh)
EP (1) EP3063788B1 (zh)
JP (1) JP2016541110A (zh)
CN (1) CN105684141B (zh)
WO (1) WO2015065582A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343369B2 (en) * 2014-05-19 2016-05-17 Qualcomm Incorporated Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
US9954033B2 (en) * 2015-12-11 2018-04-24 Flexterra, Inc. Bonding P-type and N-type sheets to form complementary circuits

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1297258A (zh) * 1999-11-23 2001-05-30 朗迅科技公司 用作电源开关的碳化硅n沟场效应晶体管及其制造方法
EP2518767A2 (en) * 2011-04-29 2012-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20130082235A1 (en) * 2011-10-04 2013-04-04 Qualcomm Incorporated Monolithic 3-d integration using graphene

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176688A (ja) * 1993-12-20 1995-07-14 Mitsubishi Electric Corp 半導体集積回路
WO2001006546A2 (en) 1999-07-16 2001-01-25 Massachusetts Institute Of Technology Silicon on iii-v semiconductor bonding for monolithic optoelectronic integration
US6882010B2 (en) * 2002-10-03 2005-04-19 Micron Technology, Inc. High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
JP2005191235A (ja) * 2003-12-25 2005-07-14 Seiko Epson Corp 半導体装置および半導体装置の製造方法
FR2896620B1 (fr) * 2006-01-23 2008-05-30 Commissariat Energie Atomique Circuit integre tridimensionnel de type c-mos et procede de fabrication
US7875952B1 (en) 2006-09-19 2011-01-25 Hrl Laboratories, Llc Method of transistor level heterogeneous integration and system
WO2008053042A1 (en) * 2006-11-02 2008-05-08 Interuniversitair Microelektronica Centrum Removal of impurities from semiconductor device layers
KR101300820B1 (ko) 2007-07-24 2013-08-26 삼성전자주식회사 반도체 집적 회로 장치 및 그 제조 방법
JP2009158528A (ja) 2007-12-25 2009-07-16 Sharp Corp 半導体装置
FR2933232B1 (fr) 2008-06-30 2010-10-29 Soitec Silicon On Insulator Procede de fabrication de dispositifs semi-conducteurs,et structure semi-conductrice obtenue par un tel procede
JP5617835B2 (ja) 2009-02-24 2014-11-05 日本電気株式会社 半導体装置およびその製造方法
JP2011108860A (ja) * 2009-11-18 2011-06-02 Panasonic Corp 固体撮像素子の製造方法
JP6019599B2 (ja) * 2011-03-31 2016-11-02 ソニー株式会社 半導体装置、および、その製造方法
US8912055B2 (en) 2011-05-03 2014-12-16 Imec Method for manufacturing a hybrid MOSFET device and hybrid MOSFET obtainable thereby
TWI550828B (zh) 2011-06-10 2016-09-21 住友化學股份有限公司 半導體裝置、半導體基板、半導體基板之製造方法及半導體裝置之製造方法
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1297258A (zh) * 1999-11-23 2001-05-30 朗迅科技公司 用作电源开关的碳化硅n沟场效应晶体管及其制造方法
EP2518767A2 (en) * 2011-04-29 2012-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20130082235A1 (en) * 2011-10-04 2013-04-04 Qualcomm Incorporated Monolithic 3-d integration using graphene

Also Published As

Publication number Publication date
US20150115473A1 (en) 2015-04-30
EP3063788A1 (en) 2016-09-07
WO2015065582A1 (en) 2015-05-07
JP2016541110A (ja) 2016-12-28
EP3063788B1 (en) 2020-10-21
US9257407B2 (en) 2016-02-09
CN105684141A (zh) 2016-06-15

Similar Documents

Publication Publication Date Title
US10134837B1 (en) Porous silicon post processing
US10420171B2 (en) Semiconductor devices on two sides of an isolation layer
US10083963B2 (en) Logic circuit block layouts with dual-side processing
US10784348B2 (en) Porous semiconductor handle substrate
JP6396624B1 (ja) 背面結合型対称バラクタ構造
WO2016022212A1 (en) Fin field-effect transistor static random access memory devices with p-channel metal-oxide-semiconductor pass gate transistors
US20160181161A1 (en) Sub-fin device isolation
CN105684141B (zh) 到晶片中的异构沟道材料集成
US10748934B2 (en) Silicon on insulator with multiple semiconductor thicknesses using layer transfer
US9966426B2 (en) Augmented capacitor structure for high quality (Q)-factor radio frequency (RF) applications
US20160225881A1 (en) Silicon germanium finfet formation
US10700012B2 (en) Porous silicon dicing
US20190386121A1 (en) Radio frequency silicon-on-insulator integrated heterojunction bipolar transistor
US20190027576A1 (en) Composite channel metal-oxide-semiconductor field effect transistor (mosfet)
US9837302B1 (en) Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer
WO2018004693A1 (en) Substrates for integrated circuits
CN112368844A (zh) 双极结型晶体管及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200911

Termination date: 20210903

CF01 Termination of patent right due to non-payment of annual fee