CN105679711A - 射频工艺中减小带电感器件的芯片面积的方法及应用 - Google Patents

射频工艺中减小带电感器件的芯片面积的方法及应用 Download PDF

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CN105679711A
CN105679711A CN201610024778.5A CN201610024778A CN105679711A CN 105679711 A CN105679711 A CN 105679711A CN 201610024778 A CN201610024778 A CN 201610024778A CN 105679711 A CN105679711 A CN 105679711A
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inductance
layer
indid
chip
radio frequency
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陈曦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种射频工艺中减小带电感器件的芯片面积的方法，在客户为降低芯片面积减小电感和周边电路的距离时，将INDID(电感标定层)层缩小，并将缩小后的INDID层设置在电感器件内部，使得满足INDID层加工艺设计规则要求的值后，电感离周边电路的距离等同客户设计值。本发明能够有效减小射频工艺中带电感器件的芯片面积，且不会造成漏电。

Description

射频工艺中减小带电感器件的芯片面积的方法及应用
技术领域
本发明涉及半导体集成电路领域，特别是涉及一种射频工艺中减小带电感器件的芯片面积的方法及应用。
背景技术
电感是射频器件，用于射频工艺如RFCMOS(射频互补金属氧化半导体)和SiGeBiCMOS(硅锗双极-互补金属氧化物半导体)工艺中。
在带电感的芯片中，为保证其Q值并防止信号串扰，电感和其它电路距离较远；例如定义为INDID(电感标定层)+45μm，这样电感器件周围45μm范围内不会摆放其他器件。
Pwell(P阱)是通过运算生成的层次，除了用作NMOS(N型金属-氧化物-半导体)器件沟道外，还是芯片接地和器件间隔离的层次，其离电感的距离也是电感要求的最小距离决定的。
这条规则导致带有电感的芯片尺寸较大，从而芯片面积也增加较多。
很多客户的芯片对电感的Q值和信号串扰的要求不是很高，但为降低芯片费用而需要更小面积，会将45μm更改为较小的值；但由于Pwell还是会按照逻辑运算产生，从而在客户的很大部分电路内没有生成，这会造成电感周边电路没有Pwell的隔离而造成漏电问题。
发明内容
本发明要解决的技术问题是提供一种射频工艺中减小带电感器件的芯片面积的方法，能够有效减小射频工艺中带电感器件的芯片面积，且不会造成漏电。
为解决上述技术问题，本发明的射频工艺中减小带电感器件的芯片面积的方法是采用如下技术方案实现的：
在客户为降低芯片面积减小电感和周边电路的距离时，将INDID(电感标定层)层缩小，并将缩小后的INDID层设置在电感器件内部，使得满足INDID层加工艺设计规则要求的值后，电感离周边电路的距离等同客户设计值。
本发明是射频工艺如RFCMOS和SiGeBiCMOS工艺中，减小带电感器件面积的方法，采用本发明的方法产生的Pwell，可以包住电感周边的电路，不会产生由于客户为了降低芯片面积而人为修改规则造成的漏电问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1是现有的减小带电感器件的芯片面积的方法示意图；
图2是所述射频工艺中减小带电感器件的芯片面积的方法示意图。
具体实施方式
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述。
所述射频工艺中减小带电感器件的芯片面积的方法，在下面的实施例中是这样实现的：
如果客户为缩小芯片的需要降低电感和周边电路的距离，则在电路设计中将电感标定层(INDID)作相应的指向电感器件内部的缩小，例如客户将要求的45μm缩小到25μm，则INDID层向电感内部缩小20μm(45-25)，这样在INDID+45μm之后，产生的Pwell层和电路距离电感的值相同，等于客户设计值。
采用上述方法，在不用修改逻辑运算(EB)的情况下，就可以满足客户对芯片面积与电感Q值的平衡；同时由于不同客户，同一客户的不同芯片，甚至同一芯片的不同区域的电路，电感和其它电路的距离设计不同，用上述方法可以简单地解决。
参见图1，其中，1表示INDID层，通常是包在电感器件外面；6是指金属层1-4(即第1金属层至第4金属层)，4是指第五层金属，5是指顶层金属，2和3是指电感的两个端口。
再参见图2，采用所述射频工艺中减小带电感器件的芯片面积的方法，将INDID层缩小，并将缩小后的INDID层移入电感器件内部(图2中其中间的方框部分表示INDID层)，使得其它器件离电感的距离可以满足客户设计的要求。
以上通过具体实施方式对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (2)

1.一种射频工艺中减小带电感器件的芯片面积的方法，其特征在于：在客户为降低芯片面积减小电感和周边电路的距离时，将INDID层缩小，并将缩小后的INDID层设置在电感器件内部，使得满足INDID层加工艺设计规则要求的值后，电感离周边电路的距离等同客户设计值。
2.权利要求1所述的方法在包括RFCMOS和SiGeBiCMOS在内的射频器件中的应用。
CN201610024778.5A 2016-01-15 2016-01-15 射频工艺中减小带电感器件的芯片面积的方法及应用 Pending CN105679711A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020163375A1 (en) * 2001-05-03 2002-11-07 Wu John C. On-chip integrated mixer with balun circuit and method of making the same
CN101447276A (zh) * 2007-09-28 2009-06-03 富士通媒体部品株式会社 电子器件
CN201303050Y (zh) * 2008-10-16 2009-09-02 上海集成电路研发中心有限公司 应用于rfid芯片的集成天线
CN103187926A (zh) * 2011-12-28 2013-07-03 国民技术股份有限公司 Lc-vco芯片及其版图布局方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020163375A1 (en) * 2001-05-03 2002-11-07 Wu John C. On-chip integrated mixer with balun circuit and method of making the same
CN101447276A (zh) * 2007-09-28 2009-06-03 富士通媒体部品株式会社 电子器件
CN201303050Y (zh) * 2008-10-16 2009-09-02 上海集成电路研发中心有限公司 应用于rfid芯片的集成天线
CN103187926A (zh) * 2011-12-28 2013-07-03 国民技术股份有限公司 Lc-vco芯片及其版图布局方法

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