CN105634487A

CN105634487A - Device for implementing parallel DDS with wide coverage

Info

Publication number: CN105634487A
Application number: CN201410594647.1A
Authority: CN
Inventors: 陆骁璐; 吕华平
Original assignee: JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
Current assignee: JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
Priority date: 2014-10-29
Filing date: 2014-10-29
Publication date: 2016-06-01

Abstract

The invention belongs to the technical field of frequency synthesis and relates to a device for implementing a parallel DDS with wide coverage. The device utilizes parallel internal structure and comprises two phase accumulators, two sine look-up table ROMs, a selector, a DAC, and a LPF module. A frequency control word is simultaneously input into the phase accumulator A and the phase accumulator B. The outputs of the two phase accumulators are output to the sine look-up table ROMs to look up tables separately. Binary amplitude sequences output by the two sine look-up table ROMs are output to the one-out-of-two data selector and then are output in an interlaced way under the control of a clock. The operating reference clock frequency of the phase accumulators, the sine look-up table ROMs, and the selector is fc. Two signals are combined by the selector and then are output to the DAC. The reference clock frequency of the DAC is 2fc. The parallel DDS may effectively expand the output bandwidth of the DDS.

Description

The wide parallel fo DDS covered realizes device

Technical field

The invention belongs to frequency synthesis technique field, what particularly relate to a kind of wide parallel fo DDS covered realizes device.

Background technology

Compared with other frequency synthesis modes, the output bandwidth of DDS is narrower, the output frequency upper limit is clock frequency the 50% of DDS in theory, but frequency is more high spuious more many, in practical application, general output frequency is the 40% of clock frequency, and the Digitized Structure of DDS makes its clock frequency can not be too high, therefore, the relative bandwidth of DDS is very limited.

When DDS needs to export wider frequency bandwidth, if by conventional DDS+PLL scheme, the output phaselocked loop of DDS is carried out frequency multiplication, so can improve output frequency, but the frequency resolution of whole frequency synthesis system can reduce, and phaselocked loop outputting stable frequency needs certain locking time, thus makes system lose the characteristic of frequency agility.

Summary of the invention

The technique effect of the present invention can overcome drawbacks described above, it is provided that a kind of wide parallel fo DDS covered realizes device, and it achieves the wide covering of frequency.

For achieving the above object, the present invention adopts the following technical scheme that it adopts internal structure parallel mode, including two phase accumulators, two sine lookup table ROM, selector, DAC, LPF module, frequency control word is sent into A simultaneously, in the phase accumulator of B two-way, the output of two-way phase accumulator is re-fed into sine lookup table ROM and tables look-up respectively, then after the binary amplitude sequence of two sine lookup table ROM outputs being sent into alternative data selector, under clock control, timesharing is staggered exports, accumulator, the reference clock frequency of sine lookup table and data selector work is fc, two paths of signals is combined into a road after selector and delivers to digital to analog converter DAC, the reference clock frequency of DAC is then 2fc.

The another way of the present invention is: adopt overall structure parallel mode, including MCU, multichannel DDS parallel output, BPF module, close way switch, this synthesis mode is respectively synthesized being originally divided into n section with the frequency bandwidth �� f of a road synthesis, all DDS use same reference clock, and being uniformly controlled by a MCU, the output of every road DDS exports then through conjunction way switch after band-pass filter.

Parallel DDS just becomes a kind of well selection. Parallel DDS can be divided into two kinds of forms, and a kind of is the parallel of DDS internal structure aspect, and one is that two DDS are integrally-built parallel, and they can expand the output bandwidth of DDS effectively.

Accompanying drawing explanation

Fig. 1 is the parallel DDS fundamental diagram of internal structure of the present invention;

Fig. 2 is the parallel DDS structural representation of overall structure of the present invention.

Detailed description of the invention

The technical problem to be solved be a kind of wide parallel fo DDS covered proposed realize device.

Internal structure carries out the DDS structure of parallel connection as shown in Figure 1.

First and common DDS structure the difference is that, this parallel DDS structure has two phase accumulators and two sine lookup table ROM, frequency control word is sent in the phase accumulator of A, B two-way simultaneously, the output of two-way phase accumulator is re-fed into sine lookup table ROM and tables look-up respectively, then after the binary amplitude sequence of two sine lookup table ROM outputs being sent into alternative data selector, under clock control, timesharing is staggered exports, and the reference clock frequency of this part of accumulator, sine lookup table and data selector work is fc. Two paths of signals is combined into a road after selector and delivers to the final output frequency that the reference clock frequency of digital to analog converter DAC, DAC is then 2fc, such DDS and be then doubled.

The advantage of this parallel way is the output frequency bandwidth that improve DDS, reaches original twice, but to spurious reduction not significantly effect.

The second, when requiring DDS output bandwidth wider, the spuious index of DDS will worsen more. The low-order harmonic that causes when DAC is non-linear is spuious when dropping in output band, and spuious will being difficult to of system is filtered out. On the contrary, if output band is very narrow, then various spuious to be mixed into probability therein general just less, therefore spurious performance is generally better. So, the spurious performance of DDS and output bandwidth are the factors of two mutual restrictions. Along with exporting the broadening of signal bandwidth, the spuious of DDS will worsen with performance of making an uproar mutually, thus systematic function can be made to decline. If adopting the form of DDS in parallel, every branch road individually exports a band frequency, then filters respectively, exports finally by closing road process, such that it is able to make broadband signal become narrow band signal, is so obtained with the highly purified broadband signal output of high speed.

The structure chart of the DDS of overall structure parallel fo is as shown in Figure 2.

In figure, parallel DDS adopts multichannel DDS parallel output, this synthesis mode is respectively synthesized being originally divided into n section with the frequency bandwidth �� f of a road synthesis, thus need n road DDS, all DDS use same reference clock, and being uniformly controlled by a MCU, the output of every road DDS exports then through conjunction way switch after band-pass filter. the output bandwidth of each road DDS can divide according to actual needs, if by point outputs such as �� f, the frequency bandwidth of every road DDS output is �� f/n, this reduces the output bandwidth of DDS, due to output band very narrow time various spuious to be mixed into probability therein relatively small, spuious meeting in these time-frequency band all reduces accordingly, and the output of each road DDS both passes through a band-pass filter, further suppress spuious, eventually pass the output of spuious relatively single DDS synthesis in total output band �� f of synthesizer synthesis also can be improved preferably, so both obtain frequency spectrum and export signal preferably, remain again the advantages such as the original frequency agility of DDS.

Claims

1. the parallel fo DDS of a wide covering realize device, it is characterized in that, it adopts internal structure parallel mode, including two phase accumulators, two sine lookup table ROM, selector, DAC, LPF module, frequency control word is sent into A simultaneously, in the phase accumulator of B two-way, the output of two-way phase accumulator is re-fed into sine lookup table ROM and tables look-up respectively, then after the binary amplitude sequence of two sine lookup table ROM outputs being sent into alternative data selector, under clock control, timesharing is staggered exports, accumulator, the reference clock frequency of sine lookup table and data selector work is fc, two paths of signals is combined into a road after selector and delivers to digital to analog converter DAC, the reference clock frequency of DAC is then 2fc.

2. the parallel fo DDS of a wide covering realize device, it is characterized in that, it adopts overall structure parallel mode, including MCU, multichannel DDS parallel output, BPF module, close way switch, this synthesis mode is respectively synthesized being originally divided into n section with the frequency bandwidth �� f of a road synthesis, all DDS use same reference clock, and are uniformly controlled by a MCU, and the output of every road DDS exports then through conjunction way switch after band-pass filter.