CN202818272U - Rubidium clock frequency conversion circuit without frequency synthesizer - Google Patents
Rubidium clock frequency conversion circuit without frequency synthesizer Download PDFInfo
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- CN202818272U CN202818272U CN 201220366517 CN201220366517U CN202818272U CN 202818272 U CN202818272 U CN 202818272U CN 201220366517 CN201220366517 CN 201220366517 CN 201220366517 U CN201220366517 U CN 201220366517U CN 202818272 U CN202818272 U CN 202818272U
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Abstract
The utility model provides a rubidium clock frequency conversion circuit without a frequency synthesizer. The rubidium clock frequency conversion circuit mainly comprises a non-integer voltage-controlled crystal oscillator, a CPLD-based frequency division and DDS circuit, a phase modulation circuit, a servo amplification circuit, a synchronous phase demodulation circuit and a 1PPS signal processor. Output of the non-integer voltage-controlled crystal oscillator is generated into a 144Hz triangular wave signal through the frequency division and DDS synthesis circuit, the signal being used for phase modulation of the output of the voltage-controlled crystal oscillator; through a x5 frequency multiplier and x72 microwave frequency multiplication, the signal performs quantum frequency demodulation processing via a physical system together with a microwave signal generated by rubidium atoms under stimulated transition; and the signal is converted to an electric error signal through a photocell, correcting voltage is obtained through 144Hz synchronous phase demodulation and a low pass filter, and the non-integer voltage-controlled crystal oscillator is controlled to be in a locked state. The rubidium clock frequency conversion circuit is simple in structure, convenient for debugging and beneficial for improvement of integration level and miniaturization of rubidium atomic frequency standard and enjoys promising application prospect.
Description
Technical field
The utility model relates to the Technology of Atomic Frequency Standards field, and particularly a kind of by improved rubidium clock frequency-conversion circuit without Frequency Synthesizer, this circuit is applicable to make small Rb atom frequency marking.
Background technology
The advantages such as Rb atom frequency marking has that volume is little, power consumption, environmental suitability are strong, high frequency stability and low drift rate.Although frequency stability and drift rate index are not as good as caesium, Hydrogen Atom Frequency Standard, it has simple in structure, and characteristics with low cost are still the atomic frequency standard that is most widely used at present.Its development trend is high-performance and miniaturization.In the Rb atom frequency marking, physical system provides a frequency stabilization, the narrower atomic resonance Absorption Line of live width.The hyperfine levels transition frequency signal has high frequency accuracy, but it is output as the non-integer microwave frequency, and power output is minimum, thereby does not possess practicality.
Traditional rubidium clock frequency translation servo circuit system transforms to 90MHz to the output frequency of 10MHz VCXO, the 5.3125MHz fractional frequency signal superposition that produces with frequency synthesizer subsequently is sent to microwave cavity and carries out 76 step frequencys multiplication and simultaneously mixing, thereby obtains the microwave frequency signal that determined by the rubidium atomic transition:
Because the mode of proportion synthesizer mixing in microwave cavity increases the complexity of frequency-conversion circuit.The side frequency component that has simultaneously 5.3125MHz and harmonic wave thereof in the chamber makes spuious increase and has affected the performance index of atomic frequency standard.
Summary of the invention
Technical problem to be solved in the utility model is: a kind of improved rubidium clock frequency-conversion circuit without Frequency Synthesizer is provided, in the situation of proportion synthesizer not, the stability that realizes atomic frequency standard shifts, and is transformed into the integer of standard and the high frequency stabilization mark signal output of power practicality with being not easy to practical rubidium atom microwave frequency signal.
The technical scheme that its technical problem of solving the utility model adopts is: mainly by
MHz non-integer VCXO,
The frequency division of frequency multiplier circuit, complex programmable device (CPLD) design and combiner circuit, DDS triangular wave combiner circuit, phase modulation circuit, servo amplifier, synchronous phase discriminator, 1PPS signal processor form.Wherein: the output of non-integer VCXO produces the 144Hz triangular signal through frequency division and combiner circuit, and this signal carries out phase modulation to the output of non-integer VCXO; Warp again
Frequency multiplier and
Microwave multiple-frequency carries out frequency discrimination with the microwave signal that the transition of rubidium atom-exciting produces to physical system to 6.8346875GHz; Then be converted to the error signal of telecommunication by photocell, obtain correction voltage by the synchronous phase demodulation of 144Hz and low pass filter, control non-integer VCXO is to lock-out state.
Described
MHz non-integer VCXO directly obtains the microwave excitation signal through frequency multiplier chain, makes frequency discrimination by physical system and processes, and need not frequency synthesizer and carries out the frequency adjustment.
Described frequency divider divide ratio by the CPLD design is 131072, and the output lock-out pulse is 144Hz.Synthetic 144Hz triangular signal, signal to the output of non-integer VCXO carries out indirect frequency modulation, the combiner circuit of described CPLD design is the two-way Direct Digital Frequency Synthesizers of CPLD design, formed by FREQUENCY CONTROL word register, phase accumulator, sinusoidal waveform question blank, digital to analog converter etc., one the tunnel is fixing 10MHz frequency output, and another road can arrange applicable frequency output.
Described 1PPS treatment circuit produces the output of 1PPS signal, or is subjected to 1PPS signal input control, makes the non-integer VCXO be synchronized with standard 1PPS signal.
The utility model solves the technical scheme that its technical problem adopts, and compares with traditional Rb atom frequency marking frequency-conversion circuit to have following main advantage:
1. have the adjustable frequency resolution of liaison, because the direct voltage-controlled non-integer crystal oscillator of correction voltage, so can obtain mantissa's output frequency of continuous variable.After the frequency multiplier chain frequency multiplication, the resolution of output frequency can be infinitely narrow in theory.
2. the microwave signal spectral purity of rubidium frequency standard microwave cavity is high.After radio frequency frequency multiplier frequency multiplication, the signal that is input to the snap-off diode microwave cavity is
The single-frequency of MHz, and without the frequency synthesizer component.Effectively reduce phase noise and spuious component, also effectively reduced spuious component to the impact of frequency marking.
3. hardware circuit is simplified, and is easy to the miniaturization of Rb atom frequency marking.Because all digital circuits comprise that frequency dividing circuit and triangular wave combiner circuit, Direct Digital Frequency Synthesizers and 1PPS treatment circuit are all selected with CPLD and design, saved again frequency synthesizer and the additive mixing unit in the frequency-conversion circuit, optimized and simplified hardware circuit.
4. the applicable output frequency of Rb atom frequency marking obtains conveniently, because adopt the two DDS technology by complex programmable device CPLD design, the one tunnel is fixing 10MHz frequency in the two-way output.The output frequency of another road DDS can in applicable frequency range, arrange and obtain output frequency.
The advantages such as in a word, the utlity model has system optimization, circuit structure is simple, and volume is little, and low in energy consumption and debugging is convenient, the integrated level and the miniaturization that are conducive to improve Rb atom frequency marking have good application prospect.
Description of drawings
Fig. 1 is that the utility model is without the structured flowchart of the rubidium clock frequency-conversion circuit of Frequency Synthesizer.
Fig. 2 is the structured flowchart of servo control circuit among Fig. 1.
Fig. 3 is the digital-to-analogue conversion figure principle block diagram that the utility model is used for DDS or triangular wave.
Fig. 4 is the digital system theory diagram of CPLD design among Fig. 3.
Embodiment
The utility model is described in further detail below in conjunction with embodiment and accompanying drawing.
The utility model discloses a kind of improved rubidium clock frequency-conversion circuit without Frequency Synthesizer, the resonance frequency of the non-integer VCXO that it adopts is
MHz, the resulting error signal of correction information that physical system is obtained is removed servo non-integer VCXO, can be offset because of the sum frequency that the various factors system produces by effective compensation, realizes the closed loop locking of complete machine.Province is except the additive mixing unit of the frequency synthesizer in the control loop and frequency multiplier and frequency synthesizer, stopped Frequency Synthesizer phase noise and spuious impact.
The utility model is described in further detail below in conjunction with embodiment and accompanying drawing, but be not limited to following described or illustrated structure and implementation detail.
The rubidium clock frequency-conversion circuit without Frequency Synthesizer that the utility model provides, as depicted in figs. 1 and 2.Because physical system can equivalence be a frequency discriminator, in the described frequency-conversion circuit
The output signal of the non-integer VCXO of MHz through indirect frequency modulation,
Behind frequency multiplication and the microwave multiple-frequency, obtain the microwave signal of oneself modulation of 6.8346875GHz, physical system
The microwave excitation signal frequency discrimination of atomic ground state hyperfine transition frequency signal after to non-integer VCXO frequency multiplication if microwave signal frequency greater than the core frequency, produces negative correction voltage behind phase demodulation, reduces the frequency of VCXO; If otherwise exciting signal frequency produces positive correction voltage less than the core frequency behind phase demodulation, the frequency of VCXO is risen; If exciting signal frequency equals the core frequency, then be output as the signal of the twice of modulating frequency, do not produce correction voltage behind phase demodulation, this moment, the frequency of non-integer VCXO was constant, realization is passed through the Rb atom frequency marking signal of DDS stable output again to the locking of non-integer VCXO.
Because VCXO has certain voltage-controlled scope, the voltage of therefore rectifying a deviation can make the frequency of microwave signal be within the scope of Atomic absorption live width fully, thereby can realize the reliable closed loop locking of complete machine.
The rubidium clock servo control circuit without Frequency Synthesizer that the utility model provides, concrete structure as shown in Figure 2, mainly by the non-integer VCXO, remove
(148322Hz), remove
(144Hz) frequency divider and the triangular wave combiner circuit, phase modulation circuit that comprise D/A,
Frequency multiplier and microwave multiple-frequency, servo amplifier, the synchronous phase discriminator of 144Hz and low pass filter, 288Hz lock-in detection form with indication, wherein: as the output of the non-integer VCXO in the initialize signal source of Rb atom frequency marking system through removing
, remove
Produce 288Hz and
Frequency divider produces the square-wave signal of 144Hz, respectively as the synchronous phase discriminating pulse of 144Hz and 288Hz lock-in detection and marker pulse signal.Remove
Frequency divider is exported VCXO by phase modulation circuit after the D/A conversion forms triangular signal again
The signal of MHz carries out phase modulation, is actually indirect frequency modulation.Signal warp after the modulated
Frequency multiplier obtains
The radiofrequency signal of MHz, again warp
Microwave multiple-frequency is to 6.8346875GHz, and it is by the microwave signal frequency discrimination of the high steady 6.8346875GHz of atom-exciting transition generation.The frequency discrimination optical error signal is converted to the error signal of telecommunication by photocell, after the servo amplifier amplifies, obtain correction voltage by the synchronous phase discriminator of 144Hz, low pass filter again, control the non-integer VCXO to lock-out state, and provide lock indication signal by the square-wave signal control locking indicating circuit of 288Hz.
Described error signal preamplifier selects high-precision low-drift integrated operational amplifier (such as AD8628 etc.), low noise field effect transistor etc., non-integer VCXO among Fig. 1 and Fig. 2
MHz output is through removing
, remove
Obtain the rectangular pulse signal of 144Hz and 288Hz,
In
Export to the D/A that is made of CPLD and external resistor array, by its synthetic triangular wave, digital-to-analogue conversion figure principle block diagram as shown in Figure 3.And the switch phase discriminator that locking phase is picked up in the survey selects the high accuracy break-make near the high-speed analog switch (such as MAX392 etc.) of perfect condition.
Provided as shown in Figure 3 the structure chart by one 10 DAC Bian Change circuit of CPLD design, the CPLD design includes fast data buffer register and the Wei Qie Change switch of 10 parallel-by-bits.External high precision reference voltage source and low error R-2R resistor network are subjected to the control of Wei Qie Change switch, its output is exported behind high speed, low noise, rail-to-rail output fortune grate amplifier (such as ADA4897-1) Hyblid Buffer Amplifier, becomes sinusoidal ladder frequency signal to export the frequency data Bian Change of sinusoidal waveform question blank.When as the triangular wave combiner circuit, remove
Consisted of by forward-backward counter,
In
The parallel high-speed data that is made of CPLD buffer register is given in output, and count pulse Bian Change is become the output of triangle staircase waveform frequency signal.
The utility model adopts CPLD design Direct Digital Frequency Synthesizers (DDS), for conveniently choosing applicable frequency, adopt two DDS Direct Digitals, the non-integer VCXO output frequency of system lock can be transformed to high accuracy Rb atom frequency marking signal.Fig. 4 is the digital system theory diagram of CPLD design in the frequency-conversion circuit, and it comprises two DDS, removes
, remove
, triangular wave digital-to-analogue conversion, 1PPS treatment circuit etc., the output signal warp of non-integer VCXO
Frequency multiplier obtains
The radiofrequency signal of MHz is exported to DDS as the high accuracy reference source, and again by DDS synthetic standards rubidium frequency standard signal output, CPLD can be other companies such as the MAX II series of ALTERA company or XILINX.
As shown in Figure 4, the direct digital synthesiser (DDS) of CPLD design comprises the parts such as FREQUENCY CONTROL word register, phase accumulator, sinusoidal waveform question blank, digital-to-analogue conversion and filter circuit.FREQUENCY CONTROL word register wherein, phase accumulator, sinusoidal waveform question blank, digital-to-analogue conversion part are by the CPLD design, and particularly the digital to analog converter of CPLD design has response soon, the characteristics that power consumption and cost are low.Designed data register storage frequency control data (frequency control word), have the serial/parallel data input function, and serial, parallel input come self-controller or microcomputer.This technology is two-way output with the output frequency ， Bian Change of the voltage-controlled quartz oscillator of non-integer of servo system locking.Frequency control data is inputed to phase accumulator by parallel, and the figure place of phase accumulator can be chosen according to the desired resolution of frequency synthesizer.
Known clock is
MHz if select 44 phase accumulators, then can get minimum output frequency (frequency resolution) and is
, the fine requirement of satisfying rubidium frequency standard output frequency accuracy of energy, the corresponding frequency control word of output 10MHz is
, be converted to binary system and be
The output of 10MHz can be processed through narrow-band filtering and eliminate out-of-band noise and spuious.The output frequency of selecting any suitable another road DDS can be set, and output is exported after low pass filter filtering.
Except DDS is designed by complex programmable device (CPLD), removing among Fig. 4
, remove
Parallel high-speed data buffer register among frequency divider, the D/A, high speed COMS bus exchange switch, 1PPS treatment circuit also design by CPLD.
Complex programmable device (CPLD) in the utility model adopts the MAX2 series CPLD such as ALTERA company, or the CPLD of Xilinx company, can also select FPGA.And complex programmable device (CPLD) has better flexibility.
The above-mentioned improved rubidium clock frequency-conversion circuit without Frequency Synthesizer that the utility model provides, its purposes is: be used for making small Rb atom frequency marking.
The above, it only is preferred embodiment of the present utility model, be not that structure of the present utility model is done any pro forma restriction, every foundation technical spirit of the present utility model all still belongs in the scope of the technical solution of the utility model any simple modification, equivalent variations that above embodiment does.
Claims (5)
1. rubidium clock frequency-conversion circuit without Frequency Synthesizer, it is characterized in that mainly by the non-integer VCXO,
The frequency division of frequency multiplier circuit, CPLD design and combiner circuit, phase modulation circuit, servo amplifier, synchronous phase discriminator, 1PPS signal processor form, wherein: the output of non-integer VCXO produces the 144Hz triangular signal through frequency division and combiner circuit, and this signal carries out phase modulation to the output of non-integer VCXO; Warp again
Frequency multiplier and
Microwave multiple-frequency carries out frequency discrimination with the microwave signal that the transition of rubidium atom-exciting produces to physical system to 6.8346875GHz; Then be converted to the error signal of telecommunication by photocell, obtain correction voltage by the synchronous phase demodulation of 144Hz and low pass filter, control non-integer VCXO is to lock-out state.
2. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1 is characterized in that the non-integer VCXO adopts
MHz non-integer VCXO, the microwave excitation signal that its output obtains through frequency multiplier chain is done to lock this VCXO after frequency discrimination is processed by physical system, need not frequency synthesizer and carries out the frequency adjustment.
3. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 2 is characterized in that: described
The output of MHz signal produces the 144Hz triangular signal through frequency division and the DDS combiner circuit of CPLD design, and this signal carries out phase modulation to the output of non-integer VCXO, is equivalent to indirect frequency modulation; Warp again
After the frequency multiplication, obtain
MHz delivers to microwave snap-off diode frequency multiplier circuit.
4. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1, it is characterized in that: the combiner circuit of described CPLD design is the two-way Direct Digital Frequency Synthesizers of CPLD design, formed by FREQUENCY CONTROL word register, phase accumulator, sinusoidal waveform question blank, digital to analog converter, it is two-way output that this synthesizer is Shuaied Bian Change with the Pin of the voltage-controlled quartz oscillator of non-integer output, and one the tunnel is fixing 10MHz frequency; Another road obtains applicable output frequency by arranging.
5. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1, it is characterized in that: described 1PPS signal processor is designed by CPLD, and this processor produces the output of 1PPS signal or is subjected to 1PPS signal input control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220366517 CN202818272U (en) | 2012-07-27 | 2012-07-27 | Rubidium clock frequency conversion circuit without frequency synthesizer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220366517 CN202818272U (en) | 2012-07-27 | 2012-07-27 | Rubidium clock frequency conversion circuit without frequency synthesizer |
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| Publication Number | Publication Date |
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| CN202818272U true CN202818272U (en) | 2013-03-20 |
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| CN 201220366517 Expired - Fee Related CN202818272U (en) | 2012-07-27 | 2012-07-27 | Rubidium clock frequency conversion circuit without frequency synthesizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634487A (en) * | 2014-10-29 | 2016-06-01 | 江苏绿扬电子仪器集团有限公司 | Device for implementing parallel DDS with wide coverage |
-
2012
- 2012-07-27 CN CN 201220366517 patent/CN202818272U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634487A (en) * | 2014-10-29 | 2016-06-01 | 江苏绿扬电子仪器集团有限公司 | Device for implementing parallel DDS with wide coverage |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130320 Termination date: 20150727 |
|
| EXPY | Termination of patent right or utility model |