CN104579340A

CN104579340A - Passive hydrogen clock digital servo system based on FPGA

Info

Publication number: CN104579340A
Application number: CN201510057606.3A
Authority: CN
Inventors: 柳丽
Original assignee: Shanghai Aerospace Measurement Control Communication Institute
Current assignee: Shanghai Aerospace Measurement Control Communication Institute
Priority date: 2015-02-04
Filing date: 2015-02-04
Publication date: 2015-04-29
Anticipated expiration: 2035-02-04
Also published as: CN104579340B

Abstract

The invention discloses a passive hydrogen clock digital servo system based on an FPGA. An analog-digital converter is used for transforming an error detection voltage signal into digital quantity from analogue quantity, feeding to a signal processing FPGA to compare and compute; the signal processing FPGA is used for generating a 4FSK signal and conveying into a direct digital frequency synthesizer to carry out FSK modulation; a frequency multiplier is used for multiplying an input base frequency signal and then providing to the signal processing FPGA to generate a clock signal, a proportional signal, a modulation signal, a blanking signal and a blanking phase control signal; a first digital-to-analogue converter is used for transforming a resonator frequency control signal into the analogue quantity from the digital quantity; and a second digital-to-analogue converter is used for transforming a voltage-controlled crystal frequency signal into the analogue quantity from the digital quantity.

Description

A kind of passive hydrogen clock digital servosystem based on FPGA

Technical field

The present invention relates to electronic circuit technology field, particularly a kind of passive hydrogen clock digital servosystem based on FPGA.

Background technology

Satellite atomic clock provides precise time benchmark for satellite system, and its stability performance directly determines the positioning precision of satellite navigation and location system.The Galileo system in the GPS navigation system of the U.S., Muscovite GLONASS system and Europe is all equipped with the high-performance satellite atomic clock that country separately develops voluntarily.The Beidou II satellite navigation and location system that China is developing also proposes urgent requirement to high accuracy satellite atomic clock, frequency stability, the property indices such as frequency accuracy and frequency drift of passive-type hydrogen atomic clock are all better than rubidium atomic clock, become the core frequency source device of Beidou II navigation satellite.

The passive hydrogen clock circuit servo system of Ground Application realizes based on DSP device, although DSP device processing speed is very fast, the RAM memory of its inside very easily overturns by the impact of single particle effect or damages and lost efficacy in space.The necessary tool Flouride-resistani acid phesphatase of components and parts of spaceborne passive hydrogen clock Circuits System and the ability of anti-single particle effect.

Summary of the invention

The present invention is directed to prior art above shortcomings, provide a kind of passive hydrogen clock digital servosystem based on FPGA.The present invention is achieved through the following technical solutions:

Based on a passive hydrogen clock digital servosystem of FPGA, comprising:

Analog to digital converter, in order to receive an error-detecting voltage signal and error-detecting voltage signal be converted to digital quantity by analog quantity;

Frequency multiplier, in order to receive a reference frequency and by reference frequency frequency multiplication;

Signal transacting FPGA, connection mode number converter and frequency multiplier, in order to calculate resonant cavity frequency control signal and VCXO frequency control signal according to the reference frequency be converted to after the error-detecting voltage signal of digital quantity and frequency multiplication, and produce fsk signal;

Direct Digital Synthesizer, connection signal process FPGA, in order to produce fsk modulated signal according to fsk signal;

First digital to analog converter, connection signal process FPGA, in order to be converted to analog quantity by resonant cavity frequency control signal by digital quantity;

Second digital to analog converter, connection signal process FPGA, in order to be converted to analog quantity by VCXO frequency control signal by digital quantity;

Wherein, signal transacting FPGA comprises:

Clock management module, connects frequency multiplier;

Pid control module, connects Clock management module and analog to digital converter;

4FSK generation module, connects Clock management module;

Clock management module is using the reference frequency after frequency multiplication as clock generating: the main processing clock signal of clock signal, blanking signal, AD, scaling signal and modulation signal, and pid control module calculates resonant cavity frequency control signal and VCXO frequency control signal according to the error-detecting voltage signal of clock signal, blanking signal, the main processing clock signal of AD and digital quantity; 4FSK generation module produces 4FSK signal according to clock signal, scaling signal, modulation signal and a switch controlling signal, and produces a blanking signal phase control signal, transfers to Clock management module.

Preferably, blanking signal, the main processing clock signal of AD, scaling signal and modulation signal are produced by the counter frequency division in Clock management module.

Preferably, frequency multiplier by: variable capacitance diode, snap-off diode, triode, non-linear delay line or phase-locked loop circuit form.

Preferably, signal transacting FPGA comprises: anti-fuse FPGA device, the FPGA device based on Flash or the FPGA device based on SRAM.

Preferably, the resolution figure place of analog to digital converter, the first digital to analog converter and the second digital to analog converter comprises: 8,12,14,16,24 or 32.

The comparison that the invention solves error signal produces with calculating, Control timing sequence, fsk signal generates and the problem of Time-sharing control crystal oscillator frequency and microwave cavity frequency, achieve high resolution frequency step by step modulating, analog-to-digital conversion and the beneficial effect such as digital-to-analogue conversion precision is high, circuit form is simple, reliability is high.

Accompanying drawing explanation

Shown in Fig. 1 is overall structure schematic diagram of the present invention;

Shown in Fig. 2 is the structural representation of signal transacting FPGA of the present invention.

Embodiment

Below with reference to accompanying drawing of the present invention; clear, complete description and discussion are carried out to the technical scheme in the embodiment of the present invention; obviously; as described herein is only a part of example of the present invention; it is not whole examples; based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to protection scope of the present invention.

For the ease of the understanding to the embodiment of the present invention, be further explained for specific embodiment below in conjunction with accompanying drawing, and each embodiment does not form the restriction to the embodiment of the present invention.

As shown in Figure 1, a kind of passive hydrogen clock digital servosystem based on FPGA provided by the invention, comprising:

Analog to digital converter 1, inputs to signal transacting FPGA2 after the error-detecting voltage signal of square-wave frequency modulation is converted to digital quantity by analog quantity;

Signal transacting FPGA2, with analog to digital converter 1, frequency multiplier 3, digital to analog converter (4,5) and Direct Digital Synthesizer 6(DDS, Direct Digital Synthesizer) be connected, realize the comparison of resonant cavity frequency control signal and VCXO frequency control signal and calculating thus produce control signal;

Frequency multiplier 3, is connected with signal transacting FPGA2, for giving signal transacting FPGA2 after reference frequency frequency multiplication as processing clock signal;

Digital to analog converter 4, is connected with signal transacting FPGA2, for the resonant cavity frequency control signal of digital quantity is transformed into analog output;

Digital to analog converter 5, is connected with signal transacting FPGA2, for the VCXO frequency control signal of digital quantity is transformed into analog output;

Direct Digital Synthesizer 6, is connected with signal transacting FPGA2, with the clock signal of signal transacting FPGA2 generation for operating frequency produces fsk modulated signal.

Preferably, above-mentioned frequency multiplier 3 can be variable capacitance diode, snap-off diode, triode, or the frequency multiplier of non-linear delay line composition, also can be the frequency multiplier of phase-locked loop circuit composition.

As shown in Figure 2, signal transacting FPGA comprises:

Clock management module 7, reference frequency carried out processing the signals such as rear clock signal, blanking signal, the main processing clock of AD, scaling signal, modulation signal, wherein the phase place of blanking signal can adjust according to the rising edge of blanking signal phase control signal;

Pid control module 8, be connected with Clock management module 7 with analog to digital converter 1, the digital error detectable voltage signals inputted analog to digital converter 1 according to the cycle of scaling signal compares, moving average calculates and PID calculates, and obtains resonant cavity frequency control signal and VCXO frequency control signal respectively;

4FSK generation module 9, take clock signal as work clock, unstringed by the switch controlling signal received, the cycle according to modulation signal switches between (f1, the f2) of hydrogen atom transition center frequency both sides, (f3 simultaneously in resonant cavity centre frequency both sides, f4) switch between, according to cycle of scaling signal at (f1, f2) and (f3, f4) switch between, generate 4FSK signal.

The course of work of the present invention and operation principle are described below:

Reference frequency enter to export after Clock management module 7 first makes buffered two-way clock respectively to pid control module 8 and 4FSK generation module 9 as work clock, then export a road obtain the main processing clock signal of scaling signal, modulation signal, blanking signal and AD etc. after DDS algorithm sum counter frequency division.

In sum, the present invention proposes a kind of error-detecting voltage signal realized based on FPGA extract, compare calculate with PID, Control timing sequence produces, fsk signal generates and the device of Time-sharing control crystal oscillator frequency and microwave cavity frequency.Utilize product of the present invention, when the reference frequency of input is 120MHz, the different signal of multichannel is produced by many group frequency-dividing counters after signal transacting FPGA generates 10.056MHz after frequency synthesis, between the signal of each road, the degree of regulation of phase difference is better than 1ms, because the present invention realizes based on FPGA device, can increase and decrease according to demand the signal that reference frequency exports through frequency synthesis and frequency division, the coefficient frequency dividing ratio of frequency synthesis can repeated configuration, and therefore the output signal of signal transacting FPGA module has reconfigurable characteristic.

Present invention achieves to compare and calculate the error signal of resonant cavity and VCXO thus produce control signal and control crystal oscillator resonant cavity variable capacitance diode respectively, VCXO is locked in hydrogen atom jump frequency, makes the centre frequency of resonant cavity be locked on VCXO; Realize the generation of the 4FSK signal in resonant cavity frequency and the saltus step of jump frequency both sides.

The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims

1., based on a passive hydrogen clock digital servosystem of FPGA, it is characterized in that, comprising:

Analog to digital converter, in order to receive an error-detecting voltage signal and described error-detecting voltage signal be converted to digital quantity by analog quantity;

Frequency multiplier, in order to receive a reference frequency and by described reference frequency frequency multiplication;

Signal transacting FPGA, connect described analog to digital converter and described frequency multiplier, in order to calculate resonant cavity frequency control signal and VCXO frequency control signal according to being converted to the described reference frequency after the described error-detecting voltage signal of digital quantity and frequency multiplication, and produce fsk signal;

Direct Digital Synthesizer, connects described signal transacting FPGA, in order to produce fsk modulated signal according to described fsk signal;

First digital to analog converter, connects described signal transacting FPGA, in order to described resonant cavity frequency control signal is converted to analog quantity by digital quantity;

Second digital to analog converter, connects described signal transacting FPGA, in order to described VCXO frequency control signal is converted to analog quantity by digital quantity;

Wherein, described signal transacting FPGA comprises:

Clock management module, connects described frequency multiplier;

Pid control module, connects described Clock management module and described analog to digital converter;

4FSK generation module, connects described Clock management module;

Described Clock management module is using the described reference frequency after frequency multiplication as clock generating: the main processing clock signal of clock signal, blanking signal, AD, scaling signal and modulation signal, and described pid control module calculates resonant cavity frequency control signal and VCXO frequency control signal according to the described error-detecting voltage signal of described clock signal, described blanking signal, described AD main processing clock signal and digital quantity; Described 4FSK generation module produces 4FSK signal according to described clock signal, described scaling signal, described modulation signal and a switch controlling signal, and produces a blanking signal phase control signal, transfers to described Clock management module.

2. the passive hydrogen clock digital servosystem based on FPGA according to claim 1, it is characterized in that, described blanking signal, described AD main processing clock signal, described scaling signal and described modulation signal are produced by the counter frequency division in described Clock management module.

3. the passive hydrogen clock digital servosystem based on FPGA according to claim 1, is characterized in that, described frequency multiplier by: variable capacitance diode, snap-off diode, triode, non-linear delay line or phase-locked loop circuit form.

4. the passive hydrogen clock digital servosystem based on FPGA according to claim 1, is characterized in that, described signal transacting FPGA comprises: anti-fuse FPGA device, the FPGA device based on Flash or the FPGA device based on SRAM.

5. the passive hydrogen clock digital servosystem based on FPGA according to claim 1, it is characterized in that, the resolution figure place of described analog to digital converter, described first digital to analog converter and described second digital to analog converter comprises: 8,12,14,16,24 or 32.