CN105555063A - Multiplexing method for via holes on same layer for PCB - Google Patents
Multiplexing method for via holes on same layer for PCB Download PDFInfo
- Publication number
- CN105555063A CN105555063A CN201610062003.7A CN201610062003A CN105555063A CN 105555063 A CN105555063 A CN 105555063A CN 201610062003 A CN201610062003 A CN 201610062003A CN 105555063 A CN105555063 A CN 105555063A
- Authority
- CN
- China
- Prior art keywords
- holes
- pcb
- hole
- etching
- multiplexing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention provides a multiplexing method for via holes on the same layer for a PCB, and relates to the manufacturing technology of the printed circuit board. The multiplexing method comprises the steps of drilling holes in L2-3 layers, performing PTH, pasting a drying film, exposing and developing; performing tin plating on the L2-3 layers after being developed; then removing the film and performing alkali etching; etching off a hole ring of a 201 hole close to the region of a 203 point through alkali etching; performing resin plugging for the etched L2-3; drilling a 702 hole, and performing PTH on the 702 hole; and then performing pattern transferring. The multiplexing method is used for solving the problem of insufficient wiring spacings in the design of the PCB; and signal shielding is provided for high-speed signals.
Description
Technical field
The present invention relates to a kind of printed circuit board (pcb) manufacturing technology, particularly relate to a kind of PCB with layer via hole multiplexing method.
Background technology
See in PCB manufactures, hole, line, face is three important elements forming PCB.But along with the development of electronics industry, PCB layout density is also more and more higher.More circuit is walked in less region becomes inevitable.Technique traditionally, a via hole half can only bear the effect of a signalling channel, and is limited to machining accuracy and the signal interference problem of PCB, is wiring forbidden zone around via hole in certain limit.This severely limits the development of PCB.In order to address this problem, the technology such as industry has invented buried via hole, blind hole, hole mesopore improve wiring density.
As Fig. 1, this is a kind of hole mesopore technology.This is four laminates, and in this applications, 101 is a hole, and he can be communicated with L2 and L3, and 102 is another one holes, and he can connect L1 and L4.Adding man-hour, L2-3 is a CORE, L2-3 carries out brill 101 hole, PTH, 101 hole filling holes with resin, and L2, L3 layer makes figure, and then L2-3 and L1, L4 carries out pressing, bores 102 holes again after pressing, 102 holes is carried out to the work flow of conventional PCB.So both can complete a hole mesopore technique.In such a process, the diameter in 101 holes is the diameters being greater than 102 holes.
Current this technique can utilize the part in the middle of 101 holes to make 102 holes, thus line density is walked in increase, realizes hole mesopore technique.But this technique also has a problem that cannot realize.He can only realize realizing hole recycling in different levels, then cannot realize for same level.As Fig. 2, if need to go further 202 holes in the middle of 201 holes of L2-3 layer, make according to the technique of hole mesopore before, consent after 201 hole PTH, bore 202 holes again, and then carry out PTH, graphic making, at this moment will find that the cabling in 202 holes and the cabling in 201 holes are short-circuited at 203, the orifice ring place in 202 holes.Therefore according to current technology, in same layer, via hole cannot be realized multiplexing.If need to need to increase cabling at L2-3 layer, space is not enough again, and traditionally mesopore technology in hole also cannot realize, and can only increase the quantity of buried via hole, and as Fig. 3, needing exactly to increase wiring density in L2-3 layer is the schematic diagram increasing buried via hole quantity.301 is buried via holes, if when wiring needs to increase cabling, just need increase by 302 hole.Due to the needs in space, in order to give 302 more regions, then the overall volume increasing PCB is needed to place 302 holes to provide enough spaces.Increase volume and current electronic equipment are toward lighter, and thinner developing direction is disagreed.
Summary of the invention
In order to solve this problem, the present invention proposes a kind of PCB with layer via hole multiplexing method, the hole that can be implemented in after using structure of the present invention on same layer is multiplexing.Solve the problem of wire distribution distance deficiency in day by day complicated PCB design.And provide signal shielding for high speed signal.
Technical scheme of the present invention is:
A kind of PCB is with layer via hole multiplexing method, and step is as follows:
1) first in the boring of L2-3 layer, PTH, pastes dry film, exposure imaging; The region that after development, dry film covers is the 203rd point, and the region that dry film covers is greater than the area of the wire in 202 holes and the orifice ring intersection in 201 holes, to reserve the fitment tolerance in the course of processing;
2) the L2-3 layer completing development carries out zinc-plated, then moves back alkali etching after film; By alkali etching, the orifice ring in 201 holes near 203 regions is etched away; Provide the cabling space of 202 hole wires.
3) filling holes with resin is carried out to completing the L2-3 after etching; All can by resin beyond the Great Wall in the region being removed copper by etching.
4) get out 702 holes, wherein 701 holes and 702 holes are equal to aforementioned 201 holes and 202 holes respectively; PTH is carried out for 702 holes, then carries out Graphic transitions.
The present invention is by optimizing PCB structural design.Following benefit can be brought:
1, improve the wiring density of PCB.More circuit can be established at less space lining with layer via hole is multiplexing.
2, the volume of PCB is reduced.More area is laid more circuit and mean that PCB can do less, thinner.This technology adapts to the trend of PCB.
3, this technology has certain first carrying out.
Accompanying drawing explanation
Fig. 1 is existing hole mesopore technology schematic diagram;
Fig. 2 is walking sky schematic diagram at L2-3 layer;
Fig. 3 needs to increase the schematic diagram that wiring density is increase buried via hole quantity in L2-3 layer;
Fig. 4 is the schematic diagram after development;
Fig. 5 is the view after etching;
Fig. 6 carries out filling holes with resin schematic diagram to completing the L2-3 after etching;
Fig. 7 is the schematic diagram getting out 702 holes.
Embodiment
More detailed elaboration is carried out to content of the present invention below:
By a kind of new PCB structure, solve the afoul problem of area of step space of lines and actual pcb board from the structure of PCB, for PCB provides more wiring space.Reduce thickness of slab and the volume of PCB, promote PCB to thinner, less future development.
If 1 will realize multiplexing with layer via hole at L2-3 layer.Present L2-3 layer boring, PTH, pastes dry film, exposure imaging.The region that after development, dry film covers is the 203rd point indicated in Fig. 2, and the region that dry film covers is larger than the area of the wire in 202 holes and the orifice ring intersection in 201 holes, to reserve the fitment tolerance in the course of processing.Fig. 4 is exactly the schematic diagram after development, and 401 in Fig. 4 is exactly 203 regions indicated in Fig. 2.
The L2-3 layer completing development carries out zinc-plated, then moves back alkali etching after film.Just the orifice ring in 201 holes near 203 regions can be etched away by alkali etching.Provide the cabling space of 202 hole wires.As Fig. 5 be exactly etching after state.
2, carry out filling holes with resin to completing the L2-3 after etching, as shown in Figure 6, the region that copper is removed by etching in 201 holes in fig. 2 and 501 shown in Fig. 5 all can by resin beyond the Great Wall.Be equal in figure 6 shown in 601.
3, as Fig. 7, get out 702 holes, wherein 701 holes and 702 holes are equal to 201 holes in Fig. 2 and 202 holes respectively.PTH is carried out for 702 holes, then carries out Graphic transitions.
After above the method disclosed in the present, can be clear that, hole mesopore can be applied at same layer, also just achieves same layer via hole multiplex technique.
Claims (3)
1. PCB is with a layer via hole multiplexing method, and it is characterized in that, step is as follows:
1) first in the boring of L2-3 layer, PTH, pastes dry film, exposure imaging; The region that after development, dry film covers is the 203rd point, and the region that dry film covers is greater than the area of the wire in 202 holes and the orifice ring intersection in 201 holes, to reserve the fitment tolerance in the course of processing;
2) the L2-3 layer completing development carries out zinc-plated, then moves back alkali etching after film;
3) filling holes with resin is carried out to completing the L2-3 after etching;
4) get out 702 holes, wherein 701 holes and 702 holes are equal to aforementioned 201 holes and 202 holes respectively; PTH is carried out for 702 holes, then carries out Graphic transitions.
2. method according to claim 1, is characterized in that, by alkali etching, the orifice ring in 201 holes near 203 regions is etched away; Provide the cabling space of 202 hole wires.
3. method according to claim 1, is characterized in that, all can by resin beyond the Great Wall in the region being removed copper by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610062003.7A CN105555063A (en) | 2016-01-29 | 2016-01-29 | Multiplexing method for via holes on same layer for PCB |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610062003.7A CN105555063A (en) | 2016-01-29 | 2016-01-29 | Multiplexing method for via holes on same layer for PCB |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105555063A true CN105555063A (en) | 2016-05-04 |
Family
ID=55833917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610062003.7A Pending CN105555063A (en) | 2016-01-29 | 2016-01-29 | Multiplexing method for via holes on same layer for PCB |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105555063A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104582319A (en) * | 2013-10-18 | 2015-04-29 | 珠海方正科技高密电子有限公司 | Metallized semi-hole forming method and printed circuit board manufacturing method |
CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
-
2016
- 2016-01-29 CN CN201610062003.7A patent/CN105555063A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104582319A (en) * | 2013-10-18 | 2015-04-29 | 珠海方正科技高密电子有限公司 | Metallized semi-hole forming method and printed circuit board manufacturing method |
CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103188886B (en) | A kind of printed circuit board and preparation method thereof | |
CN101286454B (en) | Printed circuit board producing method | |
US9417415B2 (en) | Interposer with polymer-filled or polymer-lined optical through-vias in thin glass substrate | |
US20140266549A1 (en) | Printed circuit board package structure and manufacturing method thereof | |
CN103369868B (en) | A kind of manufacture method of pcb board and pcb board | |
CN105101685B (en) | The preparation method and multi-layer PCB of a kind of multi-layer PCB | |
CN104754886A (en) | Pcb processing method and pcb | |
CN105025658A (en) | Mechanical backdrilling method for PCB | |
CN105792521B (en) | Pcb board pad Compensation Design technique and its application | |
JP2013118370A (en) | Via hole plating method and printed circuit board manufactured using the same | |
CN106455363A (en) | Printed circuit board manufacturing method and printed circuit board | |
CN105744740A (en) | Printed circuit board and method of manufacturing the same | |
CN108882558A (en) | The gold plating method and golden finger circuit board of golden finger | |
CN104640379A (en) | Printed circuit board and manufacturing method thereof | |
US20150014044A1 (en) | High speed via | |
CN101677493B (en) | Making method of circuit board and circuit structure | |
CN105555063A (en) | Multiplexing method for via holes on same layer for PCB | |
WO2023206958A1 (en) | Pcb signal via structure, and determination method, determination apparatus and determination device therefor | |
US20150008029A1 (en) | Circuit board and method of manufacturing the same | |
CN104023484A (en) | Manufacturing method of printed circuit board overlaid through hole structure | |
CN101160027B (en) | Method of producing circuit board and compound circuit substrates with through-hole plating structure | |
CN105451469A (en) | Circuit board golden finger manufacturing method | |
CN110392482A (en) | Circuit board | |
CN109874229B (en) | Manufacturing method of PCB stepped hole and PCB | |
CN107820360B (en) | Circuit boring guiding structure and board, printed circuit board manufacturing method with it |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160504 |