CN105553262A - 一种提高dc/dc升压变换器转换效率的方法 - Google Patents

一种提高dc/dc升压变换器转换效率的方法 Download PDF

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CN105553262A
CN105553262A CN201510961076.5A CN201510961076A CN105553262A CN 105553262 A CN105553262 A CN 105553262A CN 201510961076 A CN201510961076 A CN 201510961076A CN 105553262 A CN105553262 A CN 105553262A
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CN105553262B (zh
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黄胜明
黄鑫
冯多力
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Suzhou Regu Technology Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dc-Dc Converters (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种不会发生闩锁效应的提高DC/DC升压变换器转换效率的方法，除了原有的HS-LDMOS器件外，再增加一个面积很小的HS-LDMOS1器件，HS-LDMOS1的源极S1及栅极G1分别和HS-LDMOS的源极S及栅极G相连接；HS-LDMOS1的漏极D1则和N型深阱的欧姆接触区N+相连接，在这两个器件的体区(P-Body)到D1之间形成寄生二极管Diso；在HS-LDMOS的漏极D一侧N型外延层里紧靠N型深阱N+接触区的地方添加一个P+区，使之和N+接触区组成一个高压二极管HV-Diode。本发明主要应用于DC/DC升压变换器。

Description

一种提高DC/DC升压变换器转换效率的方法
技术领域
本发明涉及到一种DC/DC升压变换器，尤其涉及到一种提高DC/DC升压变换器转换效率的方法。
背景技术
众所周知，由于具有较高的转换效率和较好的可靠性，DC/DC变换器广泛应用于消费类电子产品和工业产品中。同步整流DC/DC变换器是电源管理电路应用的主要拓扑。在相同面积的情况下，P沟道MOSFET的导通电阻是N沟道MOSFET的2.5倍，为了提高电源管理电路的转换效率，开关和同步整流器件通常都应用N沟道器件的拓扑越来越受欢迎，特别是在电压高于12V的应用领域。图1所示是一个同步整流BOOST升压拓扑，下部的LS-LDMOS是开关器件，上部的HS-LDMOS是同步整流器件、且都是N型横向DMOS器件。由于任何时刻上、下两个器件不能同时导通，因此，它们的开关驱动信号高电平之间要留有死区(Dead-Time)。当LS-LDMOS导通时，电感电流线性增加，当LS-LDMOS截止时，在死区里电感电流流经HS-LDMOS的体二极管Db，到输出电容Cout上，提供负载电流。死区过后，HS-LDMOS导通，起到同步整流以及减小Db上功耗的作用。与此同时，电感电流开始下降。缩短死区时间有利于提高转换效率。利用典型的BCD工艺制造的HS-LDMOS器件的剖面结构如图2所示，在其版图设计上，用于HS-LDMOS源极隔离用的N型深阱(Deep-NWell)通常和其漏极D相连接，如图2(a)所示。这样，从P-Body的P+接触区、深阱接触区N+到P型衬底(P-Sub)形成了一个寄生的PNP双极晶体管。在上述提及的死区时间里，由于电流从HS-LDMOS的源极S经Db流向其漏极D，即S极的电位比D极的电位高出一个二极管的正向压降的电压，导致寄生PNP处于导通状态，从HS-LDMOS的源极向P型衬底注入电流，即此时器件的漏电流增加，造成能量损失。如果把N型深阱和HS-LDMOS的源极相连接，如图2(b)所示，在死区寄生PNP不会导通。但当LS-LDMOS处于导通、HS-LDMOS处于截止状态时，HS-LDMOS的源极和N型深阱被下拉至接近于地电位，如果该器件周围有高于PN结正向压降的P型区域存在，会导致其它可能到该N型深阱的寄生电流通路，特别是可能会诱发潜在的闩锁效应(Latch-up)。因此，对于这种连接，周围的版图设计需要至少三个P+/N+/P+环进行隔离，防止可能的Latch-up。这样一来，版图面积将会增加。
发明内容
本发明所要解决的技术问题是：提供一种不会发生闩锁效应的提高DC/DC升压变换器转换效率的方法。
为解决上述技术问题，本发明所采用的技术方案为：一种提高DC/DC升压变换器转换效率的方法，其步骤为：在DC/DC变换升压拓扑结构中的上端MOS器件采用N型的MOS或LDMOS器件，并将该N型的MOS或LDMOS器件动态隔离。
作为一种优选方案，在所述的一种提高DC/DC升压变换器转换效率的方法中，在DC/DC变换升压拓扑结构中的上端MOS器件采用N型LDMOS器件。
作为一种优选方案，在所述的一种提高DC/DC升压变换器转换效率的方法中，所述的上端MOS器件动态隔离的具体方法为：在上端MOS器件的体区到左侧的深阱欧姆连接区N+之间增加一个N型LDMOS器件、作为上端辅助MOS器件，上端辅助MOS器件的源极与上端MOS的源极相连，上端辅助MOS器件的栅极与上端MOS的栅极相连；上端辅助MOS器件的漏极与N型深阱的欧姆连接区N+相连接，从而在这上端MOS器件的体区与上端辅助MOS器件的漏极之间形成寄生二极管，在上端辅助MOS器件的漏极的右侧N型外延层里紧靠N型深阱N+连接区处设置一个P+区，使该P+区和右侧的深阱区的N+接触区组成一个高压二极管，所述上端MOS器件的体区与漏极之间形成一个体区二极管。
本发明的有益效果是：本发明除了原有的上端MOS器件(由N沟道MOS器件或者N沟道横向双扩散金属氧化物半导体器件即N型LDMOS)外，又增加一个面积很小的上端辅助MOS器件(由N沟道MOS器件或者N沟道横向双扩散金属氧化物半导体器件即N型LDMOS构成)，形成N型深阱非固定连接结构，从而有效地避免了闩锁效应的发生，并提高了DC/DC升压变换器的转换效率。
附图说明
图1是典型的同步整流Boost升压拓扑及功率器件驱动信号时序图。
图2是HS-LDMOS的剖面结构图，其中：(a)N型深阱和漏极相连，(b)N型深阱和源极相连。其中，从P-Body的P+接触区、深阱接触区N+到P型衬底(P-Sub)形成了一个寄生的PNP双极晶体管。
图3是本发明所述的HS-LDMOS的N型深阱的动态连接剖面结构图。
图4是图3所示的HS-LDMOS的N型深阱动态连接的等效电路图。
具体实施方式
下面结合附图，详细描述本发明所述的可提高DC/DC升压变换器转换效率的方法的具体实施方案：
如图3所示，其等效电路如图4所示，本发明所述的一种可提高DC/DC升压变换器转换效率的方法，除了原来的上端MOS器件(N沟道横向双扩散金属氧化物半导体器件)即图3和图4中的HS-LDMOS器件外，还增加一个面积很小的上端输助MOS器件(N沟道横向双扩散金属氧化物半导体器件)即图3和图4中的HS-LDMOS1器件，HS-LDMOS1的源极S1与HS-LDMOS的源极S相连，HS-LDMOS1的栅极G1与HS-LDMOS的栅极G相连接，HS-LDMOS1的漏极D1则与左侧N型深阱的欧姆接触区N+相连接，从而在HS-LDMOS的体区(P-Body)与HS-LDMOS1的漏极D1之间形成寄生二极管Diso，除此之外，在HS-LDMOS的漏极D一侧N型外延层里紧靠N型深阱N+接触区处设置一个P+区，使得该P+区和右侧的深阱区的N+接触区组成一个高压二极管HV-Diode，所述HS-LDMOS的漏极与体区(P-Body)形成体区二极管Db。在死区时间里，尽管二极管Db导通，HS-LDMOS的漏极D比其源极S低一个二极管压降，但是，从寄生二极管Diso到Vout也即HS-LDMOS的漏极D的电流通路被HV-Diode阻断，这样，寄生二极管Diso上无电流通过，左侧的N型深阱的电位高于HS-LDMOS的漏极电位，上述提及的寄生的双极PNP晶体管不会导通。死区过后，当HS-LDMOS的栅极是高电平时，N型深阱通过HS-LDMOS1和HS-LDMOS的源极连接在一起。当HS-LDMOS和HS-LDMOS1截止、LS-LDMOS导通时，尽管两个器件的源极S和S1被下拉至地电位，此时HS-LDMOS的漏极仍处于整个系统的最高电位(输出电压)，HV-Diode处于正向偏置状态，而寄生二极管Diso处于反偏状态，因此，HV-Diode中无电流，N型深阱的电位接近于此时的最高电位Vout。这样，寄生的双极PNP晶体管的漏电将被抑制，而且不会带来其它问题。
综上所述，仅为本发明的较佳实施例而已，并非用来限定本发明实施的范围，凡依本发明权利要求范围所述的形状、构造、特征及精神所作的均等变化与修饰，均应包括在本发明的权利要求范围内。

Claims (3)

1.一种提高DC/DC升压变换器转换效率的方法，其步骤为：在DC/DC变换升压拓扑结构中的上端MOS器件采用N型的MOS或LDMOS器件，并将该N型的MOS或LDMOS器件动态隔离。
2.根据权利要求1所述的提高DC/DC升压变换器转换效率的方法，其特征在于：在DC/DC变换升压拓扑结构中的上端MOS器件采用N型LDMOS器件。
3.根据权利要求2所述的提高DC/DC升压变换器转换效率的方法，其特征在于：所述的上端MOS器件动态隔离的具体方法为：在上端MOS器件的体区到左侧的深阱欧姆连接区N+之间增加一个N型LDMOS器件、作为上端辅助MOS器件，上端辅助MOS器件的源极与上端MOS的源极相连，上端辅助MOS器件的栅极与上端MOS的栅极相连；上端辅助MOS器件的漏极与左侧的N型深阱的欧姆连接区N+相连接，从而在该上端MOS器件的体区与上端辅助MOS器件的漏极之间形成寄生二极管，在上端辅助MOS器件的漏极的右侧N型外延层里紧靠N型深阱N+连接区处设置一个P+区，使该P+区和右侧的深阱区的N+接触区组成一个高压二极管，所述上端MOS器件的体区与漏极之间形成一个体区二极管。
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